Infineon XDPL8221 User manual

Design Guide Please read the Important Notice and Warnings at the end of this document V 1.0
www.infineon.com/XDP page 1 of 61 2019-1-23
DG_1711_PL21_1712_143020
XDPL8221 digital PFC + flyback controller IC
XDP™digital power
Ordering code: REF-XDPL8221-U100W
About this document
Scope and purpose
This document is a step-by-step guide to designing a high-performance dual-stage digital PFC + flyback AC-DC
converter using the XDPL8221 controller for LED lighting applications. The document also describes parameter
handling for typical Infineon use cases using the Infineon .dp Vision tool for the Infineon XDPL8221.
Intended audience
This document is intended for anyone wishing to design a high-performance dual-stage digital PFC + flyback
AC/DC-DC converter for LED lighting based on the XDPL8221 digital controller.
Table of contents
About this document....................................................................................................................... 1
Table of contents............................................................................................................................ 1
1Introduction .......................................................................................................................... 3
1.1 Product highlights...................................................................................................................................3
1.2 Design features........................................................................................................................................3
1.3 Target applications .................................................................................................................................3
1.4 Pin configuration and description..........................................................................................................4
2Hardware design.................................................................................................................... 6
2.1 System specification of a 100 W driver for LED lighting applications ...................................................6
2.2 Schematic................................................................................................................................................7
2.3 Bridge rectifier.........................................................................................................................................8
2.4 Design PFC boost converter....................................................................................................................8
2.4.1 Main PFC boost inductor....................................................................................................................8
2.4.2 PFC boost diode ...............................................................................................................................11
2.4.3 PFC power MOSFET..........................................................................................................................13
2.4.4 PFC MOSFET gate driver ..................................................................................................................13
2.4.5 PFC CS and ZCD................................................................................................................................14
2.4.6 PFC output voltage sense ................................................................................................................16
2.4.7 PFC output capacitor .......................................................................................................................18
2.4.8 PFC multi-mode control...................................................................................................................18
2.4.9 PFC start-up and steady-state control ............................................................................................20
2.4.10 Input voltage sensing.......................................................................................................................21
2.4.11 PFC protection features ................................................................................................................... 22
2.4.11.1 Bus voltage protection................................................................................................................23
2.4.11.2 Input voltage protection.............................................................................................................25
2.4.11.3 Over-current protection..............................................................................................................25
2.4.11.4 Soft-start failure..........................................................................................................................26

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2.4.11.5 CCM protection ...........................................................................................................................26
2.5 Designing the flyback converter ...........................................................................................................26
2.5.1 Designing the flyback transformer..................................................................................................27
2.5.1.1 Transformer turns ratio ..............................................................................................................27
2.5.1.2 Primary magnetizing inductance ...............................................................................................28
2.5.1.3 Flyback transformer winding turns............................................................................................30
2.5.2 Flyback primary power MOSFET......................................................................................................33
2.5.3 Flyback MOSFET gate driver ............................................................................................................34
2.5.4 Flyback primary snubber.................................................................................................................34
2.5.5 Flyback secondary rectifier diode ...................................................................................................36
2.5.6 Flyback secondary snubber.............................................................................................................37
2.5.7 Flyback secondary output capacitor...............................................................................................37
2.5.8 Flyback ZCD divider .........................................................................................................................38
2.5.9 Flyback CS resistor...........................................................................................................................39
2.5.10 Flyback operating window ..............................................................................................................40
2.5.11 Flyback multi-mode control ............................................................................................................42
2.5.12 Flyback start-up control...................................................................................................................43
2.5.13 Flyback protection features.............................................................................................................45
2.5.13.1 Flyback primary over-current protection ..................................................................................45
2.5.13.2 Flyback output under-voltage protection..................................................................................46
2.5.13.3 Flyback output over-voltage protection ....................................................................................46
2.5.13.4 Flyback output over-current protection ....................................................................................47
2.5.13.5 Flyback output over-power protection......................................................................................47
2.5.13.6 Flyback CCM protection..............................................................................................................47
2.5.13.7 Soft-start failure..........................................................................................................................48
2.5.13.8 Other flyback protections...........................................................................................................48
2.6 Design the power supply for XDPL8221................................................................................................48
2.7 Design the bleeder ................................................................................................................................50
2.8 Design the adaptive temperature protection ......................................................................................52
2.9 Design the dimming interface...............................................................................................................53
2.10 UART interface.......................................................................................................................................55
2.11 PCB layout guidelines ...........................................................................................................................55
2.11.1 Star connection of grounding..........................................................................................................55
2.11.2 Filtering capacitors of XDPL8221.....................................................................................................56
2.11.3 PFC voltage sense circuit ................................................................................................................. 56
2.11.4 Minimum current loop .....................................................................................................................56
2.11.5 Other layout considerations............................................................................................................56
3Configuration set-up and procedures ......................................................................................58
3.1 Design parameters ................................................................................................................................58
3.2 XDPL8221 configuration........................................................................................................................58
References....................................................................................................................................59
Revision history.............................................................................................................................60

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Introduction
1Introduction
The XDPL8221 digital controller IC belongs to the Infineon XDPTM digital power family. It provides an
independent PFC boost and flyback dual-stage control to achieve an output that combines Constant Voltage
(CV), Constant Current (CC) and Limited Power (LP) for LED luminaires. The IC is available in a PG-DSO-16
package and supports many features with only a minimal requirement of external components. The digital
engine of the IC offers the possibility to configure operational parameters and protection modes. This eases the
design phase and enables great product variety with a reduced number of hardware variants. Accurate
primary-side output voltage and current control eliminates a secondary-side feedback loop.
This design guide provides detailed information on how to calculate the major power stage component values,
as well as the setting of parameters for general functions and protection features. Useful tips on PCB layout are
included to help customers optimize their PCB design. Finally, the installation and use of a Graphical User
Interface (GUI) – .dp Vision – is described to guide the customer to set parameters for the digital IC. The numeric
values below are shown for the 100 W reference board with universal input voltage.
1.1 Product highlights
•UART command interface enables real-time communication for smart control applications
•Flicker-free dimming by analog reduction of output driving current down to 1 percent
•Primary-Side Regulated (PSR) CV, CC, LP output
•High current accuracy output of typically +/-2 percent across universal AC-DC input voltage range (90 Vrms
to 305 Vrms) with extended output voltage range from 16 V DC to 48 V DC
•Multi-mode flyback stage control (QRM + DCM + ABM) ensures high power efficiency over the entire load
range and low dimming output down to 1 percent of the full current
•High Power Factor (PF, greater than 0.9) and low input current Total Harmonic Distortion (iTHD, less than 15
percent) for AC and DC input up to 300 VRMS and load down to 30 percent
•Integrated 600 V start-up cell ensures fast time to light and low power consumption
•Adapted external temperature protection
1.2 Design features
•Universal AC input (120 V to 277 V AC +/-10 percent) or DC input (120 V to 430 V DC +/-10 percent)
•Extended output voltage range from 16 V to 48 V DC
•Recommended power range from 25 W to 150 W
1.3 Target applications
•Driver for LED luminaires

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Figure 1 XDPL8221 typical application schematic
1.4 Pin configuration and description
Pin assignments and basic pin description information are shown below.
Figure 2 Pin configuration of XDPL8221
Table 1 Pin definitions and functions
Name Pin Type Function
GDFB 1 O Flyback gate drive output
Output for directly driving a power MOSFET of the flyback converter via a resistor
CSFB 2 I Flyback Current Sense (CS) input
Connected to an external shunt resistor and the source of a power MOSFET of the
flyback converter
VCC 3 I Positive power supply

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IC power supply
GND 4 - Ground
IC ground
ZCD 5 I Flyback Zero-Crossing Detection (ZCD)
Connected to the flyback auxiliary winding via a resistive divider for ZCD as well as
primary-side output voltage sensing for output regulation and back-up bus voltage
sensing for safety
VS 6 I PFC voltage sense
Connected to the DC bus via a resistive divider for the PFC boost converter output
voltage sensing
N.U. 7 - Not used, to be connected to GND externally
HV 8 I High voltage input
Connected to the AC mains via external rectifier diode and resistor. An internal 600 V
HV start-up cell is used to charge VCC initially. In addition, sampled HV sensing is also
used for AC/DC detection and brown-out.
PWM 9 I PWM dimming
PWM pin is used as a dimming input
TEMP 10 I External temperature sensor
Connected to an external NTC resistor to sense the environment temperature
CSPFC 11 I PFC current sensing
Connected to an external shunt resistor and the source of a power MOSFET of the
PFC boost converter. Additionally, it is connected to the PFC auxiliary winding for
ZCD.
N.U. 12 I/O Not used, to be connected to GND externally
GDPFC 13 O PFC gate drive output
Output for directly driving a power MOSFET of the PFC boost converter via a resistor
UART 14 - Universal Asynchronous Receiver Transmitter (UART) communication
The UART pin is used for the UART interface to support parameterization
N.C. 15 - Not connected. To be connected externally to GND.
N.C. 16 - Not connected. To be connected externally to GND.

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2Hardware design
The hardware design part provides detailed calculations of power component values as well as the setting of
parameters of general functions and protection features for both PFC boost and flyback converters. Useful tips
on PCB layout are included to help customers optimize their PCB design.
The design example used in this hardware design part is a 100 W CC mode driver reference design for direct
driving of LED lighting applications. The customer can easily apply their own target specifications according to
this example and obtain the design parameters by themselves.
2.1 System specification of a 100 W driver for LED lighting applications
The system specification of a 100 W driver reference design for LED lighting applications is shown as follows:
Table 2
Parameter Symbol Target value Unit
Input characteristic
Nominal input AC voltage (RMS) Vin_AC 120 to 300 V AC
Nominal input DC voltage Vin_DC 120 to 300 V DC
Nominal output DC voltage VOUT 16 to 48 V DC
Nominal output DC current IOUT 550 to 2500 mA
Nominal output power PO100 W
Power factor PF More than 0.9
THD iTHD Less than 15 %
Power efficiency ɳ Less than 89 %
PFC stage
PFC MOSFET maximum drain-source voltage VDS_PFC 600 V
Maximum PFC stage output power PO_PFC 110 W
Minimum PFC switching frequency fsw,min_PFC 22 kHz
Maximum PFC switching frequency fsw,max_PFC 80 kHz
Flyback stage
Nominal input voltage V DC 460 V DC
Maximum output power PO100 W
Nominal output over-voltage threshold VOUT,OV 53 V
Flyback MOSFET maximum drain-source voltage VDS_FB 800 V
Minimum switching frequency fsw,min 16 kHz

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2.2 Schematic
Figure 3 XDPL8221 100 W driver schematic

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2.3 Bridge rectifier
The bridge rectifier usually has the highest semiconductor power loss in the PFC boost converter. Using a higher
rated current bridge rectifier can reduce the forward voltage drop, which reduces the total power dissipation at
a small incremental cost. The total power loss is calculated using the average input current flowing through two
of the bridge rectifying diodes if the forward voltage is assumed as 1 V:
_ =_ ∗2∗_ = 2√2
∗__ __∗ ɳ ∗2∗_ = 2.71W
With the value of the power loss, an appropriate bridge rectifier should be selected based on its thermal
characteristics.
2.4 Design PFC boost converter
PFC shapes the input current of the power supply to synchronize with the mains voltage, in order to maximize
the real power drawn from the mains. In a perfect PFC circuit, the input current follows the input voltage as a
pure resistor, without any input current harmonics. In the 100 W driver reference design, PFC is implemented as
a boost converter that works in Quasi-Resonant Mode (QRM) with constant on-time control. The converter
provides the following flyback stage a constant high DC voltage as input, which ensures flicker-free light output.
This chapter describes the methodology for designing the QRM PFC boost converter based on the XDPL8221,
including PFC boost inductor design, equations for power loss estimation, and a selection guide for power
semiconductor devices and passive components.
2.4.1 Main PFC boost inductor
As the key magnetic component of the PFC boost converter, the boost inductor has the main function of energy
storage. Its inductance is given as the following formula:
 =_
∗(−_) ∗ ɳ
4∗∗_∗
Where
•LPFC – Inductance of the PFC boost inductor
•Vin_pk – Peak value of the input AC mains
•Vbus – Bus voltage as the PFC output
•ηPFC – Estimated power efficiency of the PFC boost converter
•PO_PFC – Output power of the PFC boost converter
•fPFC – Operation switching frequency of the PFC boost inductor
In the 100 W driver reference design, the output of the PFC boost converter is chosen as 460 V so that a high PF is
still guaranteed at the maximum AC/DC input. The minimum switching frequency limited at 22 kHz to avoid
audible noise is controlled by XPDL8221 through a “maximum switching period time-out” approach, which starts
the next switching cycle when 45 µs of maximum switching period is reached. The detailed variable values are
given in Table 3.

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Table 3 PFC design specification
Parameter Symbol Value Unit
AC or DC input under-voltage threshold VUV_rms 76 V
AC or DC input over-voltage threshold VOV_rms 320 V
Maximum PFC boost converter output power PO_PFC_max 110 W
Maximum PFC on-time ton,max_PFC 32 µs
Minimum PFC on-time ton,min_PFC 200 ns
Minimum switching frequency fsw,min_PFC 22 kHz
Estimated PFC boost converter power efficiency
at maximum AC input voltage
ηPFC Less than or equal
to 96
%
Nominal PFC boost converter output voltage Vbus 460 V
Power factor PF More than 0.9 –
The maximum possible inductance should be calculated at both lowest (input under-voltage threshold) and
highest (input over-voltage threshold) possible input voltage with full load and minimum switching frequency.
At 76 V AC input:
_ =76 ∗ √2∗460 − 76 ∗ √2∗ 0.96
4 ∗ 460 ∗ 110 ∗ 22 ∗ 10≈0.88 
At 320 V AC input:
_ =320 ∗ √2∗ (460 − 320 ∗ √2) ∗ 0.96
4 ∗ 460 ∗ 110 ∗ 22 ∗ 10≈1.15 
The suitable inductance must be less than the smaller one of both.
 <,
Other considerations regarding PFC choke inductance:
•The selected PFC inductance must be small enough to cover the maximum output power at the minimum
input (e.g. to cover the brown-in/out feature).
•Higher PFC inductance has the advantage at light load in comparison to smaller inductance due to longer on-
time. This ensures smaller minimum output power in DCM when the LED load is small (e.g. 1 percent dimming)
and avoids unwanted bus voltage ripples due to the limited minimum on-time of the IC controller.
•For the maximum output power, higher PFC inductance has longer on-time and lower switching frequency. It
must be guaranteed that these two parameters are still within the limits of the XDPL8221.
•Higher PFC inductance leads to a larger choke size and more winding turns, which causes more winding loss.
In contrast, lower inductance results in smaller size and fewer winding turns but higher frequency, which
could lead to more switching loss.
In the reference design, LPFC = 0.6 mH is chosen to avoid magnetic saturation in worst cases such as start-up and
load transient. After the PFC choke inductance has been fixed, the relevant choke parameters can be calculated
as follows with the assumption of the boundary conduction mode operation:
Maximum input current (RMS) happens at minimum AC input and maximum output power:
__ =__
_∗ ɳ =1.5 

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Maximum input peak current: __ =√2∗__ =2.12 
Maximum inductor peak current: ,__ =2∗__ =4.24 
Figure 4 Boost inductor current waveform in a switching cycle
According to Figure 4, other important parameters of the PFC boost converter can be calculated as follows if
QRM1 operation is assumed:
Maximum on-time: _ = ∗,__
√2∗_ =23 μ
If Tosc = 1.5 µs is assumed, off-time at minimum AC input and maximum output power:
 =∗,__
− √2∗_+0.5∗ =7.97 μ
The lowest frequency for maximum output power of PFC converter in QRM:
_ =1
_+ =32.3 
Maximum current (RMS) through the PFC inductor during on-time:
,___ = 2 ∗ __∗1
3∗_∗_ =1.49 
Maximum current (RMS) through the PFC inductor during off-time:
,___ = 2 ∗ __∗1
3∗∗_ =0.84 
Thus the maximum PFC inductor current (RMS):
__ =,___
+,___ =1.71 

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To realize the ZCD of the inductor current for the quasi-resistant mode switching, an additional auxiliary winding
is introduced in the PFC inductor. It is recommended to keep the maximum voltage across the auxiliary winding
below 50 V, which is proportional to the maximum voltage drop across the PFC inductor main winding. This must
comply with the maximum voltage rating of the components that are connected to the auxiliary winding. In the
100 W reference design, a turns ratio of 10:1 is used.
The important parameters of the PFC boost inductor are summarized in Table 4.
Table 4 PFC boost inductor design parameters
PFC boost converter
Parameter Symbol Value Unit
Main inductance of the PFC boost inductor LPFC 600 µH
Minimum switching frequency in QRM fPFC_min 32.3 kHz
Maximum inductor peak current IL,pk_PFC_max 4.24 A
Maximum input current (RMS) Iin_rms_max 1.5 A
Maximum input peak current Iin_pk_max 2.12 A
Maximum inductor current (RMS) IL_rms_max 1.71 A
Maximum on-time ton_max 23 µs
Turns ratio of primary to auxiliary winding Np_PFC/Na_PFC 10:1 –
Based on the calculated specifications above, the inductor can be constructed according to different design
requirements such as size, power efficiency, temperature, etc. by selecting different bobbins and cores. In order
to avoid core saturation and achieve an optimized core loss, the flux density Bmax is recommended not to exceed
0.3.
In the Infineon 100 W driver reference design, the PFC boost inductor is constructed by Würth Elektronik using
part no. 750343236 as a design example. The specification sheet is given in Table 5.
Table 5 Parameters of Würth inductor 750343236
Parameter Value Unit
Inductance 600 µH
Bobbin ETD34 –
Core material TP4A or DMR44 –
Turns ratio of primary to auxiliary winding 10:1 –
DC resistance primary winding 0.13 Ω
DC resistance auxiliary winding 0.033 Ω
Saturation current 4.3 A
The maximum main inductor copper loss can be calculated based on the specification above as:
__ =__
∗__ = 0.38 W
2.4.2 PFC boost diode
The selection of the boost diode is a major decision in the PFC boost converter design and it is related to the
converter efficiency. The following considerations should be taken into account:

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•Reverser breakdown voltage
It must be chosen to be higher than the bus voltage with at least 20 percent margin:
__ <1.2∗_ =582 
A 600 V diode is suitable here in the 100 W reference design.
•Average rectified forward current
It must be higher than the PFC boost converter output current:
__ >__
_ = 0.275 
Using a diode with high current capability will benefit the power efficiency.
•Forward voltage
It is directly related to the power efficiency. So the forward voltage should be chosen to be as small as possible.
•Reverse recovery time
As the PFC boost converter is controlled by the XDPL8221 in the QRM + DCM mode, the PFC boost diode current
goes back to zero while the PFC MOSFET turns on. So there is no current commutation between the PFC diode
and MOSFET and thus no switching loss by reverse recovery. It is not necessary to choose an ultra-fast diode.
•Power loss
The only power loss that should be considered is conduction loss. The maximum PFC diode current (RMS) is
calculated as:
___ =
4
3∗2 ∗ √2 π∗__
_∗_ = 0.73 A
With a forward voltage of 0.5 V assumed, the diode conduction loss can be calculated as follows:
__ =___ ∗__ = 0.365 W
•Thermal characteristics
With the thermal resistance of the diode RD_PFC_TH_JA and ambient temperature TA, the PFC diode temperature
without heatsink is calculated as: _ =__ ∗___+ 
The important parameters for the boost diode used in the 100 W driver reference design are summarized in
Table 6.
Table 6 Boost diode design parameters
Parameter Symbol Value Unit
Maximum reverse voltage VRRM_D_PFC 600 V
Average rectified forward current ID_PFC_avg 4 A
Maximum PFC diode RMS current ID_PFC_rms_max 0.73 A
Forward voltage VF_D_PFC 0.5 V

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2.4.3 PFC power MOSFET
The selection of the PFC power MOSFET is based mainly on consideration of the breakdown voltage and power
dissipation. According to the operating bus voltage, a 600 V MOSFET is suitable. In the QRM + DCM mode PFC
boost converter, the overall MOSFET losses comprise:
•Conduction loss
These losses are frequency independent and do not scale significantly with frequency. It is calculated as follows:
___ =,___∗()
•Turn-on transition loss
As the converter works in QRM + DCM mode, the turn-on transition loss caused by the magnetizing current can
be ignored because the current rises from zero when a switching cycle starts. But to discharge the parasitic
capacitors like Coss and Ccan through the MOSFET channel can cause significant turn-on transition loss. These
losses occur every switching cycle and are thus frequency dependent.
•Eoss and 1/2∙Ccan∙V2loss
As mentioned above, the energy stored in Ccan and Coss at the time of turn-on must be dissipated in the MOSFET
channel and CS resistor during the turn-on transition. The energy stored in any capacitor is fundamentally a
function of the square of the voltage across it, and thus the Eoss and ½∙Ccan∙V2losses can be very significant during
high-line conditions. These losses occur every switching cycle and are thus frequency dependent. To simplify the
calculation, we assumed that the switching loss is approximately half of the conduction loss:
___ =1
2∗___
•Gate driver loss
These losses also scale linearly with frequency, but are generally quite a small contribution to the overall losses
(at switching frequencies of below 100 kHz) and depend almost exclusively on the MOSFET Qg (total gate-charge).
The gate-driver power is typically dissipated in the external gate resistor and gate-driver itself and thus does not
need to be considered in the thermal calculation of the MOSFET.
In the 100 W driver reference design, the 600 V Infineon MOSFET IPA60R190C6 from the C6 family is used. With
the RDS(on) of 190 mΩ, the total loss of the MOSFET is calculated as:
__ = ___ + ___ =1.5∗___ =0.63 
The important parameters for the PFC MOSFET are summarized in Table 7.
Table 7 PFC MOSFET design parameters
Parameter Symbol Value Unit
Breakdown voltage VBR_DSS_PFC 650 V
MOSFET on-resistance RDS(on) 190 mΩ
PFC MOSFET conduction loss Ploss_MOS_PFC_con 0.42 W
PFC MOSFET switching loss Ploss_MOS_PFC_sw 0.21 W
PFC MOSFET total loss Ploss_MOS_PFC 0.63 W
2.4.4 PFC MOSFET gate driver
The XDPL8221 PFC boost converter gate driver GDPFC offers the following advanced features:

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Hardware design
•Configurable charge current from 30 to 118 mA for turn-on slope optimization with .dp Vision tool
•Configurable gate voltage from 4.5 to 15 V
Figure 5 Configurable gate driver with gate voltage and charge current
Due to the configurable gate charge current and voltage, the external gate resistor should not be chosen to be
too high. A gate resistor of 10 Ωshould fit most application cases. The soft turn-on for improved EMI results is
guaranteed by the configurable constant current gate charging. The following table shows the recommend range
of the external gate resistor for a stable gate-drive operation of different MOSFETs:
Table 8 Recommended external gate resistor value
Parameter Symbol Value Unit
MOSFET gate capacitance Cg 1.0 to 2.0 nF
MOSFET gate source current Igs 100 mA
MOSFET gate source resistance Rgs 10 100 kΩ
Recommended external gate
resistor
Rg 5 ~ 20 15 ~ 25 Ω
2.4.5 PFC CS and ZCD
The pin CSPFC of the XDPL8221 is used for two different purposes in one switching cycle. During the on-time of
the PFC MOSFET, it is used as a CS pin. The CS of the PFC boost converter is used to limit the turn-on time of the
PFC MOSFET by sensing the peak current flowing through the MOSFET in order to protect it and also the boost
inductor from an over-power situation. When the MOSFET is turned off, the pin is used as a ZCD pin. The ZCD
catches the moment when the boost inductor current goes back to zero and the next switching cycle can be
started so that the boost converter always works in the QRM or DCM mode with minimum switching loss.
As Figure 6 shows, when the PFC MOSFET turns on, the rectifier diode D1blocks the negative voltage drop across
the PFC auxiliary winding so that the CSPFC pin is effectively connected only to the shunt resistor RCS_PFC via the
resistor RZCD2_PFC and thus only sees the peak CS voltage signal. When the PFC MOSFET turns off, a positive voltage
drop is forwarded by D1. The CSPFC pin is effectively connected to resistor divider RZCD1_PFC and RZCD2_PFC. A zener
diode and a capacitor are necessary to clamp the pin voltage not higher than 3.3 V. Another diode is required to
decouple the CS signal from the clamping circuit.

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Figure 6 Schematic of shared CS and ZCD functions at the CSPFC pin
The ratio of the resistor divider RZCD1_PFC and RZCD2_PFC decides the amplitude of the oscillation at the CSPFC pin. So
that the comparator for the ZCD works correctly, the amplitude at the CSPFC pin must be higher than 1.53 V as
shown in Figure 7. The ratio of the divider must be designed theoretically, as follows:
−__∗_
_∗_ _+_ >1.54 
Attention: The bus voltage ripple and the parasitic resistance of the winding which leads to the damping
of the amplitude should be also taken into account if necessary. A wrongly designed divider
ratio will cause the loss of the PFC ZCD signal.
Figure 7 Hysteretic comparator threshold for ZCD
To design the PFC CS shunt resistor, the following condition must be complied with:
,__∗ <__ =1.214 

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and
_ <1.214
,__ = 0.28 Ω
The value of the CS resistor is chosen to be 0.165 Ω with two resistors of 0.33 Ω connected in parallel. This splits
the power dissipation and reduces the thermal stress. The maximum power loss of each shunt resistor is:
___ =0.5 ∗ __
∗ _ =0.5∗1.71∗ 0.33= 0.48 
This should be considered while selecting the proper shunt resistor type.
The important design parameters for bus voltage sensing are summarized in Table 9.
Table 9 PFC CS and ZCD design parameters
Parameter Symbol Value Unit
Upper resistor of the PFC ZCD divider RZCD1_PFC 8.2 kΩ
Lower resistor of the PFC ZCD divider RZCD2_PFC 33 kΩ
PFC OCP1 maximum operating range VOCP1_PFC_max 1.214 V
PFC CS resistor RCS_PFC 0.33//0.33 =
0.165
Ω
2.4.6 PFC output voltage sense
As shown in Figure 8, the bus voltage is measured at the VS pin of the XDPL8221 through a resistor divider. This
measurement is used as the input of the PFC output voltage regulator to generate the PWM control signal for the
PFC MOSFET and offers the protection functions for the PFC boost converter. It is strongly recommended to add
a filter capacitor near the VS pin to filter the switching noise in order to get a precise and stable measurement
result. The VS pin has a very low leakage current so the intolerance can be ignored.
Figure 8 Bus voltage measurement
Inside the XDPL8221, the VS pin is connected to an 8-bit ADC, which utilizes two voltage ranges for the bus voltage
measurement results. This gives the advantage on the one hand that the whole voltage range started from 0 V is
monitored. On the other hand the operating range is sensed with a high resolution so that the regulation
accuracy is guaranteed.
As shown in Figure 9, the wide voltage range from 0 to VREF results in a low resolution. If the nominal operating
bus voltage Vbus = 460 V is assumed in normal operation and mapped to VREF by the resistor divider as
recommended, then an 8-bit ADC gives the range 0 ~ 460 V a resolution of:
  =
256 ≈1.8 /

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This range is used to monitor the start-up behavior or other failures.
The narrow voltage range from 5/6 VREF to 7/6 VREF gives a three times better resolution. If the nominal operating
bus voltage Vbus = 460 V is assumed and mapped to VREF, then an 8-bit ADC gives the range from 5/6*Vbus = 383 V
to 7/6* Vbus = 536 V a resolution of:
  =1
3∗ 256 ≈0.6 /
So in the steady-state operation, the high-resolution range is used to get an accurate bus voltage regulation.
Figure 9 Bus voltage sensing ranges
The calculation of the resistor divider is given as follows if the Vbus = 460 V is mapped to VREF:
_
_ =−  = 188.46
To reduce the inaccuracy caused by the resistor divider, it is necessary to select the bus voltage sensing resistors
with a tolerance of 1 percent or less. In the 100 W driver reference design, to reduce the voltage stress, the upper
resistor RVS1_PFC consists of three resistors each of 3.32 MΩ, and the lower resistor RVS1_PFC is selected as 52.3 kΩ.
Note: As indicated in the XDPL8221 datasheet, the VCC pin voltage must be higher than 3.4 V before the
voltage of VS exceeds 1.2 V. So it is recommended to select the divider with the highest impedance.
This also helps to reduce the power consumption in standby mode.
The criteria to switch between these two ranges are as follows if the tolerance of the resistors can be ignored:
•The PFC boost converter always starts in the narrow (high resolution) range.
•In the narrow (high resolution) range, if the bus voltage Vbus is less than 406 V, it will be switched to wide range.
•In the wide (low resolution) range, if the bus voltage Vbus is more than 430 V, it will be switched to the narrow
range.
Note: In order to reduce the switching noise coupled in the bus voltage sense signal, a filter capacitor of
1 nF is strongly recommended to be placed near the VS pin.
The important design parameters for bus voltage sensing are summarized in Table 10.
Table 10 Bus voltage sensing design parameters

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Parameter Symbol Value Unit
Nominal PFC boost converter output voltage Vbus 460 V
XDPL8221 internal ADC reference voltage VREF 2.428 V
Bus voltage sensing divider upper resistor RVS1_PFC 3.32 x 3 MΩ
Bus voltage sensing divider lower resistor RVS2_PFC 52.3 kΩ
Bus voltage sensing filter capacitor CVS 1 nF
Narrow (high resolution) range – 383 ~ 536 V
Resolution of narrow range – 0.6 V/LSB
Wide (low resolution) range – 0 ~ 460 V
Resolution of wide range – 1.8 V/LSB
2.4.7 PFC output capacitor
The PFC bus capacitor can be calculated with the following formula if the ESR of the capacitor is small enough to
be neglected and the peak-to-peak voltage ripple is selected as 20 V. Please note that the tolerance of 20 percent
of the capacitance also needs to be taken into account:
 = __
2∗∗_∗ __ ∗ 1.2=46 μ
With:
__ =__
 =0.24 
Regarding the voltage rating with consideration of over-voltage protection threshold, a 500 V capacitor is
necessary. But due to price and size factors, it is reasonable to use two 250 V rating capacitors in series. The ESR
of the capacitor should be selected to be as small as possible, and the allowed maximum ripple current should
have enough margin. In the 100 W driver reference design, one 500 V capacitor of 47 µF with low ESR is selected.
To symmetrize the voltage stress on the two in series-connected capacitors, an in-parallel connected high-ohmic
resistor divider is recommended, which will slightly increase the standby power consumption.
The important parameters for the bus capacitor selection are summarized in Table 11.
Table 11 Bus capacitors design parameters
Parameter Symbol Value Unit
Nominal PFC boost converter output voltage Vbus 460 V
Maximum PFC boost converter output power Pout_PFC_max 110 W
Bus voltage ripple (peak to peak) Vbus_ripple_pp 20 V
AC input line frequency fline 45 ~ 66 Hz
PFC bus capacitor Cbus 47 µF
2.4.8 PFC multi-mode control
The PFC boost converter regulates the output bus voltage through the calculated constant on-time:
_ =2∗__∗
_
∗ ɳ

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As shown from the formula above, when the inductance is fixed and the line input voltage is constant, the PFC
on-time is only dependent on the converter output power. The output voltage is sensed and fed into the internal
regulator for on-time calculation. With the calculated on-time and frequency law, a switching cycle is defined.
For a PFC boost converter operating in QRM, the PFC MOSFET is turned on with constant on-time throughout the
complete AC half-cycle, and the off-time varies during the AC half-cycle depending on the instantaneous input
voltage applied. A new switching cycle starts after the inductor current reaches zero. It is ideal for full-load
operation, where the on-time is long. However, the on-time reduces at light load, resulting in very high switching
frequency especially near the zero-crossings of the AC input. The high switching frequency increases the
switching loss, resulting in poor efficiency at light load. Therefore multi-mode control is implemented.
The XDPL8221 uses QRM + DCM operation for PFC load regulation. At full load and heavy load, the PFC is running
with QRM1 for the best power efficiency. When the load decreases, the XDPL8221 reduces the on-time and
switching frequency at the same time by adding an additional delay into each switching cycle through selecting
further inductor current valleys to achieve QR2M and up to maximum QRM5 (configurable) operation. Figure 10
illustrates the QRM2 valley switching in multi-mode PFC control as an example. In case of light load e.g. deep
dimming, DCM operation with fixed on-time is applied to further reduce the power transfer: the adjustment of
the switching period will regulate the load change and the switching frequency can be reduced.
Figure 10 PFC boost multi-mode control with QRM2
The multi-mode control is defined in the frequency law, which consists of a maximum switching frequency
fsw_PFC_max and a minimum switching frequency fsw_PFC_min and controls the valley selection (QRMn). In this way, the
switching frequency is limited within the defined range, and efficiency at light load can be improved. An
illustration of the frequency law is shown in Figure 11.
Figure 11 Frequency law for operating mode
Switching between QRM and DCM operation is described in Figure 12.

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•PFC will enter DCM operation from QRM once the internal calculated on-time is smaller than ton_dcm_PFC
•PFC will leave DCM operation and return to QRM once the switching frequency is higher than fsw_max_dcm_PFC
Figure 12 Mode switching between QRMn and DCM operation
The important design parameters for multi-mode control are summarized in the following table:
Table 12 Input voltage sensing design parameters
Parameter Symbol Value Unit
Maximum PFC boost converter switching frequency fsw_max_PFC 80 kHz
Minimum PFC boost converter switching frequency fsw_min_PFC 22 kHz
Minimum on-time to enter DCM operation ton_dcm_PFC 300 ns
Maximum frequency to leave DCM operation fsw_max_dcm_PFC 150 kHz
Maximum allowed valley Nvalley_max_PFC 8 –
2.4.9 PFC start-up and steady-state control
After the AC or DC voltage is applied at the input, the bus voltage is charged by the bridge rectifier and PFC diode.
The VCC capacitors are charged by the HV start-up cell until the VCC on-threshold is reached and the XDPL8221 is
active. After activation, the XDPL8221 checks first if the bus voltage is higher than Vbus_start_PFC (brown-in condition).
The PFC boost converter begins with the soft-start phase once the condition is fulfilled. After the threshold
Vbus_steady_entry_UV is reached within the time tstart_max_PFC, the start-up phase is over and the controller will switch to
the steady-state operation until the operating bus voltage value Vbus_set is reached. Once the bus voltage is still
lower than the threshold beyond the time, the PFC soft-start failure will be triggered. This is shown in Figure 13.
The XDPL8221 PFC stage uses the PIT1 (Proportional-Integral-T1) controller to control the bus voltage in start-
up and steady-state operation:
•Term P is proportional to the bus voltage error (difference between current bus voltage value and the
operating nominal bus voltage value)
•Term I accounts for past values of the bus voltage error and integrates them over time to produce the I-term