Infineon OPTIREG TLF30681QVS01 User manual

OPTIREG™ PMIC TLF30681QVS01
Power management IC
Features
•High-eiciency step-down pre-regulator for wide input voltage range from
3.7 V to 35 V (40 V limited time) with low overall power loss and fast
transient performance
• Suitable for operation with ceramic capacitors
•High-eiciency step-down post-regulator for second output voltage
generation
• Step-up post-regulator with 5 V output voltage
• Voltage monitoring for two external voltage rails including enable signals
• 16-bit SPI
• Configurable window watchdog
• Green Product (RoHS compliant)
Potential applications
• Automotive applications
• Advanced Driver Assistance Systems (ADAS)
- 77 GHz radar ECUs
- Camera ECUs
• Human Machine Interface (HMI) applications
Product validation
Qualified for automotive applications. Product validation according to AEC-Q100.
Description
The OPTIREG™ PMIC TLF30681QVS01 is a multiple rail Power Management IC (PMIC) for automotive
applications, optimized for the use in Advanced Driver Assistance Systems (ADAS). The device consists of a
battery connected buck regulator (Buck1) providing 3.3 V to external loads and to two low voltage post-
regulators. The first post-regulator (Buck2) provides an output voltage of 1.25 V (output voltage adjustment via
SPI in the range of 0.9 V to 1.3 V). The second post-regulator (Boost1) provides an output voltage of 5.0 V and is
intended to supply up to two CAN transceivers. The TLF30681QVS01 supports 16-bit SPI communication to a
microcontroller. SPI commands can read status information from the device and control features of the power
regulators, such as PWM synchronization. The device operates at a nominal switching frequency of 2.2 MHz. The
switching frequency is selectable via SPI from 1.8 MHz to 2.5 MHz in steps of 100 kHz. The switching regulators
can synchronize to an external clock signal. The TLF30681QVS01 can provide a synchronization signal for other
DC/DC regulators in the system. The TLF30681QVS01 provides two voltage monitoring channels with
Datasheet Please read the Important Notice and Warnings at the end of this document Rev. 1.0
www.infineon.com/OPTIREG-PMIC 2020-04-08

monitoring inputs and enable outputs. The monitoring channels can be used to control and monitor external
LDOs or external DC/DC switching regulators.
Type Package Marking
TLF30681QVS01 PG-VQFN-48 TLF30681 S01
OPTIREG™ PMIC TLF30681QVS01
Power management IC
Description
Datasheet 2 Rev. 1.0
2020-04-08

Table of contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Potential applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.2 Pin definitions and functions PG-VQFN-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2 Functional range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3 Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 Quiescent current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5 Typical performance characteristics quiescent current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4 Power converters and power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1 High voltage step-down regulator Buck1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1.1 Functional description Buck1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.1.2 Electrical characteristics Buck1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.1.3 Typical performance characteristics Buck1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.2 Post-regulator step-down converter Buck2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.2.1 Functional description Buck2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.2.2 Electrical characteristics Buck2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
4.2.3 Typical performance characteristics Buck2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.3 Post-regulator step-up converter Boost1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
4.3.1 Functional description Boost1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.3.2 Electrical characteristics Boost1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
4.3.3 Typical performance characteristics Boost1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4.4 Support of external voltage rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.4.1 Electrical characteristics support of external voltage rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5 Central functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1 Supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.1 Electrical characteristics supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
5.2 Enable functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.1 ENA pin configurability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.2.2 Electrical characteristics enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.2.3 Typical performance characteristics enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
OPTIREG™ PMIC TLF30681QVS01
Power management IC
Table of contents
Datasheet 3 Rev. 1.0
2020-04-08

5.3 Power sequencing and so start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.1 Electrical characteristics power sequencing and so start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5.4 Frequency generation and clock synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.4.1 Electrical characteristics frequency generation and clock synchronization . . . . . . . . . . . . . . . . . .42
5.4.2 Typical performance characteristics frequency generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.5 IOVDD - overvoltage detection and undervoltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
5.5.1 Electrical characteristics IOVDD - overvoltage detection and undervoltage detection . . . . . . . . 45
6 Monitoring functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1 Voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.1 Monitoring of R1VSx battery supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.1.2 Monitoring of output voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.1.3 Monitoring of external voltage rails . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.4 Monitoring of internal supply voltages and bandgaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.5 Electrical characteristics voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
6.2.1 Electrical characteristics temperature sensor monitoring block . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7 Microcontroller interface and supervisory functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.1 Microcontroller interface supply IOVDD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
7.1.1 Electrical characteristics microcontroller interface supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7.2 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.2.1 SPI introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
7.2.2 SPI write access to protected registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
7.2.3 SPI write initiated state transition request and regulator configuration . . . . . . . . . . . . . . . . . . . . .58
7.2.4 Configuration of Buck2 output voltage via SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
7.2.5 SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
7.2.6 Electrical characteristics SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7.2.7 Electrical characteristics SPI timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
7.3 Reset generation (ROT signal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
7.3.1 Electrical characteristics ROT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
7.4 Interrupt generation (INT signal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.4.1 Electrical characteristics INT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.5 Window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
7.5.1 Window watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.5.2 Electrical characteristics window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
7.6 Microcontroller programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
7.6.1 Electrical characteristics microcontroller programming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
8 State machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8.1 State machine introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
8.2 Operation states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
8.3 State transitions and trigger signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.4 Electrical characteristics state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
OPTIREG™ PMIC TLF30681QVS01
Power management IC
Table of contents
Datasheet 4 Rev. 1.0
2020-04-08

9 SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
9.1 SPI register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
9.1.1 Device configuration registers (device startup default configuration) . . . . . . . . . . . . . . . . . . . . . . .87
9.1.1.1 Register DEVCFG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
9.1.1.2 Register CLKCFG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
9.1.1.3 Register CLKCFG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
9.1.1.4 Register PWDCFG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
9.1.1.5 Register PWDCFG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
9.1.1.6 Register PWDCFG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
9.1.2 Read-only registers for protected configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
9.1.2.1 Register RWDCFG0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
9.1.2.2 Register RWDCFG1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
9.1.2.3 Register RWDCFG2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
9.1.3 Protected device configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.1.3.1 Register DEVCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
9.1.3.2 Register DEVCTRLN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
9.1.3.3 Register B2VCTRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
9.1.3.4 Register B2VCTRLN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
9.1.4 General registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9.1.4.1 Register PROTCFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
9.1.4.2 Register WWDSCMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.1.5 Event status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
9.1.5.1 Register GSF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
9.1.5.2 Register SYSSF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
9.1.5.3 Register SYSSF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
9.1.5.4 Register MCUSF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.1.5.5 Register MCUSF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
9.1.5.6 Register SPISF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
9.1.5.7 Register MONSF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
9.1.5.8 Register MONSF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
9.1.5.9 Register MONSF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
9.1.5.10 Register OTSF0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
9.1.5.11 Register OTSF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
9.1.5.12 Register OCSF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
9.1.6 Device status information registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
9.1.6.1 Register OTSTAT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
9.1.6.2 Register VMONSTAT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
9.1.6.3 Register DEVSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
9.1.6.4 Register PROTSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
9.1.6.5 Register WWDSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
9.1.6.6 Register MPSSTAT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
OPTIREG™ PMIC TLF30681QVS01
Power management IC
Table of contents
Datasheet 5 Rev. 1.0
2020-04-08

9.1.6.7 Register B2VSTAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
9.1.7 Device information registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
9.1.7.1 Register HWDECT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
9.1.7.2 Register DEVID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
10 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
11 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
OPTIREG™ PMIC TLF30681QVS01
Power management IC
Table of contents
Datasheet 6 Rev. 1.0
2020-04-08

1 Block diagram
Logic
SMPR
Buck1
Feedback
SPI
ENABLE
ENABLE
Fault
Manager
V_S (T30)
TM1
AG2
WDI
SDO
SDI
SCL
SCS
ENA
R1VSx
Window
Watchdog
Reset Generator
INT
ROT
INTERRUPT
Generator
Bandgap 2
for V- Mon.
Bandgap 1
SMPR
Buck2 V_Buck2
Feedback
R2SWx
R2PGx
R2FB
V_Buck1
R1SWx
R1PGx
R1FB
NC
R2VS1x
R1BTS
UV/OV-Monitoring/
Enable Handling
Internal
Supply
SPI_DataIn
SPI_Clock
SPI_ChipSelect
SPI_DataOut
Watchdog_TriggerIn
µC_Reset
Interrupt
ExtRail1_Feedback
ExtRail1_Enable
VM1EN
VM1FB
ExtRail2_Feedback
ExtRail2_Enable
VM2EN
VM2FB
Clock
Generation SYNCO
SYNCI SYNC_In
SYNC_Out
MPS
R3SW
SMPR
Boost R3PG
V_Boost
Feedback
R3FB
AG3
IOVDD
AG4 AG5
R1BTSV
Interface_supply
NC
TM2
AG1
R3VS
Buck1
Driver
Supply
AG6
Figure 1 Block diagram
OPTIREG™ PMIC TLF30681QVS01
Power management IC
Block diagram
Datasheet 7 Rev. 1.0
2020-04-08

2 Pin configuration
2.1 Pin assignment
Top View
E
R1PG3 12
VM2FB 48
SDO 37
13 R1SW1
24 R2PG2
25 R2SW1 36 SYNCI
E
E
E
SCL 39
SCS 40
ROT 41
INT 42
WDI 43
TM2 44
VM1EN 45
VM2EN 46
VM1FB 47
SDI 38
22 R2FB
21 AG4
20 R1FB
19 AG3
18 AG2
17 AG1
16 R1BTS
15 R1SW3
14 R1SW2
23 R2PG1
34 IOVDD 33 MPS 32 TM1 31 R3FB
30 R3PG1 29 R3SW1 28 R2VS2 27 R2VS1 26 R2SW2
35 SYNCO
R1PG1 10
R1VS3 9
R1VS2 8 R1VS1 7
ENA 6
NC 5
R1BTSV 4
AG6 3
NC 2
AG5 1
R1PG2 11
Figure 2 Pin configuration
OPTIREG™ PMIC TLF30681QVS01
Power management IC
Pin configuration
Datasheet 8 Rev. 1.0
2020-04-08

2.2 Pin definitions and functions PG-VQFN-48
Pin Symbol Function
1 AG5 Analog ground, pin 5:
Connect this pin directly to ground via a low ohmic and low inductive trace.
2 NC Not connected:
Leave the pin floating in the application.
3 AG6 Analog ground, pin 6:
Connect this pin directly to ground via a low ohmic and low inductive trace.
4 R1BTSV Decoupling of internal supply voltage:
Connect a decoupling capacitor between this pin and R1PGx.
5 NC Not connected:
Leave this pin floating in the application.
6 ENA Enable input:
A valid enable condition at this pin enables the device.
7 R1VS1 High voltage regulator supply voltage, pin 1:
Connect this pin in parallel with R1VS2 and R1VS3 and then to the supply (battery)
voltage via a reverse protection diode. Additionally connect a capacitor between this
pin and ground. An EMC filter is recommended.
8 R1VS2 High voltage regulator supply voltage, pin 2:
Connect this in parallel with R1VS1 and R1VS3 and then to the supply (battery) voltage
via a reverse protection diode. Additionally connect a capacitor between this pin and
ground. An EMC filter is recommended.
9 R1VS3 High voltage regulator supply voltage, pin 3:
Connect this pin in parallel with R1VS1 and R1VS2 and then to the supply (battery)
voltage via a reverse protection diode. Additionally connect a capacitor between this
pin and ground. An EMC filter is recommended.
10 R1PG1 High voltage regulator power ground, pin 1:
Connect this pin in parallel with R1PG2 and R1PG3 and then to the Buck1 output
capacitor ground terminal to ground.
11 R1PG2 High voltage regulator power ground, pin 2:
Connect this pin in parallel with R1PG1 and R1PG3 and then to the Buck1 output
capacitor ground terminal to ground.
12 R1PG3 High voltage regulator power ground, pin 3:
Connect this pin n parallel with R1PG1 and R1PG2 and to the Buck1 output capacitor
ground terminal to ground.
13 R1SW1 High voltage regulator power stage output, pin 1:
Connect this pin in parallel with R1SW2 and R1SW3 and then to the pre-regulator Buck1
output filter inductor.
14 R1SW2 High voltage regulator power stage output, pin 2:
Connect this pin in parallel with R1SW1 and R1SW3 and then to the pre-regulator
output filter inductor.
OPTIREG™ PMIC TLF30681QVS01
Power management IC
Pin configuration
Datasheet 9 Rev. 1.0
2020-04-08

Pin Symbol Function
15 R1SW3 High voltage regulator power stage output, pin 3:
Connect this pin in parallel with R1SW1 and R1SW2 and then to the pre-regulator
output filter inductor.
16 R1BTS Bootstrap supply voltage:
Connect this pin via the bootstrap capacitor to the R1SWx pins.
17 AG1 Analog ground, pin 1:
Connect this pin directly to ground via a low ohmic and low inductive trace.
18 AG2 Analog ground, pin 2:
Connect this pin directly to ground via a low ohmic and low inductive trace.
19 AG3 Analog ground, pin 3:
Connect this pin directly to ground via a low ohmic and low inductive trace.
20 R1FB High voltage regulator output voltage feedback:
Connect this pin to the Buck1 output capacitor.
21 AG4 Analog ground, pin 4:
Connect this pin directly to ground via a low ohmic and low inductive trace.
22 R2FB Post-regulator output voltage feedback:
Connect this pin to the Buck2 output capacitor.
23 R2PG1 Pre-regulator power ground, pin 1:
Connect this pin in parallel with R2PG2 and then to the Buck2 output capacitor ground
terminal to ground.
24 R2PG2 Pre-regulator power ground, pin 2:
Connect this pin in parallel with R2PG1 and then to the Buck2 output capacitor ground
terminal to ground.
25 R2SW1 Post-regulator power stage output, pin 1:
Connect this pin in parallel with R2SW2 and then to the Buck2 output filter inductor.
26 R2SW2 Post-regulator power stage output, pin 2:
Connect this pin in parallel with R2SW1 and then to the Buck2 output filter inductor.
27 R2VS1 Post-regulator supply voltage, pin 1:
Connect this pin to the Buck1 output capacitor.
In order to compensate for disturbances, add a local bypass capacitor.
28 R2VS2 Post-regulator supply voltage, pin 2:
Connect this pin to the Buck1 output capacitor.
In order to compensate for disturbances, add a local bypass capacitor.
29 R3SW1 Regulator 3 power stage output, pin 1:
Connect this pin to Boost1 inductor and external rectifying diode.
30 R3PG1 Regulator 3 power ground, pin 1:
Connect this pin to Boost1 output capacitor ground terminal to ground.
31 R3FB Regulator 3 output voltage feedback pin:
Connect this pin to Boost1 output capacitor.
OPTIREG™ PMIC TLF30681QVS01
Power management IC
Pin configuration
Datasheet 10 Rev. 1.0
2020-04-08

Pin Symbol Function
32 TM1 Test mode 1:
Not for customer use. Leave this pin floating in the application.
33 MPS Microcontroller programming mode
Connect this pin to ground for normal operation in the application. Optionally the pin
can be used for microcontroller programming purposes, see Application information.
34 IOVDD I/O supply voltage:
Connect this pin to the I/O supply voltage of the microcontroller.
Add a decoupling capacitor.
35 SYNCO Synchronization output:
Optional: Connect this pin to an external switch-mode post-regulator synchronization
input. This pin delivers the internal switching frequency signal, either in phase or
shied by 180°, depending on the settings via SPI. The switch-mode post-regulator
synchronizes to the rising edge.
If this pin is not used, then leave it floating.
36 SYNCI Synchronization input:
Connect this pin to an optional external synchronization signal to synchronize the
switching of the internal switch-mode regulators. The feature needs to be enabled via
SPI.
If the pin is not used, then leave it floating.
37 SDO Serial peripheral interface, signal data output:
SPI signalling port;
connect this pin to the SPI port "data input" of the microcontroller to send status
information during SPI communication.
38 SDI Serial peripheral interface, signal data input:
SPI signalling port;
connect this pin to the SPI port "data input" of the microcontroller to receive status
information during SPI communication.
39 SCL Serial peripheral interface, signal clock input:
SPI signalling port;
connect this pin to the SPI port "clock" of the microcontroller to clock the device for SPI
communication.
40 SCS Serial peripheral interface, signal chip select:
SPI signalling port;
connect this pin to the SPI port "chip select" of the microcontroller to address the
device for SPI communication.
41 ROT Reset output:
Open drain structure with internal pull up resistor.
"Low" indicates a reset event for the microcontroller.
Connect this pin to the microcontroller reset input.
42 INT Interrupt output:
OPTIREG™ PMIC TLF30681QVS01
Power management IC
Pin configuration
Datasheet 11 Rev. 1.0
2020-04-08

Pin Symbol Function
Push-pull output. A "low" pulse at this pin indicates an interrupt, and the
microcontroller reads the SPI status registers.
Connect this pin to a non-maskable interrupt port (NMI) of the microcontroller.
43 WDI Watchdog input, trigger signal:
Connect this pin to the "trigger signal output" of the microcontroller.
This pin has an internal pull-down.
If this pin is not used, then leave it floating.
44 TM2 Test mode 2:
Not for customer use. Connect this pin to GND in the application.
45 VM1EN Enable signal for external voltage rails 1:
Connect this pin to the enable pin of an optional external voltage regulator 1.
If the external regulator is not used, then connect this pin to ground.
46 VM2EN Enable signal for external voltage rails 2:
Connect this pin to the enable pin of an optional external voltage regulator 2.
If the external regulator is not used, then connect this pin to ground.
47 VM1FB Input for optional external voltage monitoring rail 1:
Connect this pin to an external resistor divider to adjust the overvoltage threshold and
the undervoltage threshold of the monitored external voltage generated by the
optional external voltage regulator 1.
If the optional external regulator is not used, then connect this pin to ground.
48 VM2FB Input for optional external voltage monitoring rail 2:
Connect this pin to an external resistor divider to adjust the overvoltage threshold and
the undervoltage threshold of the monitored external voltage generated by the
optional external voltage regulator 2.
If the optional external regulator is not used, then connect this pin to ground.
Cooling tab GND Cooling tab:
Internally connected to GND.
– EP1 Edge pin 1:
Keep the area below this pin free of ground or other signals. Do not solder this pin to
ground or any other signal. This pin must be kept free of soldering.
– EP2 Edge pin 2:
Keep the area below this pin free of ground or other signals. Do not solder this pin to
ground or any other signal. This pin must be kept free of soldering.
– EP3 Edge pin 3:
Keep the area below this pin free of ground or other signals. Do not solder this pin to
ground or any other signal. This pin must be kept free of soldering.
– EP4 Edge pin 4:
Keep the area below this pin free of ground or other signals. Do not solder this pin to
ground or any other signal. This pin must be kept free of soldering.
OPTIREG™ PMIC TLF30681QVS01
Power management IC
Pin configuration
Datasheet 12 Rev. 1.0
2020-04-08

3 General product characteristics
3.1 Absolute maximum ratings
Table 1 Absolute maximum ratings1)
Tj = -40°C to 150°C; all voltages with respect to ground, positive current flowing into pin, (unless otherwise
specified)
Parameter Symbol Values Unit Note or condition Number
Min. Typ. Max.
Pin
MPS VMPS -0.3 – 6.0 V – P_3.1.1
IOVDD VIOVDD -0.3 – 6.0 V – P_3.1.2
SCS VSCS -0.3 – 6.0 V – P_3.1.3
SCL VSCL -0.3 – 6.0 V – P_3.1.4
SDI VSDI -0.3 – 6.0 V – P_3.1.5
SDO VSDO -0.3 – 6.0 V – P_3.1.6
WDI VWDI -0.3 – 6.0 V – P_3.1.7
INT VINT -0.3 – 6.0 V – P_3.1.10
AG1 VAG1 -0.3 – 0.3 V – P_3.1.13
AG2 VAG2 -0.3 – 0.3 V – P_3.1.14
AG3 VAG3 -0.3 – 0.3 V – P_3.1.15
AG4 VAG4 -0.3 – 0.3 V – P_3.1.16
AG5 VAG5 -0.3 – 0.3 V – P_3.1.17
AG6 VAG6 -0.3 – 0.3 V – P_3.1.18
SYNCI VSYNCI -0.3 – 6.0 V – P_3.1.19
SYNCO VSYNCO -0.3 – 6.0 V – P_3.1.20
TM1 VTM1 -0.3 – 6.0 V – P_3.1.22
ENA VENA -0.3 – 35 V 2) P_3.1.23
ENA IENA -5.0 – – mA – P_3.1.24
R1BTS VR1BTS VR1SWx - 0.3 – VR1SWx + 6.0 V – P_3.1.25
R1BTSV VR1BTSV -0.3 – 6.0 V – P_3.1.26
R1VS1 VR1VS1 -0.3 – 35 V 2) P_3.1.27
R1VS2 VR1VS2 -0.3 – 35 V 2) P_3.1.28
1Not subject to production test, specified by design.
2Maximum rating is extended to 40 V for an overall time of 7 minutes during the lifetime of the product
(load dump requirement).
OPTIREG™ PMIC TLF30681QVS01
Power management IC
General product characteristics
Datasheet 13 Rev. 1.0
2020-04-08

Table 1 Absolute maximum ratings1) (continued)
Tj = -40°C to 150°C; all voltages with respect to ground, positive current flowing into pin, (unless otherwise
specified)
Parameter Symbol Values Unit Note or condition Number
Min. Typ. Max.
R1VS3 VR1VS3 -0.3 – 35 V 2) P_3.1.29
R1SW1 VR1SW1 -0.3 – VR1VSx + 2.0 V – P_3.1.30
R1SW2 VR1SW2 -0.3 – VR1VSx + 2.0 V – P_3.1.31
R1SW3 VR1SW3 -0.3 – VR1VSx + 2.0 V – P_3.1.32
R1PG1 VR1PG1 -0.3 – 0.3 V – P_3.1.33
R1PG2 VR1PG2 -0.3 – 0.3 V – P_3.1.34
R1PG3 VR1PG3 -0.3 – 0.3 V – P_3.1.35
R1FB VR1FB -0.3 – 7.0 V – P_3.1.36
R2VS1 VR2VS1 -0.3 – 7.0 V – P_3.1.37
R2VS2 VR2VS2 -0.3 – 7.0 V – P_3.1.38
R2SW1 VR2SW1 -0.3 – 7.0 V – P_3.1.39
R2SW2 VR2SW2 -0.3 – 7.0 V – P_3.1.40
R2PG1 VR2PG1 -0.3 – 0.3 V – P_3.1.41
R2PG2 VR2PG2 -0.3 – 0.3 V – P_3.1.42
R2FB VR2FB -0.3 – 7.0 V – P_3.1.43
R3SW1 VR3SW1 -0.3 – 7.0 V – P_3.1.44
R3PG1 VR3PG1 -0.3 – 0.3 V – P_3.1.45
R3FB VR3FB -0.3 – 7.0 V – P_3.1.46
VM1FB VVM1FB -0.3 – 6.0 V – P_3.1.47
VM1EN VVM1EN -0.3 – 6.0 V – P_3.1.48
VM2FB VVM2FB -0.3 – 6.0 V – P_3.1.49
VM2EN VVM2EN -0.3 – 6.0 V – P_3.1.50
ROT VROT -0.3 – 6.0 V – P_3.1.51
TM2 VTM2 -0.3 – 6.0 V – P_3.1.52
Temperatures
Junction temperature Tj-40 – 150 °C – P_3.1.53
Storage temperature Tstg -55 – 150 °C – P_4.1.9
ESD susceptibility
1Not subject to production test, specified by design.
2Maximum rating is extended to 40 V for an overall time of 7 minutes during the lifetime of the product
(load dump requirement).
OPTIREG™ PMIC TLF30681QVS01
Power management IC
General product characteristics
Datasheet 14 Rev. 1.0
2020-04-08

Table 1 Absolute maximum ratings1) (continued)
Tj = -40°C to 150°C; all voltages with respect to ground, positive current flowing into pin, (unless otherwise
specified)
Parameter Symbol Values Unit Note or condition Number
Min. Typ. Max.
ESD susceptibility all pins VESD,HBM -2 – 2 kV HBM3) P_4.1.10
ESD susceptibility all pins VESD,CDM -500 – 500 V CDM4) P_4.1.12
ESD susceptibility of corner
pins to GND
VESD,Corne
r
-750 – 750 V CDM4) P_4.1.13
Notes:
1. Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute
maximum rating conditions for extended periods of time may aect device reliability.
2. Integrated protection functions are designed to prevent IC destruction under fault conditions described in
the data sheet. Fault conditions are considered as outside the normal operating range. Protection functions
are not designed for continuous repetitive operation.
3.2 Functional range
Table 2 Functional range
Parameter Symbol Values Unit Note or condition Number
Min. Typ. Max.
Supply voltage range for
normal operation
VR1VSx 5.0 – 35 V 5) P_3.2.1
Supply voltage range for
reduced operation
VR1VSx 3.7 – 5.0 V 5)6) P_4.2.5
Junction Temperature Tj-40 – 150 °C – P_4.2.9
Note: Within the functional or operating range, the IC operates as described in the circuit description. The
electrical characteristics are specified within the conditions given in the electrical characteristics
table.
1Not subject to production test, specified by design.
3ESD susceptibility, HBM according to ANSI/ESDA/JEDEC JS001 (1.5k Ω, 100 pF).
4ESD susceptibility, Charged Device Model "CDM" according JEDEC JESD22-C101.
5When first powered up, a proper startup of the device can only be ensured by applying minimum 6 V at
pins R1VSx for at least 2 ms. The device may start at even lower voltages.
6The current capability of Buck1 is reduced to limit the current stress in the device.
OPTIREG™ PMIC TLF30681QVS01
Power management IC
General product characteristics
Datasheet 15 Rev. 1.0
2020-04-08

3.3 Thermal resistance
Table 3 Thermal resistance7)
Parameter Symbol Values Unit Note or condition Number
Min. Typ. Max.
Junction to case RthJC – – 12.2 K/W – P_4.3.1
Junction to soldering point
(pin)
RthJSP 20.1 – 22.1 K/W JEDEC 2s2p,
measured to pin 1, 3,
17, 18, 19, 21
P_3.3.1
Junction to soldering point
(pin)
RthJSP 34.9 – 37.6 K/W JEDEC 1s0p,
measured to pin 1, 3,
17, 18, 19, 21
P_3.3.2
Junction to soldering point
(soldering pad)
RthJSP 11.0 – 14.7 K/W JEDEC 2s2p P_3.3.3
Junction to soldering point
(soldering pad)
RthJSP 13.1 – 18.0 K/W JEDEC 1s0p P_4.3.2
Junction to ambient RthJA – 37 – K/W 8) P_4.3.3
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information
visit www.jedec.org.
7Not subject to production test, specified by design.
8Specified RthJA value is according to JEDEC JESD51-2,-5,-7 at natural convection on FR4 2s2p board; the
product (chip and package) was simulated on a 76.2 × 114.3 × 1.5 mm3 board with two inner copper layers
(2 × 70 µm Cu, 2 × 35 µm Cu). Where applicable, a thermal via array next to the package contacted the first
inner copper layer.
OPTIREG™ PMIC TLF30681QVS01
Power management IC
General product characteristics
Datasheet 16 Rev. 1.0
2020-04-08

3.4 Quiescent current
Table 4 Quiescent current
Tj = -40°C to 150°C; VR1VSx = 9 V to 25 V; unless otherwise specified
Parameter Symbol Values Unit Note or condition Number
Min. Typ. Max.
ACTIVE state Iq,OP – – 20 mA Tj ≤ 85°C;
9 V ≤ VR1VSx ≤ 25 V;
no load, watchdog
disabled
P_3.4.1
DISABLED state Iq,DIS – 13 17.5 µA Tj ≤ 85°C;
9 V ≤ VR1VSx ≤ 25 V
P_3.4.2
DISABLED state Iq,DIS – 11 13.5 µA Tj = 25°C;
VR1VSx = 13.5 V
P_3.4.3
FAULT state Iq,FLT – 1 2 mA Tj ≤ 85°C;
9 V ≤ VR1VSx ≤ 25 V
P_3.4.4
LOCKED state Iq,LCK – 35 50 µA Tj ≤ 85°C;
9 V ≤ VR1VSx ≤ 25 V
P_3.4.5
OPTIREG™ PMIC TLF30681QVS01
Power management IC
General product characteristics
Datasheet 17 Rev. 1.0
2020-04-08

3.5 Typical performance characteristics quiescent current
DISABLED state - quiescent current Iq versus
supply voltage VR1VSx
LOCKED state - quiescent current Iq versus
supply voltage VR1VSx
OPTIREG™ PMIC TLF30681QVS01
Power management IC
General product characteristics
Datasheet 18 Rev. 1.0
2020-04-08

4 Power converters and power management
4.1 High voltage step-down regulator Buck1
4.1.1 Functional description Buck1
The high-voltage step-down regulator Buck1 converts the battery voltage R1VSx to the Buck1 voltage.
A synchronous, current-mode-controlled buck converter with internal power switches is integrated for this
purpose. The output rail VBuck1 can be used as direct supply rail as well as pre-regulated rail for post-
regulators.
An integrated driver circuit supplied by an external boot-strap capacitor drives the N-/N-MOS power stage. The
integrated dead-time optimization prevents cross-conduction, minimizes dead-time and increases system
eiciency. An internal voltage divider sets the output voltage. Internal compensation allows for fast loop
performance across a wide range of output capacitance. No external tuning of the loop is required. The device
supports ceramic capacitors as well as electrolytic capacitors. For detailed information on the selection of the
external power stage components, such as the inductor and the filter capacitors for input and output, see
Application information.
The converter oers various configuration options:
• Switching frequency selectable via SPI
• Synchronization of the switching frequency to other integrated converters as well as to an external
synchronization signal
• Protection features that are designed to prevent damage to the converter due to fault conditions, such as:
- Overcurrent detection
- Overtemperature detection
OPTIREG™ PMIC TLF30681QVS01
Power management IC
Power converters and power management
Datasheet 19 Rev. 1.0
2020-04-08

Logic
Pre-
Regulator
Buck1
Feedback
Bandgap 1
V_Buck1
R1SWx
R1PGx
R1FB
R1BTS
Clock
Generation SYNCO
SYNCI SYNC_In
SYNC_Out
R1VSx
Vbat
Figure 3 Functional block diagram Buck1
Modulation concept
The converter uses several modulation schemes, depending on the operation mode. It uses a PWM scheme in
most of the operating area. It supports synchronization to internal and external clock sources. For light-load
and high-line operation it uses pulse-skipping operation. This allows for an improved system eiciency and
ensures a minimum turn-on time to ensure correct operation of the switches.
The converter handles the transition between PWM and pulse-skipping automatically, with the need to
configure this. The current thresholds and voltage thresholds for this transition depend on the selected power
stage components.
Loop compensation
The converter uses a cascaded current-mode, voltage-mode control scheme. An inner loop controls the
inductor current, while the external voltage compensation loop regulates the output voltage. The
compensation loop can operate with a variety of power stages. For information on the selection of the external
components see Application information. The dynamic performance of the system is a function of the power
stage components and the internal compensation loop. To achieve optimum performance, follow the design
considerations in Application information.
Cycle-by-cycle current limitation
The device features cycle-by-cycle current limitation to protect the switches and external components in case of
a fault condition. If the current reaches a defined current threshold, then the peak current monitoring turns o
the high-side switch. The device also monitors the current in the low side switch. If the current in the low side
switch exceeds the overcurrent threshold at the end of the switching period, then the device does not turn on
the high side switch in the subsequent switching period. This allows the device to work as a constant current
source.
OPTIREG™ PMIC TLF30681QVS01
Power management IC
Power converters and power management
Datasheet 20 Rev. 1.0
2020-04-08