Infineon XDPL8218 Guide

Design Guide Please read the Important Notice and Warnings at the end of this document V 1.0
www.infineon.com/XDPL8218 page 1 of 48 2018-06-06
DG_1711_PL21_1802_031149
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
About this document
Scope and purpose
This document is a design guide using XDPL8218 as the control IC of the front-stage High Power Factor (HPF)
flyback converter, which regulates the secondary output voltage supply to the second-stage Constant Current
(CC) converter for LED lighting applications.
Intended audience
Power supply design engineers, field application engineers.
Table of contents
About this document....................................................................................................................... 1
Table of contents............................................................................................................................ 1
1Introduction .......................................................................................................................... 3
2Design specifications.............................................................................................................. 5
3Transformer design................................................................................................................ 6
4Flyback MOSFET and secondary main output diode selection...................................................... 8
5CS resistor and GD pin-related design......................................................................................10
6MOSFET maximum current cycle-by-cycle limit and start-up phase design ..................................11
7HV pin-related design ............................................................................................................14
8VCC capacitance and output UVP design....................................................................................15
9Output OVP-related design.....................................................................................................17
10 DC link filter and secondary main output capacitance ...............................................................18
11 Input voltage levels for start-up and protection .......................................................................19
12 ZCD pin-related design...........................................................................................................20
13 Secondary-side regulation FB circuit design.............................................................................22
14 Regulated mode parameters ..................................................................................................26
14.1 Digital notch filter..................................................................................................................................26
14.2 On-time limit and switching frequency limit (QRM1/DCM) .................................................................26
14.3 ABM FB voltage sensing and control ....................................................................................................27
14.4 FB voltage mapping and mode transition............................................................................................28
14.5 FB voltage maximum limit ramp ..........................................................................................................29
15 Other protection-related parameters......................................................................................30
15.1 VCC OVP...................................................................................................................................................30
15.2 Regulated mode VCC UVP.......................................................................................................................30
15.3 IC over-temperature protection ...........................................................................................................30
15.4 Primary MOSFET over-current protection............................................................................................30
15.5 Debug mode ..........................................................................................................................................31
16 PCB layout guide...................................................................................................................32

Design Guide 2 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
Introduction
17 Parameter configuration list, set-up and procedures ................................................................33
17.1 Parameter configuration list.................................................................................................................33
17.2 Parameter configuration set-up ...........................................................................................................34
17.3 Parameter configuration procedures...................................................................................................35
18 Fine-tuning guide..................................................................................................................38
18.1 Input voltage-sensing parameter fine-tuning......................................................................................38
18.2 QR valley switching parameter fine-tuning..........................................................................................39
18.3 Input power quality related parameter fine-tuning ............................................................................41
19 Debugging guide ...................................................................................................................42
19.1 Pin signal debugging.............................................................................................................................42
19.2 Firmware status code read-out procedures with debug mode...........................................................45
20 References ...........................................................................................................................46
Revision history.............................................................................................................................47

Design Guide 3 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
Introduction
1Introduction
XDPL8218 regulates Constant Voltage (CV) output of a HPF flyback converter, according to its feedback (FB) pin
voltage signal, which is controlled by the secondary-side regulation FB circuit via an isolated optocoupler, as
shown in Figure 1.
CoolMOS™
XDPL8218
Feedback
Circuit
VCC
CS
GD
ZCD
CV Output
HV
FB
GND UART
AC Input
voltage
Figure 1 XDPL8218 flyback converter simplified circuitry with secondary-side regulated CV output
For LED lighting applications, XDPL8218 flyback CV output usually is converted to a CC output by a second-
stage DC-DC switching or linear regulator.
XDPL8218 comes in a PG-DSO-8 package with eight pins, as shown in the datasheet [1]. The main functions of
each pin are shown in Table 1.
Table 1 XDPL8218 pins assignment
Pin
Symbol
Type
Pin name and main functions
1
ZCD
Input
Zero Crossing Detection pin:
Transformer auxiliary winding ZCD via external resistor/divider
Sensing of the reflected input and output voltage signals from auxiliary winding
via external resistors divider
2
FB
Input
Feedback pin:
Feedback voltage sensing for secondary-side output regulation
3
CS
Input
Current Sense pin:
Flyback MOSFET current sensing via external shunt resistor
4
GD
Output
Gate Drive pin:
Flyback MOSFET gate-drive control via external series resistor
5
HV
Input
High Voltage pin:
VCC charging via its internal 600 V start-up cell during start-up and protection
Rectified AC input voltage sensing via external series resistor for line
synchronization

Design Guide 4 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
Introduction
Pin
Symbol
Type
Pin name and main functions
6
UART
Input
/Output
Universal Asynchronous Receiver Transmitter pin:
Digital communication interface for IC parameter configuration
7
VCC
Input
Voltage at Common Collector pin:
IC operating voltage supply and sensing
8
GND
–
Ground pin:
IC grounding
XDPL8218’s IC parameters are configurable digitally via its UART interface, using Infineon’s user-friendly
Graphical User Interface (GUI) on a PC. This enables a lower Bill of Materials (BOM) and rapid engineering
changes without the need for complex component design iterations.
Note: By default, the configurable parameters of a new XDPL8218 chip from Infineon are empty, so it is
necessary to configure them before any application testing.
Figure 2 shows the XDPL8218 design guide document sectioning for each step of the recommended design
flow.
Figure 2 XDPL8218 design guide document sectioning for each step of the recommended design
flow
XDPL8218
system design
(Refer to section
2 to 16)
Create system
based on system design
(Refer to section 17 for
IC parameterization
setup and procedures)
Power up system
(If any problem, refer
to section 19 for
debugging guide)
Performance check
and optimization
(Refer to section
18 for fine-tuning
guide)

Design Guide 5 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
Design specifications
2Design specifications
A front-stage HPF flyback converter with CV output set-point Vout,setpoint of 54 V (54 V/0.8 A) has been selected as a
design example. The design specifications are shown in Table 2.
Table 2 Design specifications
Specification
Symbol
Value
Unit
Normal operational minimum AC input voltage
VAC,min
90
Vrms
Normal operational maximum AC input voltage
VAC,max
305
Vrms
Normal operational AC input frequency
Fline
47 ~ 63
Hz
Secondary-side regulated CV output set-point
Vout,setpoint
54
V
Steady-state output load current
Iout
0 ~ 800
mA
Steady-state full-load output power
Pout,full
43.2
W
Minimum efficiency at Pout,full
ƞmin,at,P,out,full
90
%
Target minimum switching frequency at Pout,full
fsw,min,at,P,out,full
52
kHz
Note: Pout,full of 43.2 W is defined in this design example, to be able to supply a second-stage CC converter
which has minimum efficiency of 93 percent (or maximum 3.2 W loss) at full load, for a 40 W LED
driver design.
Note: The recommended fsw,min,at,P,out,full is between 50 kHz and 65 kHz. In general, higher fsw,min,at,P,out,full
value would result in a smaller flyback transformer with lower efficiency, while lower fsw,min,at,P,out,full
value would result in a larger flyback transformer with higher efficiency.

Design Guide 6 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
Transformer design
3Transformer design
To achieve both high efficiency and high power quality in QR Mode with first valley switching (QRM1), the
flyback transformer primary main winding to secondary main winding turns ratio, N, should be high enough,
but without exceeding the flyback MOSFET drain-source breakdown voltage V(BR)DSS. Based on the VAC,max
requirement of 305 Vrms, MOSFET V(BR)DSS = 800 V is selected for a good price to performance ratio.
To reduce transformer leakage inductance for low MOSFET voltage spike Vspike,FET, transformer design with
sandwich construction as shown in Figure 3 is highly recommended. Additionally, with the primary RCD
snubber network deployed across the primary main winding (see Figure 1), Vspike,FET can be estimated to be
around 30 percent to 45 percent of VAC,max as a rule of thumb. In this design example, VAC,max is 305 Vrms, so we
simply assume Vspike,FET as an absolute number of 100 V, which is approximately 33 percent of VAC,max.
Figure 3 Transformer design with sandwich construction
For good reliability against input voltage surge, it is recommended to reserve a voltage margin Vmargin,FET of
minimum 50 V from V(BR)DSS. If XDPL8218 input Over-Voltage Protection (OVP) would be enabled later in Section
10, as a rule of thumb, Vmargin,FET should be at least 25 percent of VAC,max, which is equivalent to 76.25 V based on
VAC,max of 305 Vrms. In this design example, Vmargin,FET of 90 V is selected.
Based on the above, N can be defined as:
 󰇛󰇜󰇛󰇜
(1)
Where VAC,max(pk) is √2 times VAC,max, and Vdis the secondary main output diode forward voltage.
Taking Vd= 0.7 V, N can then be calculated as:
 
 
Based on the above, N = 3.2 is selected.
The maximum primary peak current Ipri(pk),max can then be defined and calculated as:
󰇛󰇜 
󰏎   󰇛󰇜(2)
Where VAC,min(pk) is √2 times VAC,min.
󰇛󰇜 
 󰇣 󰇛󰇜 
󰇤
󰇛󰇜 

Design Guide 7 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
Transformer design
As a result, the primary main winding inductance Lpcan be defined and calculated as:
 󰇛󰇜󰇛󰇜
󰇛󰇜󰇛󰇜󰇛󰇜(3)
 󰇛󰇜
󰇟󰇛󰇜󰇠

Based on core cross-sectional area, Ae= 120.1 mm2and saturation flux density at 100°C, Bsat(T=100°C) = 0.41 Tesla
for TDG PQ26/20 core with TPW33 material, the transformer primary main winding turns Npcan be defined as:
 󰇛󰇜
󰇛󰇜(4)
Where Df,Bsat is the derating factor to ensure the designed transformer maximum flux density Bmax is below
Bsat(T=100°C) by a margin of (100 percent - Df,Bsat) from saturation, and itis typical to set Df,Bsat in the range of 85
percent to 95 percent for a margin of 5 percent to 15 percent from transformer core saturation.
Taking Df,Bsat = 90 percent, Npcan then be calculated as:
 

Based on the above, Np= 32 is selected.
The transformer secondary main winding turns Nscan then be calculated as:

  

To ensure fast VCC supply takeover from the primary auxiliary winding for avoiding IC reset during start-up, and
also to be able to deliver peak gate-drive voltage VGD,peak of 12 V with high enough primary auxiliary winding VCC
supply during steady-state, the minimum primary auxiliary winding demagnetization voltageVa,min is therefore
defined as 14 V. As a result, the recommended minimum primary auxiliary winding turns Na,min can be defined
and calculated as:
 
󰇛󰇜 󰇛󰇜  (5)
To ensure proper HV pin line synchronization, VCC voltage should be lower than 19 V, the maximum auxiliary
winding demagnetization voltageVa,max is therefore defined as 19 V. As a result, the recommended maximum
primary auxiliary winding turns Na,max can be defined and calculated as:
 
󰇛󰇜 󰇛󰇜  (6)
Based on the calculation results of equations (5) and (6), primary auxiliary winding turns Na= 3 is selected.
A secondary auxiliary winding is added to supply the operating voltage of the Secondary Side Regulation (SSR)
FB circuit, since its op-amp or shunt regulator’s maximum operating voltage is less than Vout,setpoint of 54 V. The
recommended minimum secondary auxiliary winding turns Na,sec,min and recommended maximum secondary
auxiliary winding turns Na,sec,max can be defined respectively as per Na,min and Na,max, as shown below:
    (7)
   (8)
Based on the calculation results of equations (7) and (8), secondary auxiliary winding turns Na,sec = 3 is selected.

Design Guide 8 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
Flyback MOSFET and secondary main output diode selection
4Flyback MOSFET and secondary main output diode selection
The CoolMOSTM P7 MOSFET series is the latest CoolMOSTM product family and targets customers looking for high
performance and at the same time being price sensitive. Through optimizing key parameters (Coss, Eoss, Qg, Ciss
and VGS(th)); integrating Zener diode for ESD protection and other measures, this product family fully addresses
market concerns in performance, ease-of-use, and price/performance ratio, delivering best-in-class
performance with exceptional ease-of-use, while still not compromising on price/performance ratio. The 700 V
and 800 V CoolMOSTM P7 series have been designed for flyback and could also be used in PFC topologies.
MOSFET drain-source breakdown voltage V(BR)DSS = 800 V is selected in this design example based on VAC,max of
305 Vrms and transformer design in Section 3.
Before selecting which MOSFET drain-source on-resistance at room temperature Rds(on),25°C is to be used, the
maximum primary rms current Ipri(rms),max has to be estimated based on:
󰇛󰇜 󰇛󰇜
(9)
Where k is a number obtained from the function curve in Figure 4, based on the variable factor of
󰇛󰇜
󰇛󰇜.
In this design example, the variable factor of 󰇛󰇜
󰇛󰇜can be calculated as:
󰇛󰇜
󰇛󰇜  󰇛󰇜 
Referring to the function curve in Figure 4, k = 0.31 is obtained.
Based on equation (9), Ipri(rms),max can then be calculated as:
󰇛󰇜 

󰇛󰇜 
Figure 4 Function curve of k

Design Guide 9 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
Flyback MOSFET and secondary main output diode selection
The selectable MOSFET Rds(on),25°C can be defined as:
󰇛󰇜  
󰇛󰇜󰇛󰇜(10)
Where m is the desired ratio of MOSFET conduction loss over Pout,full and ∆Rds(on),100°C is the ratio of 󰇛󰇜
󰇛󰇜.
It is typical to select min the range of 0.025 to 0.03 and ∆Rds(on),100°C in the range of 1.75 to 1.85. Taking m = 0.0275
and ∆Rds(on),100°C = 1.8, Rds(on),25°C can then be calculated as:
󰇛󰇜 
 
Referring to the calculation results of equation (10) and Table 3 below, Rds(on),25°C = 900 mΩis selected.
To utilize the PCB as a heatsink for the MOSFET, IPD80R900P7 with TO-252 (DPAK) package is selected.
Table 3 800 V CoolMOSTM P7 selection table
For the secondary main output diode selection, it is necessary to first estimate the maximum reverse voltage
Vr(diode),max and maximum secondary main winding peak current Isec(pk),max, based on:
󰇛󰇜    󰇛󰇜
(11)
Where Vspike,diode is the diode reverse voltage spike.
Assuming  󰇡󰇛󰇜
󰇢,
󰇛󰇜 󰇡󰇛󰇜
󰇢 󰇡  󰇢
󰇛󰇜 
󰇛󰇜 󰇛󰇜 
  (12)
󰇛󰇜 
Based on the above, a secondary main output diode with repetitive reverse voltage rating VRRM = 300 V is
selected. To minimize its switching and conduction losses, the selected diode also has the properties of hyper-
fast recovery speed and low forward voltage drop at Isec(pk),max.
Additionally, a RC secondary snubber network, e.g. 10 Ωresistor in series with 150 pF capacitor, is deployed
across the secondary main output diode, to suppress the diode reverse voltage spike and the EMI.

Design Guide 10 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
CS resistor and GD pin-related design
5CS resistor and GD pin-related design
Figure 5 shows the connections of the Current Sense (CS) resistor RCS, gate resistor RGand gate source resistor
RGS.
CS
RCS
GD
RGS
RG
Figure 5 GD pin, CS pin, RCS, RGand RGS connections
Based on the CS pin voltage across RCS, the MOSFET current can be measured.
The recommended minimum CS resistor value RCS,min is defined and calculated as:
 
󰇛󰇜      (13)
The recommended maximum CS resistor value RCS,max is defined and calculated as:
 
󰇛󰇜     (14)
Based on the calculation results above, CS resistor RCS = 0.2 Ω is selected in this design example.
RGis to damp the gate-rise oscillaton, and RGS is to ensure the MOSFET remains in an off-state when AC input is
applied, with the IC not being activated yet. RG= 10 Ω and RGS = 20 kΩ are selected in this design example.
The gate-drive peak voltage VGD,pk is typically 12 V with sufficient VCC voltage supply. To achieve a good balance
of switching loss and EMI, the gate voltage rising slope can be controlled by configuring the gate driver peak
source current parameter IGD,pk (configurable range: 30 mA to 180 mA). This saves two components (see Dfastoff,
Rslowon in Figure 6), which are conventionally added for the same purpose.
t
VGD
IGD,pk
= 30mA
=118mA
(12V typ.) IGD,pk
VGD,pk
Figure 6 Gate-drive voltage rising slope control with IGD,pk parameterization for component saving
With the high-speed switching characteristics of CoolMOSTM P7 MOSFET, it is recommended to configure the
IGD,pk parameter in the range of 30 mA to 49 mA.
As a result, IGD,pk = 30 mA is selected in this design example.

Design Guide 11 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
MOSFET maximum current cycle-by-cycle limit and start-up phase design
6MOSFET maximum current cycle-by-cycle limit and start-up phase
design
Under the single-fault condition of second-stage CC converter MOSFET drain and source pins being shorted, the
connected output LEDs could clamp the flyback output voltage below its constant voltage regulation set-point.
To limit the flyback output power to the LEDs below 100 VA as per UL1310 requirements under such fault
conditions, especially at high input voltage, XDPL8218 regulated mode features the CS pin voltage level 1 for
MOSFET maximum current cycle-by-cycle limit VOCP1(Vin), which is adaptive based on the estimated input
voltage Vin, as shown in Figure 7.
Note: Regulated mode is a controller operating state, which is entered after the start-up phase, to
regulate the output based on the FB voltage mapping, as shown in Figure 8.
Note: The estimated input voltage Vin used for VOCP1(Vin) adaptation is in rms value, which is assumed as
0.707 of estimated peak input voltage Vin,peak, regardless of whether actual input voltage is AC or
DC. As the input voltage is estimated based on ZCD pin and CS pin switching signals, proper ZCD
resistor selection (see Section 12) and Rin parameter fine-tuning (see Section 18.1) are needed.
VOCP1(Vin)
Vin,high
Vin,low Vin
VOCP1,at,V,in,low
VOCP1,at,V,in,high
Figure 7 Regulated mode CS pin voltage level 1 for MOSFET maximum current cycle-by-cycle limit
VOCP1,at,V,in,low parameter defines the value of VOCP1(Vin) variable when the estimated input voltage Vin is same as or
lower than the lowest operational input voltage parameter Vin,low.
Vin,low and VOCP1,at,V,in,low parameters can be defined and calculated as:
   (15)
Where a is the ratio recommended to be between 0.9 and 0.95.
Taking a = 0.91,
  
 
 󰇛󰇜  (16)
 

Design Guide 12 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
MOSFET maximum current cycle-by-cycle limit and start-up phase design
 
VOCP1,at,V,in,high parameter defines the value of VOCP1(Vin) variable when the estimated input voltage Vin is the same
as or higher than the highest operational input voltage parameter Vin,high. To better limit the maximum output
power transfer to the LEDs under the fault condition mentioned above, VOCP1,at,V,in,high should be configured less
than VOCP1,at,V,in,low.
Vin,high and VOCP1,at,V,in,high parameters can be defined and calculated as:
 (17)
Where b is the ratio recommended to be between 1.05 and 1.10.
Taking b = 1.07,

 
  󰇛󰇜 
󰇛󰇜 (18)
Where Vin,high(pk) is √2 times of Vin,high and c is the ratio recommended to be between 1.05 and 1.15.
Taking c = 1.12,
  󰇣
  
󰇛󰇜󰇤
 
Note: VOCP1,at,V,in,high parameter minimum configurable value is fixed as 0.34 V. If the calculation result of
equation (18) is below 0.34 V, parameter setting of VOCP1,at,Vin,high = 0.34 V should be selected.
Vstart,OCP1
02 tSS
time
Soft start phase
(based on nss = 3 configuration as example)
Output
charging
phase
Pre-Startup Check
(e.g. input voltage,
IC temperature)
tSS tout,charge
Vout,start
Startup phase
3 tSS
VOCP1(Vin)
Start of regulation according to
feedback voltage mapping
Vout
CS pin voltage level 1 for MOSFET
max current cycle by cycle limit
Voltage
(0.5ms typ.) (1.0ms typ.) (1.5ms typ.)
VOCP1,init
Startup with 1st
soft start step
Regulated Mode
VoutUV,start
tstart,max
Figure 8 Pre-start-up check, start-up phase and regulated mode
Pre-start-up check ensures the estimated input voltage Vin and IC junction temperature Tjare within the
configured protection limits before start-up, as shown in Figure 8. The parameter configurations of the input
voltage levels and maximum Tjfor start-up are covered in Section 11 and Section 15.3 respectively.

Design Guide 13 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
MOSFET maximum current cycle-by-cycle limit and start-up phase design
VOCP1,init parameter in Figure 8 denotes the initial CS pin voltage level 1 for MOSFET current limit on the input
voltage measurement pulse, during pre-start-up check. It can be defined and calculated as:
 󰇛󰇜
(19)
Where ton,min,V,in,start,sense is the minimum on-time for the pre-start-up input voltage measurement pulse and d is
the ratio recommended to be between 1.2 and 1.3.
Take ton,min,V,in,start,sense = 1.38 µs, and d = 1.29,
 
 
 
Note: A typical leading-edge blanking time tCS,LEB of 480 ns applies on VOCP1(Vin), VOCP1,init and Vstart,OCP1.
The start-up phase consists of the soft-start phase and output charging phase. The soft-start phase is to
minimize the component stress during start-up, while the output charging phase is to fast-charge the output
voltage for fast VCC self-supply takeover from the primary auxiliary winding.
During the soft-start phase, the switching frequency is fixed as 20 kHz. The MOSFET current is limited in the first
soft-start step based on the CS pin maximum voltage limit of Vstart,OCP1/(nss + 1), where Vstart,OCP1 is the parameter
for the output charging phase CS pin maximum voltage limit, and nss is the parameter for the number of soft-
start steps. The soft-start phase CS pin maximum voltage limit is increased by Vstart,OCP1/(nss + 1) after each soft-
start step, and the typical duration of each soft-start step is 0.5 ms.
During the output charging phase, the output voltage is fast-charged with MOSFET switching pulses based on
either the output charging phase CS pin maximum voltage limit of Vstart,OCP1 or the maximum on-time in QRM. To
exit the start-up phase and enter the regulated mode without triggering the start-up output UVP, the ZCD pin
estimated output voltage Vout has to either reach the output charging voltage set-point of Vout,start before the
maximum allowable start-up phase duration of tstart,max is reached, or reach at least the start-up output UVP
level of VoutUV,start at the timing of tstart,max.
It is generally recommended to set the nss parameter value between 2 and 4. In this design example, nSS = 3
parameter setting is selected, as shown in Figure 8.
To ensure fast VCC self-supply takeover from the primary auxiliary winding, the Vstart,OCP1 parameter is
recommended to be configured as per VOCP1,at,V,in,low. Hence, Vstart,OCP1 = 0.52 V parameter setting is selected in this
design example.
Vout,start parameter can be defined and calculated as:
 
(20)
Where Va,start is the desired primary auxiliary winding demagnetization voltage when output voltage is Vout,start.
Va,start is recommended to be between 8 V and 9 V. So, taking Va,start = 8.3 V,
 

 

Design Guide 14 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
HV pin-related design
7HV pin-related design
As shown in Figure 9, HV series resistor RHV is connected from the HV pin to the cathodes of HV diode DHV1 and
DHV2, while bridge rectifier AC input should be applied across the DHV1 anode and DHV2 anode.
Additionally, a HV capacitor CHV should also be connected between the HV pin and ground.
RHV
HV
~ ~
CHV
DHV1 DHV2
Bridge rectifier `
Figure 9 HV pin, RHV, CHV, DHV1 and DHV2 connections
The recommended minimum HV series resistor value RHV,min is defined and calculated as:
 󰇛󰇜
 (21)
Where IHV,max is the HV pin maximum peak input current of 9.6 mA.
 
  kΩ
The recommended maximum HV series resistor value RHV,max is defined and calculated as:
 󰇛󰇜
󰇛󰇜    󰇛󰇜(22)
Where VAC,min(rect,avg) is the average value of the rectified VAC,min, while VVCCON,max is the maximum VCC turn-on voltage
threshold of 22 V, and IHV,min(avg) is the recommended HV pin minimum average input current of 1 mA.
 
 󰇣 󰇡
󰇢󰇤
 
Based on the above, RHV = 52 kΩ is selected in this design example.
The HV series resistor dielectric withstand voltage should be above the total of VAC,max(pk) and Vmargin,FET (see
Section 4 for their respective values), which is equivalent to 521.3 V. As an example, the selected RHV = 52 kΩ in
this design example can be formed using a 36 kΩ 0.5 W resistor (dielectric withstand of 350 V) in series with a 16
kΩ 0.25 W resistor (dielectric withstand of 200 V).
For better line synchronization stability against noise interference, CHV shown in Figure 9 is needed. In addition,
CHV also improves the surge and ESD capability of the HV pin.
CHV = 1 nF is recommended and selected in this design example.

Design Guide 15 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
VCC capacitance and output UVP design
8VCC capacitance and output UVP design
To fulfill the Energy Star time-to-light requirement of 500 ms, the VCC voltage maximum charging time for IC
activation, tVCCON,charge,max should not exceed 350 ms. Therefore, the maximum VCC capacitance CVCC,max can be
defined and calculated as:
 󰇛󰇜
    󰇛󰇜(23)
Where VVCCON,max is the maximum VCC turn-on threshold of 22 V, VAC,120(rect,avg) is the average value of rectified 120
Vrms AC input, and VAC,120(pk) is the peak value of 120 Vrms AC input.
 
  󰇣 󰇡
󰇢󰇤
tstart,max parameter refers to the maximum allowable duration of the start-up phase, which consists of the soft-
start phase and output charging phase. It can be indirectly configured with VCC capacitance parameter CVCC,
based on:
 󰇛󰇜
 󰇛󰇜   (24)
Where VVCCON is the typical VCC turn-on voltage threshold of 20.5 V, VUVOFF is the typical VCC turn-off voltage
threshold of 6 V and IIC,avg,est is the estimated IC current consumption of 12 mA.
For proper start-up, as shown in Figure 10 (left), CVCC has to be high enough to ensure its corresponding tstart,max
calculated from equation (24) is longer than tout,charge, whch tout,charge is the time needed to charge the output
voltage to the start-up output UVP level VoutUV,start or higher.
Based on the considerations above, VCC capacitor value and IC parameter setting of CVCC = 22 Fare selected in
this design example, which results in tstart,max = 21.3 ms. In addition, a noise decoupling ceramic capacitor of
CVCCdecouple = 0.1 Fwith low ESR is added in parallel to CVCC.
In the start-up phase, if the ZCD pin estimated output voltage Vout is lower than VoutUV,start over a time-out period
of tstart,max, the start-up output UVP is triggered. For instance, this could happen if the flyback output is shorted
during the start-up, as shown in Figure 10 (right). It is recommended to configure VoutUV,start as Vout,start. Hence,
VoutUV,start = 27 V is selected in this design example.
The reaction of start-up output UVP is fixed as auto-restart and the auto-restart time is based on the tauto,restart
parameter. tauto,restart = 1.2 sec setting is selected in this design example. Please note that tauto,restart is a common
auto-restart time used for other system protections with auto-restart reaction.
time
VVCC
VVCCON
VUVOFF
tout,charge
(20.5V typ)
(6V typ.)
Vout,start
Output setpoint
tVCC,holdup
Voltage
Vout
Startup output undervoltage
protection triggered
(Vout < VoutUV,start ,at tstart,max)
Normal startup
tstart,max
Output short startup
VoutUV,start
time
VVCC
VVCCON
VUVOFF
(20.5V typ)
(6V typ.)
Vout,start
Output setpoint
tVCC,holdup
Voltage tstart,max
VoutUV,start
Vout
tVCCON,charge tVCCON,charge
Figure 10 Normal start-up and start-up output UVP (short) waveforms

Design Guide 16 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
VCC capacitance and output UVP design
Under the single-fault condition of second-stage CC regulator MOSFET drain and source pins being shorted, the
main output could be clamped by a low-output LED voltage, which could result in the flyback MOSFET
continuously operating in the saturation region due to low VCC and gate-drive voltages.
Hence, in this design example, ENUVP,Vout = Enabled parameter setting is selected to enable the regulated mode
output UVP, which could be triggered if the ZCD pin estimated output voltage Vout is below the regulated mode
output UVP level VoutUV for longer than a blanking time of tVoutUV,blank, as shown in Figure 11.
VoutUV parameter can be defined and calculated as:
 
(25)
Where Va,UV is the desired primary auxiliary winding demagnetization voltage when output voltage is VoutUV.
Va,UV is recommended to be between 9.5 V and 10.5 V. So, taking Va,UV = 10.1 V,
 

 
To prevent the regulated mode output UVP from being triggered by the output undershoot during input voltage
step-down, e.g. from 277 Vrms to 120 Vrms, tVoutUV,blank is recommended to be at least 100 ms. Hence, tVoutUV,blank =
500 ms is selected in this design example.
Vout
time
Turn-on
Output load current
too high causing
power limit and
Vout drop below
set-point
Startup
phase
Regulated Mode
(Vout > VoutUV)
Output under-
voltage protection
triggered after
tVoutUV,blank
VoutUV
Vout,start
Output setpoint Start of regulation
according to feedback
voltage mapping
Regulated Mode
(Vout < VoutUV for tVoutUV,blank)
Figure 11 Regulated mode output UVP (based on ZCD pin voltage sensing)
The reaction of regulated mode output UVP is configurable to latch-mode or auto-restart, based on the
ReactionUVP,Vout parameter. ReactionUVP,Vout = Auto-Restart is selected in this design example.
Note: The regulated mode output UVP is not active in Active Burst Mode (ABM).

Design Guide 17 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
Output OVP-related design
9Output OVP-related design
Under the single-fault condition of the FB pin open, the main output voltage would rise quickly above Vout,setpoint.
As shown in Figure 12, the output OVP would be triggered when the ZCD pin estimated output voltage Vout is
higher than the output OVP level VoutOV for longer than a blanking time.
Note: The output OVP blanking time is typically a quarter of the half sine wave period, e.g. 2.5 ms for Fline
= 50 Hz with line synchronization established.
To prevent the output OVP from being triggered by the output overshoot during input voltage step-up, e.g.
from 120 Vrms to 277 Vrms, the output OVP level VoutOV should be configured well above Vout,setpoint. Therefore, the
VoutOV parameter can be defined and calculated as:
  
Based on the above, VoutOV = 65 V is selected in this design example.
Considering the ZCD pin estimated output voltage protection accuracy is subjective to the the sampled signal
accuracy, sampling delay, indirect sensing delay (e.g. output voltage cannot be estimated near AC input phase
angle of 0 degrees and 180 degrees) and blanking time, the output capacitor voltage rating Vout,cap,rating should be
selected well above VoutOV. As a result, Vout,cap,rating can be defined and calculated as:
 
   (27)
Based on the above, Vout,cap,rating = 80 V is selected in this design example.
Attention: It is mandatory to ensure that VoutOV is configured well below the actual output capacitor
voltage rating Vout,cap,rating, while the Vout,cap,rating is not exceeded in actual testing with all the
necessary test conditions.
Vout
time
Turn-on
Start of regulation
according to
feedback voltage
mapping
FB pin Open
Startup
phase
Regulated Mode Auto-restart time
(based on tauto,restart)
VoutOV protection triggered
after blanking time
VoutOV
Vout,start
Output setpoint ReactionOVP,Vout = Auto-restart
ReactionOVP,Vout = Latch-Mode
Vout,cap,rating
Figure 12 Output OVP (based on ZCD pin voltage sensing)
The reaction of output OVP is configurable to latch-mode or auto-restart, based on the ReactionOVP,Vout
parameter. ReactionOVP,Vout = Auto-Restart is selected in this design example.
Note: The output OVP is not active in ABM.

Design Guide 18 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
DC link filter and secondary main output capacitance
10 DC link filter and secondary main output capacitance
CDC,filter denotes the DC link filter capacitor placed after the bridge rectifier. A higher CDC,filter value gives lower EMI
but worse power quality, and vice versa.
Table 4 Recommended initial CDC,filter value
VAC,min (V)
Steady-state full-load output power Pout,full (W)
Recommended initial CDC,filter (F)
90 ~ 107
Less than 26
0.1
26 ~ 35
0.15
36 ~ 45
0.22
Greater than 45
Greater than 0.22
Greater than or
equal to 108
Less than 31
0.1
31 ~ 40
0.15
41 ~ 55
0.22
Greater than 55
Greater than 0.22
Referring to Table 4, initial CDC,filter = 0.22 Fis selected in this design example. To improve the estimated input
voltage Vin accuracy during pre-start-up check, it is also recommended to deploy DC link resistor RDC,filter = 30
MΩ in parallel with CDC,filter, as shown in Figure 13.
AC
Input
Line Filter
and
Bridge
Rectifier
VDC,filter
+
-
~
~
CDC,filter RDC,filter
Figure 13 CDC,filter and RDC,filter across the DC link bus voltage
To compensate for the input current displacement caused by the CDC,filter, the XDPL8218 enhanced Power Factor
Correction (PFC) feature can be enabled by configuration of the compensation gain parameter named CEMI. As a
start, it can be configured as per the CDC,filter value. Hence, the initial CEMI = 0.22 Fparameter setting is selected
in this design example. Upon successful powering-up of the sytem, refer to Section 18.3 for the fine-tuning
guide.
Vripple,out(pk-pk),max denotes the maximum allowable secondary main output voltage peak-to-peak ripple level.
Assuming the flyback output in this design example is connected to a second-stage CC buck regulator, which
has a maximum LED voltage load VLED,max of 48 V and maximum allowable duty cycle Dbuck,max of 95 percent,
Vripple,out(pk-pk),max can be defined and calculated as:
󰇛󰇜  
 󰇡  󰇢  (28)
The secondary main output capacitor Cout value can then be defined and calculated as:
  
󰇛󰇜    (29)
Considering the tolerance of the electrolytic capacitor value, Cout = 470 Fis selected in this design example.
For lower EMI, low-ESR ceramic capacitors Cout,lowESR1 = 1 Fand Cout,lowESR2 = 0.1 Fare also added in parallel
with Cout.

Design Guide 19 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
Input voltage levels for start-up and protection
11 Input voltage levels for start-up and protection
ENOVP,In parameter refers to the enable switch for maximum input voltage start-up check and input OVP, based
on Vin,start,max and VinOV levels, respectively. ENOVP,In = Enabled is selected in this design example.
ENUVP,In parameter refers to the enable switch for minimum input voltage start-up check and input UVP, based
on Vin,start,min and VinUV levels, respectively. ENUVP,In = Enabled is selected in this design example.
Note: The estimated input voltage Vin used for start-up check and protection is in rms value, which is
assumed as 0.707 of estimated peak input voltage Vin,peak regardless of whether actual input
voltage is AC or DC. As the input voltage is estimated based on ZCD pin and CS pin switching
signals, proper ZCD resistor selection (see Section 12) and Rin parameter fine-tuning (see Section
18.1) are needed.
Vin,start,max parameter refers to the maximum input voltage level setting for start-up, which is recommended to be
configured as Vin,high. Hence, Vin,start,max = 326 Vrms is selected in this design example. VinOV parameter refers to the
input OVP level setting, which is recommended to be:
    (30)
Vin,start,min parameter refers to the minimum input voltage level setting for start-up, which is recommended to be
configured as Vin,low. Hence, Vin,start,min = 82 Vrms is selected in this design example. VinUV parameter refers to the
input UV (brown-out) protection level setting, which is recommended as:
   (31)
Based on the above, VinOV = 350 Vrms and VinUV = 70 Vrms are selected in this design example.
ENVIN,ABM refers to the enable switch for input voltage protections (based on VinOV and VinUV) in ABM.
If ENVIN,ABM is enabled, the enable switches for VinOV and VinUV protections in ABM are respectively based on ENOVP,In
and ENUVP,In. If ENVIN,ABM is disabled, both VinOV and VinUV protections are inactive in ABM.
In this design example, ENVIN,ABM = Enabled is selected.
Note: The reaction of VinOV and VinUV protections is auto-restart. A typical blanking time of either 10 half
sine wave periods or 10 burst periods applies on VinOV and VinUV protections triggering.
Vin
t
VinOV
Vin,start,max
VinUV
Vin,start,min
Startup
Startup
Startup
Protection
triggered
Protection
triggered
Figure 14 Input voltage levels for start-up and protection

Design Guide 20 of 48 V 1.0
2018-06-06
XDPL8218 design guide
For high power factor flyback converter with constant voltage output
ZCD pin-related design
12 ZCD pin-related design
ZCD pin filter capacitor CZCD, ZCD series resistor RZCD,1 and ZCD shunt resistor RZCD,2 are connected based on the
connections shown in Figure 15.
ZCD
RZCD,2
RZCD,1
Na
CZCD
Figure 15 ZCD pin, CZCD, RZCD1 and RZCD2 connections
CZCD is mainly for ZCD pin noise-filtering, so a fixed value can generally be used for different designs. CZCD = 47 pF
is selected in this design example.
Note: QR first valley switching of the MOSFET drain voltage can be achieved with tZCDPD parameter fine-
tuning based on Section 18.2. Initial tZCDPD = 350 ns can be used for powering-up of the system
before the fine-tuning.
Apart from zero crossing detection, the ZCD pin is also used to measure the reflected input voltage signal when
the MOSFET is turned on, and to measure the reflected output voltage signal when the MOSFET is turned off
afterward. Hence, it is important to select the correct RZCD,1 and RZCD,2 values, which can cover the necessary
measurement range, not only for normal conditions but also for protected conditions.
The recommended minimum ZCD series resistance RZCD,1,min and maximum ZCD series resistance RZCD,1,max are
defined as:
  
󰇛󰇜󰇛󰇜  (32)
  
󰇛󰇜 󰇛󰇜  (33)
Where:
VinOV(pk) and VinUV(pk) are respectively √2 times VinOV and √2 times VinUV.
IIV,max,VinOV and IIV,min,VinUV are respectively the recommended maximum ZCD pin negative clamping current for VinOV
sensing and minimum ZCD pin negative clamping current for VinUV sensing.
VZCDSH,max,VoutOV and VZCDSH,min,VoutOV are respectively the recommended maximum and minimum ZCD pin voltage
sensing levels for VoutOV sensing.
VINPCLN,max and VINPCLN,min are respectively the maximum and minimum ZCD pin negative clamping voltages.
∆Vin,HF,ripple,est is the estimated difference between the VinUV(pk) level and the high-frequency ripple minimum
voltage level at the peak of AC input half sine wave. As a rule of thumb, it can be assumed to be between 25 V
and 30 V.
Taking IIV,max,VinOV = -3.1 mA, IIV,min,VinUV = -0.15 mA, VZCDSH,max,VoutOV = 2.6 V, VZCDSH,min,VoutOV = 2.35 V, VINPCLN,max = -0.22 V,
VINPCLN,min = -0.14 V, and ∆Vin,HF,ripple,est = 27.5 V,