Infineon IDP2303 Guide

Application Note Revision 2.0
www.infineon.com 2017-05-03
DG_201701_PL21_004
Design guide IDP2303(A)
Design guide for TV power supply with digital multi-mode PFC + LLC
combo IC IDP2303(A)
About this document
Scope and purpose
This design guide is to help customers design a TV power supply using an Infineon digital controller. It provides
guidelines on power stage design, control parameters and protection settings as well as PCB layout and
dpVision GUI usage.
Intended audience
This document is intended for design engineers that want to design a high performance TV power supply using
Infineon's digital multi-mode PFC + LLC combo IC.
Table of contents
About this document .............................................................................................................................................1
Table of contents...................................................................................................................................................1
1Abstract..............................................................................................................................................3
2Introduction.......................................................................................................................................4
2.1 IC Introduction ........................................................................................................................................4
2.2 Pin configuration and description..........................................................................................................4
2.3 Product highlights...................................................................................................................................5
2.4 Application ..............................................................................................................................................6
3PFC design..........................................................................................................................................7
3.1 Target specifications...............................................................................................................................7
3.2 Power stage.............................................................................................................................................7
3.2.1 Bridge rectifier....................................................................................................................................7
3.2.2 Selection of power MOSFET...............................................................................................................8
3.2.3 MOSFET gate driving..........................................................................................................................9
3.2.3.1 Unique gate drive concept ...........................................................................................................9
3.2.3.2 Gate drive stability........................................................................................................................9
3.2.3.3 Other design tips for the gate driving circuit .............................................................................10
3.2.4 Boost diode ......................................................................................................................................10
3.2.5 Boost inductor..................................................................................................................................10
3.3 Control parameters and protections....................................................................................................12
3.3.1 Output voltage sense and protections............................................................................................12
3.3.2 Redundant OVP (ROVP)....................................................................................................................13
3.3.3 PFC ZCD divider design....................................................................................................................15
3.3.4 Current sense and Over Current Protection (OCP) .........................................................................15
3.3.4.1 Over Current Protection(OCP) tolerance & selection of current sense resistor .......................16
3.3.4.2 Verification of PFC inductance with OCP tolerance ..................................................................19
3.3.5 Frequency law for multi-mode PFC.................................................................................................19
3.3.5.1 Multimode PFC............................................................................................................................19
3.3.5.2 Frequency law.............................................................................................................................20
3.3.5.3 Setting of and ........................................................................................................21

Design guide IDP2303(A)
Abstract
Application Note 2 Revision 2.0
2017-05-03
3.3.6 AC brown-in & out ............................................................................................................................22
4LLC design........................................................................................................................................23
4.1 Target specifications.............................................................................................................................23
4.2 Power stage...........................................................................................................................................23
4.2.1 System parameter calculation ........................................................................................................23
4.2.2 Main transformer and resonant network........................................................................................24
4.2.2.1 Transformer turns ratio ..............................................................................................................24
4.2.2.2 Equivalent circuit and resonant network ..................................................................................25
4.2.2.3 Calculation of transformer turn ratio.........................................................................................27
4.2.2.4 Selection of resonant factor m...................................................................................................28
4.2.2.5 Selection of resonant capacitor .................................................................................................28
4.2.3 Power MOSFET selection.................................................................................................................29
4.2.4 MOSFET gate driving........................................................................................................................29
4.2.5 Output rectifier.................................................................................................................................29
4.3 Control parameters and protections....................................................................................................30
4.3.1 VCO frequency curve........................................................................................................................30
4.3.1.1 and....................................................................................................31
4.3.1.2 and.....................................................................................................31
4.3.1.3 (light load) : (heavy load) ................................32
4.3.2 Current sense and OCP ....................................................................................................................32
4.3.3 Dead time .........................................................................................................................................33
4.3.4 LLC model and regulation loop .......................................................................................................33
4.3.4.1 LLC small signal model...............................................................................................................33
4.3.4.2 VCO modeling..............................................................................................................................33
4.3.4.3 LLC regulation loop.....................................................................................................................34
5General features and system design considerations........................................................................36
5.1 VCC supply and high voltage startup cell.............................................................................................36
5.1.1 Start up.............................................................................................................................................36
5.1.2 Selection of VCC capacitor...............................................................................................................37
5.1.3 VCC supply circuit linear regulator..................................................................................................37
5.2 LLC High-side VCC (HSVCC) cap............................................................................................................38
5.3 Touch current........................................................................................................................................38
5.4 Black box ...............................................................................................................................................38
6Tips on PCB layout ...........................................................................................................................40
6.1 Star connection of grounding...............................................................................................................40
6.2 Filtering capacitors ...............................................................................................................................40
6.3 PFC ZCD signal detection circuit...........................................................................................................41
6.4 HBFB voltage detection circuit.............................................................................................................41
6.5 LLC high side bootstrap circuit.............................................................................................................41
6.6 Minimum current flowing loop area.....................................................................................................42
6.7 Passing 4 kV lightning surge test ..........................................................................................................42
6.8 Other considerations ............................................................................................................................43
7Usage of dpVision.............................................................................................................................44
7.1 Installation of dpVision .........................................................................................................................44
7.2 Parameter setting with dpVision ..........................................................................................................46
8References .......................................................................................................................................49

Design guide IDP2303(A)
Abstract
Application Note 3 Revision 2.0
2017-05-03
1Abstract
Infineon's digital platform controller IC (IDP2303(A)) combines the PFC and LLC controls for a high efficiency
power supply. This design guide provides detailed calculation examples for major power stage component
values as well as the settings for parameters associated with general functions and protection features.
Useful tips on PCB layout are included to help the customers optimize their PCB design. Lastly, the
installation and usage of a General User Interface - dpVision - is described to assist the customer in setting
parameters for the digital IC.
The design example used in this guide is a 120 W power supply for a UHD TV. The customer can easily apply
their own target specifications and obtain the design parameters by themselves.

Design guide IDP2303(A)
Introduction
Application Note 4 Revision 2.0
2017-05-03
2Introduction
2.1 IC Introduction
The IDP2303(A) is a multi-mode PFC and LLC controller combined with a floating high side driver and a
startup cell. A digital engine provides advanced algorithms for multi-mode operation to support the highest
efficiency over the whole load range. A comprehensive and configurable protection feature set is
implemented. Only a minimum of external components are required. The integrated HV startup cell and
advanced burst mode enable the achievement of low stand-by power. In addition, a one-time-programming
(OTP) unit is integrated to provide a wide set of configurable parameters that help to ease the design in
phase of the project. [1][2].
2.2 Pin configuration and description
The pin configuration is shown in Figure 1 and Table 1.
Figure 1 Pin configuration
Table 1 Pin definitions and functions
Symbol
Pin
Type
Function
GD0
(PFCGD)
1
O
Gate driver output 0 (PFC gate driver)
Output for directly driving the PFC PowerMOS. The default peak source current
capability is 156 mA and the peak sink current capability is 800 mA.
CS0
(PFCCS)
2
I
Current sense 0 (PFC current sense)
Pin CS0 is connected to an external shunt resistor and the source of the PFC
PowerMOS.
VCC
3
P
Positive voltage supply
IC power supply
GND
4
G
Ground
IC ground
ZCD
5
I
Zero crossing detection
Pin ZCD is connected to the auxiliary winding of the PFC choke.
1
2
3
4
14
15
16
HSGND
GD0 HSVCC
VCC
HSGD
GND 13 N.C.
5
6
7
8
10
11
12
HBFB
ZCD CS1
N.C.
GD1
HV 9MFIO
VS
CS0
IDP2303
PG-DSO-16 (150mil)

Design guide IDP2303(A)
Introduction
Application Note 5 Revision 2.0
2017-05-03
Symbol
Pin
Type
Function
VS
6
I
Voltage sensing
Pin VS is connected to a high ohmic resistor divider for directly sensing the bus
voltage.
N.C.
7
—
Creepage distance
HV
8
I
High voltage input
Pin HV is connected to the AC input via an external resistor and 2 diodes. There is
a 600 V HV startup-cell internally connected that is used for initial VCC charge. It
is also used to discharge the x-capacitors of the EMI network. Furthermore
sampled high voltage sensing is supported for brownin/brownout detection.
MFIO
(UART for
IDP2303A)
9
I
MFIO
Pin MFIO provides a half duplex UART communication IO interface for parameter
configuration. It also can be used for PFC output redundant over voltage
protection.
UART
Pin UART provides a half duplex UART communication IO interface for parameter
configuration and AC voltage detection.
HBFB
10
I
Half bridge feedback
Pin HBFB is connected to an optocoupler for the feedback path to control the
LLC switching frequency.
CS1
(HBCS)
11
I
Current sense 1 (half bridge current sense)
Pin CS1 is connected to an external shunt resistor and the source of the
PowerMOS in the half-bridge stage.
GD1
(LSGD)
12
O
Gate driver output 1 (half bridge low side gate driver)
Output for directly driving the lowside PowerMOS in the half-bridge. The peak
source current capability is 120 mA and the peak sink current capability is 500
mA.
N.C.
13
—
Creepage distance
HSGND
14
G
High side ground
Ground for floating high side driver
HSVCC
15
P
High side VCC
Power supply of the high side floating driver, supplied via bootstrap
HSGD
16
O
High side floating gate driver
Output for directly driving the high side PowerMOS in the half-bridge. The peak
source current capability is 0.52 A and the peak sink current capability is 1.3 A.
2.3 Product highlights
Integrated 600 V startup cell
Integrated floating driver based on coreless transformer technology
Digital multi-mode operation for higher efficiency
Supports low standby power by means of a direct X-cap discharge function and advanced burst mode
control
Eliminates the auxiliary power supply by means of anintegrated startup cell and burst mode
UART interface for communication and in-circuit configuration
Flexible design-in by means of one time programming capability for a wide range of parameters

Design guide IDP2303(A)
Introduction
Application Note 6 Revision 2.0
2017-05-03
2.4 Application
HSGND
HSVCC
HSGD
GD1
CS1
IDP2303
GD0
VCC
GNDHV
VAC ZCD
VS
CS0
Configuration
HBFB
Vout_2
MFIO
Vout_1
STANDBY
GD0
GD1
Figure 2 Typical application circuit for a power supply with IDP2303
HSGND
HSVCC
HSGD
GD1
IDP2303A
VCC
GND
85 ... 265 VAC
CS1
ZCD
HV
GD0
CS0
Gate1
EN
VCC
VS
PGND
VD2
Gate2
VD1
HBFB
Vcc
VS
UART
Figure 3 Typical application circuit for a power supply with IDP2303A

Design guide IDP2303(A)
PFC design
Application Note 7 Revision 2.0
2017-05-03
3PFC design
3.1 Target specifications
Table 2 shows the major specifications for the target PFC design.
Table 2 System specification
Parameter
Symbol
Value
Unit
Input voltage minimum
Vin_min
90
VAC
Input voltage maximum
Vin_max
265
VAC
Nominal bus voltage
Vbus
390
V
PFC output power
Po_PFC
130
W
Estimated efficiency of system (PFC+LLC) at 90 VAC
Ƞsys
> 87%
Estimated efficiency of PFC at 90 VAC
ƞPFC
~93%
Estimated efficiency of PFC at 265 VAC
ƞPFC_265
~96%
Minimum switching frequency
fsw_min
25
kHz
Power factor
> 0.9
3.2 Power stage
A simplified application circuit for PFC stage is given in Figure 4.
Figure 4 Simplified circuit for PFC converter
3.2.1 Bridge rectifier
The total bridge power loss is calculated using the average input current flowing through two of the bridge
rectifying diodes.

    
Knowing the value of the power loss, one can choose an appropriate bridge rectifier based on its thermal
characteristics.

Design guide IDP2303(A)
PFC design
Application Note 8 Revision 2.0
2017-05-03
3.2.2 Selection of power MOSFET
In order to select an optimum MOSFET, one must understand the MOSFET requirements in a DCM boost
converter [3]. The following are some major MOSFET selection considerations:
Low Figure of Merit - Ron*Qgand Ron*Qoss
Fast Turn-on/off switching to reduce the device switching losses
Low output capacitance Coss for low switching energy, to increase light load efficiency.
Switching and conduction losses must be balanced for minimum total loss - this is typically optimized at
the low line condition, where worst case losses and temperature rises occur.
VDS rating to handle spikes/overshoots
Low thermal resistance RthJC. Package selection must consider the resulting total thermal resistance from
junction to ambient.
Body diode speed and reverse recovery charge are not important, since the body diode never conducts in
a boost converter.
Infineon high voltage MOSFETs have several families based on different technologies, each of which target a
specific application, topology or operation. Several CoolMOS™ series devices can be used for boost
applications depending upon the customer’s requirement for the voltage rating and thermal characteristics.
With the CE in 500 V, E6 and P6 family in 600 V, Infineon offers various series with extremely low conduction
and switching losses that can make switching applications more efficient, more compact, lighter and cooler.
Two IPD50R280CE in parallel are preselected for the design and their parameters will be used for the loss
calculation. The thermal characteristic can be estimated and the device shall be replaced if it cannot meet
the thermal requirement at the end of the calculation process.
The conduction loss dissipated by each MOSFET is calculated as:

  
In which,

         

 is the on-state resistance of the MOSFET at a junction temperature of 100ºC.
For CrCM or DCM operation, the turn-on loss due to the voltage-current crossover is negligible because when
MOSFET turns on, the MOSFET current rises from zero. Therefore, only the loss due to the discharge of the
drain-source capacitance of the MOSFET shall be considered.
The calculation of the MOSFET discharge loss at turn-on () and turn-off loss (  ) is
complicated due to the changing values of voltage, current, frequency etc. over the whole AC cycle. So
based on a rule-of-thumb, the total switching loss for each MOSFET is roughly estimated as half of the
conduction loss.  

Then the total power loss of each MOSFET can be estimated as:
 

Design guide IDP2303(A)
PFC design
Application Note 9 Revision 2.0
2017-05-03
3.2.3 MOSFET gate driving
3.2.3.1 Unique gate drive concept
The IDP230x gate drive offers unique features including configurable charge current and output voltage,
which offer many advantages (Figure 5):
turn-on slope optimization for EMI by configurable current with dpVision
no need to solder and re-solder resistors
turn-off current limited by external Rgate
due to fast 1 A/0.5 A discharge, a local discharge PNP transistor is not required in some relatively low
power applications
Vgate_high up to VCC possible (rail-to-rail operation)
Figure 5 Gate drive concept
3.2.3.2 Gate drive stability
Due to the unique gate drive with configurable charge current and regulated gate high voltage, Rgate should
not be too large. Table 3 shows the recommend range for stable gate drive operation. A 10ΩRgate resistor is
suitable for most applications. Soft turn-on for trouble-free EMI is guaranteed by the configurable constant
current gate charging.
Table 3 Recommended Rgate values for different Cgate, Rgs and gate source current
Cgate (nF)
1.0~2.0
Gate source current (mA)
100
310
Rgs (Ω)
10 k
100 k
10 k
100 k
Recommended Rgate (Ω)
5~20
15~25
4~14
2~18
Output Driver
GD0
PFC Gate
Control Signal
Voltage/
Current
Control
VGD
IGD_source IGD_sink

Design guide IDP2303(A)
PFC design
Application Note 10 Revision 2.0
2017-05-03
3.2.3.3 Other design tips for the gate driving circuit
For some high power SMPS applications, two MOSFETs are often connected in parallel for the PFC converter.
In this case, it is recommended to enhance the PFC driving capability by adding an additional circuit close to
the PFC MOSFET, as shown in the example in Figure 6.
During turn-off, transistors Q3 and Q4 are turned on, discharging the PFC MOSFET gate capacitor. As a
result, the turn-off of the MOSFETs is accelerated, which reduces the MOSFETs turn-off losses. Meanwhile,
the turn-on is defined by the constant gate charge current, which can be kept relatively slow for better EMI
performance.
Apart from the gate drive resistance itself, 10 kΩresistors (R5 and R6) are also commonly connected
between MOSFET gate and source to help damping some overshoot and oscillations and discharge gate
capacitor when there is no gate signal.
Figure 6 PFC gate driving circuit
3.2.4 Boost diode
To select an appropriate boost diode, its thermal characteristic needs to be considered.
The average diode current can be calculated by:
  
  
The total diode conduction loss can be calculated by:
 
3.2.5 Boost inductor
One of the key design considerations for a boost inductor is to ensure the minimum switching frequency is
always higher than 25 kHz to avoid any audible noise. The worst cases are usually at extremes of operation
such as minimum and maximum voltage and during start up and load transients - e.g. twice full power.

Design guide IDP2303(A)
PFC design
Application Note 11 Revision 2.0
2017-05-03
Figure 7 Current and timing in QR1 operation
With the IDP230x, the minimum switching frequency of 25 kHz is guaranteed by the “maximum switching
period time-out” approach, which turns the MOSFET on when 40 us of switching period is reached.
Based on the PFC control concept of the IDP230x, the frequency may reach the 25 kHz limit in two extreme
conditions:
Heavy load when QR=1 (MOSFET turn-on at the first switching valley according to the frequency law,
which will be discussed in a later section of this document.)
Light load when QRN>10 according to the frequency law, or when the ZCD signal is too weak to be
detected within 40 us.
The second condition will not affect the design of inductor.
Figure 7 illustrates the inductor current and timing during QR1 operation. In which
 
Where is the PFC inductance and is the time related output capacitance of the PFC MOSFET.
is usually around 1 us, and is negelected in the analysis below to simplify the calculation.
The switching frequency at the AC peak, double full load with QR1 operation can be calculated as:


For 265 Vac,  󰇛󰇜
  
For 90 Vac,  󰇛󰇜
  
Comparing the switching frequency at 265 Vac and 90 Vac peak, it is obvious that the frequency at 265 Vac is
lower. Therefore,  
Then the PFC inductance to meet the requirement can be calculated as:

Design guide IDP2303(A)
PFC design
Application Note 12 Revision 2.0
2017-05-03
 
 󰇛󰇜  
Thereby, a PFC inductance of 200 µH is selected.
Another design consideration for the boost inductor is to ensure that the ferrite core will not go into
saturation. Then the number of turns in the winding is calculated as:
 
   
in which

   
Bmax is up to 0.3T, Amin is 99if an EQ30 core with PC40 ferrite material is selected.
After the threshold of Over Current Protection (OCP) is defined and its tolerance taken into consideration,
verification is needed that the inductor is able to carry the maximum current defined by OCP, and not
become saturated. Otherwise, a large current will result from the saturation, and potentially damage
devices if it is present for some time.
3.3 Control parameters and protections
3.3.1 Output voltage sense and protections
The VS pin is used for feedback regulation of the PFC Bus voltage. A simple resistor divider is used to step
down the bus voltage as shown in Figure 8.
Bus
VS pin
R2
Rn
R1 C
Vin
Figure 8 PFC bus voltage sensing
It is recommended to use sense resistors with a tolerance of 1% for accurate sensing. Due to the voltage
stress across the upper arm resistor, it is recommended to split this value into a few resistors in series.
In order to achieve a better standby performance, the resistance of sensing resistors is suggested to select a
high value. The power loss brought by these sensing resistors under standby operation can be calculated as:



Design guide IDP2303(A)
PFC design
Application Note 13 Revision 2.0
2017-05-03
To meet the low standby power consumption requirement, PRs_loss should be optimized. For example, the
expected maximum power loss across these resistors, which occurs at 264Vac, is designed to be less than
15mW under standby operation, 
.
So (R1+…+Rn) is calculated to be higher than 9.3 M.
A capacitor of approximately 1nF should be added at the VS pin to ground to filter high frequency switching
noise. 

For Over Voltage Protection (OVP), if the average sensed PFC bus voltage exceeds the OVP threshold, the
PFC will stop switching while the LLC continues to run. Once the average sensed PFC bus voltage reduces
and reaches the reference bus voltage, the PFC converter resumes normal operation.
The PFC Under Voltage Protection (UVP) is a protection for the LLC converter against LLC input under
voltage, to avoid LLC transformer saturation or capacitive mode operation. If the average sensed PFC bus
voltage falls below a configurable UVP threshold for a blanking time, then PFC under voltage is detected. As
a result, PFC and LLC will stop switching immediately.
3.3.2 Redundant OVP (ROVP)
Customers may request an additional protection, Redundant Overvoltage Protection (ROVP) in case there is
a component failure in the main OVP voltage divider, for a higher level of reliability.
At the same time, the requirements for standby power consumption of a power supply unit (PSU) in TV
applications becomes more and more stringent.
To implement ROVP, a voltage divider consisting of resistors is usually connected between the bus and
ground to detect the bus voltage (usually 350 V in standby mode, and 390 V in normal mode). These resistors
will consume some power (p=v^2/R, usually 30~100 mW), which adds to the total power consumption of the
PSU, and becomes a critical concern in standby mode.
Figure 9 shows a typical ROVP circuit, which is almost lossless during standby mode.
Bus
IC pin
R2
1640k
BSS127
R1
7.5k C1
470p
R3
50k
R4
1.5M
C3
NC
D1
1N4148
D2
1n4148
LLC LS gate
PFC gate
Figure 9 Typical circuit of ROVP

Design guide IDP2303(A)
PFC design
Application Note 14 Revision 2.0
2017-05-03
In Figure 9, R1&R2 are the resistor voltage divider to detect the bus voltage. The voltage divider is effective
only when the BSS127 MOSFET is turned on.
The BSS127 gate drive consists of:
two small signal diodes D1 & D2 to introduce LLC and PFC gate signals as control inputs
R3 as a current limiter at turn on
R4 & C3 (the input capacitance of BSS127 or an additional capacitor) network, as an RC integrator
that converts “pulse” signal into a “step” signal.
In standby mode, during burst-on, when there is either PFC or LLC switching, the BSS127 MOSFET will be
turned on and the voltage divider is connected to the MCOM (Multi-function and Communication) pin to
detect bus voltage. During burst-off, when there is neither PFC nor LLC gate switching, the BSS127 MOSFET
is open and the voltage divider is out-of-circuit. Thus, the conduction loss in the voltage divider can be
avoided during burst-off, thereby saving power during standby.
During normal operation when the load is usually much larger, the IC is always active and the PFC and/or
LLC switch continuously so the voltage divider is always in-circuit. However, the conduction loss is only a
very small portion of the total loss.
With the IDP2303, the MFIO pin is used for PFC output ROVP.
As the MCOM pin is a multifunction pin, that is not dedicated for high impedance bus voltage sensing, it
must not be connect to the bus voltage divider at start up. Current leakage into the pin during system start-
up could affect the IC start-up behaviour. The proposed solution above with the BSS127 ensures a proper
start-up and an almost lossless 2nd OVP function, which is almost lossless during standby mode.
Below in Figure 10 are the typical waveforms of PFC (green) and LLC (blue) gate signals, the gate signal of
BSS127 (red) and voltage at the MCOM pin (yellow).
Figure 10 Typical waveforms during standby(left:20 ms/div; right: 20 ms/div)
After the IC wakes from sleep mode, the firmware starts to check the voltage at the MCOM pin after it
reaches a peak and is stable. If the ROVP threshold is reached, after a defined blanking time, the IC ceases
PFC switching.
If the ROVP function is not needed, customers can connect a resistor between the MCOM and GND pins to
pull the ROVP pin voltage below the threshold to disable ROVP.

Design guide IDP2303(A)
PFC design
Application Note 15 Revision 2.0
2017-05-03
3.3.3 PFC ZCD divider design
To ensure apporiate operation of PFC ZCD detection, the value of R_zcd_h and R_zcd_l, as well as the PFC
inductor turn ratio, should be optimized. For PFCZCD pin, there are an internal negative clamping (VINPCLN), as
shown in Ttable 4, with current capabitly of 2.5mA and a positive clampling (VD_zcd) by two external diodes.
Thus PFCZCD pin voltage can be calculated during PFC MOSFET on and inductor demagnetizing period.
PFC MOSFET on: 󰇱
    
 
 
PFC inductor demagnetizing period: 󰇱
   

 
In order to get a better noise Immunization performance, PFCZCD voltage is recommended to be higher
than the clamping voltage. Thus the clamping current can be calculated as:
Negative clamping current:  󰇡
󰇢

Positive clamping current: 󰇡
󰇢

For example, with a turn ratio of 8, diode forward voltage drop of 0.7V each, and minimum negative claming
voltage 0.14V, the minimum resistor ratio can be calculated:

 ,
where we can get 
. Based on the maximum negative clamping current, we could have
󰇡
󰇢
 .
Thus, 
Based on the calculation, the R_zcd_h can select a resistor of higher than 18.6k, while R_zcd_l can be higher
than 2 times of R_zcd_h.
Table 4 PFCZCD Parameters
3.3.4 Current sense and Over Current Protection (OCP)
The PFCCS pin is used to sense the drain-source current of the switching MOSFET. The voltage measured is
only valid after a certain blanking time following the turn-on of the switch. A low pass RC filter should be
added the pin to filter high frequency switching noise.
An appropriate sensing resistor value should ensure that:

Design guide IDP2303(A)
PFC design
Application Note 16 Revision 2.0
2017-05-03
The triggering of OCP protects the PFC inductor from saturation and other components from over current
stress.
The triggering of OCP does not occur during normal operation.
3.3.4.1 Over Current Protection(OCP) tolerance & selection of current sense
resistor
From the datasheet (Table 5), the parameters of the IC that will affect OCP protection tolerance are:
OCP1 threshold tolerance
OCP1 comparator propagation delay
Table 5 Electrical characteristics of the CSx pin
Parameters
Symbol
Values
Unit
Note/Test condition
Min.
Typ.
Max.
OCP, OCP1 threshold tolerance
ΔVOCP1
—
—
±6.2
%
Delay from VCSx crossing VCSxOCP1
to CSx_OCP1 rising edge, 1.2 V
range
tCSOCP1
20
320
620
ns
1input signal slope
dVCS/dt = 10 mV/µs 2
90
170
250
ns
1input signal slope
dVCS/dt = 150 mV/µs 2
90
140
210
ns
1 input signal slope
dVCS/dt = 300 mV/µs 2
1Not tested in production test.
2This slope represents a use case of a switch-mode power supply with minimum input voltage.
In reality, external circuit specifications also come into play. For example, from Figure 11, it can be seen that
the external parameters affecting OCP protection are:
The gain error caused by the external RC filter
The external delay caused by the RC filter
External propagation delays caused by the gate discharge and MOSFET drain-source capacitor discharge
DAC
OCP
comparator
-
+
PFCCS
Rshunt
iocp_power
VOCP_ref
Digital OCP level VOCP_COMP
Propagation delay
(internal IC+ external
RC+external gate drive)
iocp_power
iOCP_level Δi
tdelay
Figure 11 OCP protection implementation structure

Design guide IDP2303(A)
PFC design
Application Note 17 Revision 2.0
2017-05-03
A spradsheet-based calculation example for selecting the current sense resistor and the OCP tolerance is
shown in Figure 12.

Design guide IDP2303(A)
PFC design
Application Note 18 Revision 2.0
2017-05-03
Figure 12 Accurate calculation of OCP tolerance

Design guide IDP2303(A)
PFC design
Application Note 19 Revision 2.0
2017-05-03
It can be seen from the calculation that the actual tolerance of current and power can be very high. Methods
to reduce tolerances include:
Reduce the tolerance of the shunt resistor
Reduce the tolerance of the PFC choke
Reduce the value of R and C for the RC filter to reduce the delay
The above calculation is accurate, but is relatively complicated, and requires input data from actual
measurements on a real power board (e.g. external propagation delay). A faster and simpler way to obtain a
value for the current sense resistor is for customers to use the spreadsheet calculation to finalize the value
after the power board is built.
󰇛󰇜
󰇛󰇜 󰇛󰇜
Where is the OCP threshold gain error, is the gain of RC filter and is the estimated error
due to the internal and external propagation delay.
3.3.4.2 Verification of PFC inductance with OCP tolerance
The maximum peak current allowed by the OCP (considering the tolerance) can be obtained from the
spreadsheet calculation results and then applied to the equation below to verify the Bmax of the PFC
inductance: 
  
This value is less than the saturation magnetic flux density (B) of 0.35 T (PC40 magnetic material). Therefore,
the PFC choke will not saturate under worst case conditions.
3.3.5 Frequency law for multi-mode PFC
3.3.5.1 Multimode PFC
For a PFC circuit operating in Critical Conduction Mode (CrCM), the MOSFET is turned on with a constant on-
time throughout the complete AC half cycle and the off-time varies during the AC half cycle depending on
the instantaneous input voltage applied. A new switching cycle starts just after the inductor current reaches
zero. CrCM is also equivalent to quasi-resonant switching at the first inductor current valley or QR1
operation.
CrCM is ideal for full load operation, where the constant on-time is large. However, the constant on-time
reduces at light load, resulting in very high switching frequency - particularly near the zero crossings of the
input voltage. The high switching frequency will increase the switching losses, resulting in poor efficiency at
light load.
The multimode PFC control can lower the switching frequency by adding an additional delay ( ) into each
switching cycle through selecting further inductor current valleys (matching also with valleys of VDS of
MOSFET) to achieve QR2, QR3 and up to QR10 operation. Figure 13 illustrates the QR2 valley switching in
multimode PFC control as an example.

Design guide IDP2303(A)
PFC design
Application Note 20 Revision 2.0
2017-05-03
iS
iL,ave
ig/iL
Tsw Tsw
0
0
ton
tcyc
iL,pk
QR2
iL,pk
iL,sampled
pkL
i,
2
1
QR1
2
on
t
0t
QR1
4
osc
T
toff
tw
t
t
Figure 13 Current and timing in QR2 operation
3.3.5.2 Frequency law
A frequency law consisting of a maximum switching frequency and the minimum switching
frequency  is defined for the valley selection (QRN). In this way, the switching frequency is limited to
the defined range and efficiency at light load can be improved. An illustration of the frequency law is shown
in Figure 14.