Intel 80C188EC User manual

80C186EC/80C188EC
Microprocessor
User’s Manual

80C186EC/80C188EC
Microprocessor
User’s Manual
1995 Order Number 272047-003

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infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions
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© INTEL CORPORATION, 1995

iii
CONTENTS
CHAPTER 1
INTRODUCTION
1.1 HOW TO USE THIS MANUAL....................................................................................... 1-2
1.2 RELATED DOCUMENTS.............................................................................................. 1-3
1.3 ELECTRONIC SUPPORT SYSTEMS........................................................................... 1-4
1.3.1 FaxBack Service .......................................................................................................1-4
1.3.2 Bulletin Board System (BBS) ....................................................................................1-5
1.3.2.1 How to Find
Ap BUILDER Software and Hypertext Documents on the BBS ...1-6
1.3.3 CompuServe Forums ................................................................................................1-6
1.3.4 World Wide Web .......................................................................................................1-6
1.4 TECHNICAL SUPPORT................................................................................................ 1-6
1.5 PRODUCT LITERATURE.............................................................................................. 1-7
1.6 TRAINING CLASSES.................................................................................................... 1-7
CHAPTER 2
OVERVIEW OF THE 80C186 FAMILY ARCHITECTURE
2.1 ARCHITECTURAL OVERVIEW .................................................................................... 2-1
2.1.1 Execution Unit ...........................................................................................................2-2
2.1.2 Bus Interface Unit .....................................................................................................2-3
2.1.3 General Registers .....................................................................................................2-4
2.1.4 Segment Registers ...................................................................................................2-5
2.1.5 Instruction Pointer .....................................................................................................2-6
2.1.6 Flags .........................................................................................................................2-7
2.1.7 Memory Segmentation ..............................................................................................2-8
2.1.8 Logical Addresses ...................................................................................................2-10
2.1.9 Dynamically Relocatable Code ...............................................................................2-13
2.1.10 Stack Implementation .............................................................................................2-15
2.1.11 Reserved Memory and I/O Space ...........................................................................2-15
2.2 SOFTWARE OVERVIEW............................................................................................ 2-17
2.2.1 Instruction Set .........................................................................................................2-17
2.2.1.1 Data Transfer Instructions .............................................................................2-18
2.2.1.2 Arithmetic Instructions ...................................................................................2-19
2.2.1.3 Bit Manipulation Instructions .........................................................................2-21
2.2.1.4 String Instructions ..........................................................................................2-22
2.2.1.5 Program Transfer Instructions .......................................................................2-23
2.2.1.6 Processor Control Instructions ......................................................................2-27
2.2.2 Addressing Modes ..................................................................................................2-27
2.2.2.1 Register and Immediate Operand Addressing Modes ...................................2-27
2.2.2.2 Memory Addressing Modes ...........................................................................2-28
2.2.2.3 I/O Port Addressing .......................................................................................2-36
2.2.2.4 Data Types Used in the 80C186 Modular Core Family .................................2-37

CONTENTS
iv
2.3 INTERRUPTS AND EXCEPTION HANDLING............................................................ 2-39
2.3.1 Interrupt/Exception Processing ...............................................................................2-39
2.3.1.1 Non-Maskable Interrupts ...............................................................................2-42
2.3.1.2 Maskable Interrupts .......................................................................................2-42
2.3.1.3 Exceptions .....................................................................................................2-42
2.3.2 Software Interrupts ..................................................................................................2-44
2.3.3 Interrupt Latency .....................................................................................................2-44
2.3.4 Interrupt Response Time ........................................................................................2-45
2.3.5 Interrupt and Exception Priority ...............................................................................2-46
CHAPTER 3
BUS INTERFACE UNIT
3.1 MULTIPLEXED ADDRESS AND DATA BUS................................................................ 3-1
3.2 ADDRESS AND DATA BUS CONCEPTS..................................................................... 3-1
3.2.1 16-Bit Data Bus .........................................................................................................3-1
3.2.2 8-Bit Data Bus ...........................................................................................................3-5
3.3 MEMORY AND I/O INTERFACES................................................................................. 3-6
3.3.1 16-Bit Bus Memory and I/O Requirements ...............................................................3-7
3.3.2 8-Bit Bus Memory and I/O Requirements .................................................................3-7
3.4 BUS CYCLE OPERATION............................................................................................ 3-7
3.4.1 Address/Status Phase ............................................................................................3-10
3.4.2 Data Phase .............................................................................................................3-13
3.4.3 Wait States ..............................................................................................................3-13
3.4.4 Idle States ...............................................................................................................3-18
3.5 BUS CYCLES.............................................................................................................. 3-20
3.5.1 Read Bus Cycles ....................................................................................................3-20
3.5.1.1 Refresh Bus Cycles .......................................................................................3-22
3.5.2 Write Bus Cycles .....................................................................................................3-23
3.5.3 Interrupt Acknowledge Bus Cycle ...........................................................................3-26
3.5.3.1 System Design Considerations .....................................................................3-28
3.5.4 HALT Bus Cycle ......................................................................................................3-29
3.5.5 Temporarily Exiting the HALT Bus State .................................................................3-32
3.5.6 Exiting HALT ...........................................................................................................3-34
3.6 SYSTEM DESIGN ALTERNATIVES ........................................................................... 3-36
3.6.1 Buffering the Data Bus ............................................................................................3-37
3.6.2 Synchronizing Software and Hardware Events .......................................................3-39
3.6.3 Using a Locked Bus ................................................................................................3-40
3.7 MULTI-MASTER BUS SYSTEM DESIGNS................................................................. 3-41
3.7.1 Entering Bus HOLD ................................................................................................3-41
3.7.1.1 HOLD Bus Latency ........................................................................................3-42
3.7.1.2 Refresh Operation During a Bus HOLD ........................................................3-43
3.7.2 Exiting HOLD ..........................................................................................................3-45
3.8 BUS CYCLE PRIORITIES........................................................................................... 3-46

v
CONTENTS
CHAPTER 4
PERIPHERAL CONTROL BLOCK
4.1 PERIPHERAL CONTROL REGISTERS........................................................................ 4-1
4.2 PCB RELOCATION REGISTER.................................................................................... 4-1
4.3 RESERVED LOCATIONS ............................................................................................. 4-4
4.4 ACCESSING THE PERIPHERAL CONTROL BLOCK.................................................. 4-4
4.4.1 Bus Cycles ...............................................................................................................4-4
4.4.2 READY Signals and Wait States .............................................................................4-4
4.4.3 F-Bus Operation .......................................................................................................4-5
4.4.3.1 Writing the PCB Relocation Register ...............................................................4-6
4.4.3.2 Accessing the Peripheral Control Registers ....................................................4-6
4.4.3.3 Accessing Reserved Locations .......................................................................4-6
4.5 SETTING THE PCB BASE LOCATION......................................................................... 4-6
4.5.1 Considerations for the 80C187 Math Coprocessor Interface ....................................4-7
CHAPTER 5
CLOCK GENERATION AND POWER MANAGEMENT
5.1 CLOCK GENERATION.................................................................................................. 5-1
5.1.1 Crystal Oscillator .......................................................................................................5-1
5.1.1.1 Oscillator Operation .........................................................................................5-2
5.1.1.2 Selecting Crystals ............................................................................................5-5
5.1.2 Using an External Oscillator ......................................................................................5-6
5.1.3 Output from the Clock Generator ..............................................................................5-6
5.1.4 Reset and Clock Synchronization .............................................................................5-6
5.2 POWER MANAGEMENT............................................................................................. 5-10
5.2.1 Idle Mode ................................................................................................................5-11
5.2.1.1 Entering Idle Mode ........................................................................................5-11
5.2.1.2 Bus Operation During Idle Mode ...................................................................5-13
5.2.1.3 Leaving Idle Mode .........................................................................................5-14
5.2.1.4 Example Idle Mode Initialization Code ..........................................................5-15
5.2.2 Powerdown Mode ...................................................................................................5-16
5.2.2.1 Entering Powerdown Mode ...........................................................................5-17
5.2.2.2 Leaving Powerdown Mode ............................................................................5-18
5.2.3 Power-Save Mode ..................................................................................................5-19
5.2.3.1 Entering Power-Save Mode ..........................................................................5-20
5.2.3.2 Leaving Power-Save Mode ...........................................................................5-22
5.2.3.3 Example Power-Save Initialization Code .......................................................5-22
5.2.4 Implementing a Power Management Scheme ........................................................5-24
CHAPTER 6
CHIP-SELECT UNIT
6.1 COMMON METHODS FOR GENERATING CHIP-SELECTS....................................... 6-1
6.2 CHIP-SELECT UNIT FEATURES AND BENEFITS ...................................................... 6-1
6.3 CHIP-SELECT UNIT FUNCTIONAL OVERVIEW ......................................................... 6-2

CONTENTS
vi
6.4 PROGRAMMING........................................................................................................... 6-5
6.4.1 Initialization Sequence ..............................................................................................6-6
6.4.2 Start Address ..........................................................................................................6-10
6.4.3 Stop Address ..........................................................................................................6-10
6.4.4 Enabling and Disabling Chip-Selects ......................................................................6-11
6.4.5 Bus Wait State and Ready Control .........................................................................6-11
6.4.6 Overlapping Chip-Selects .......................................................................................6-12
6.4.7 Memory or I/O Bus Cycle Decoding ........................................................................6-14
6.4.8 Programming Considerations ..................................................................................6-14
6.5 CHIP-SELECTS AND BUS HOLD............................................................................... 6-15
6.6 EXAMPLES ................................................................................................................. 6-15
6.6.1 Example 1: Typical System Configuration ..............................................................6-15
6.6.2 Example 2: Detecting Attempts to Access Guarded Memory .................................6-20
CHAPTER 7
REFRESH CONTROL UNIT
7.1 THE ROLE OF THE REFRESH CONTROL UNIT......................................................... 7-2
7.2 REFRESH CONTROL UNIT CAPABILITIES................................................................. 7-2
7.3 REFRESH CONTROL UNIT OPERATION.................................................................... 7-2
7.4 REFRESH ADDRESSES............................................................................................... 7-4
7.5 REFRESH BUS CYCLES.............................................................................................. 7-5
7.6 GUIDELINES FOR DESIGNING DRAM CONTROLLERS............................................ 7-5
7.7 PROGRAMMING THE REFRESH CONTROL UNIT..................................................... 7-7
7.7.1 Calculating the Refresh Interval ................................................................................7-7
7.7.2 Refresh Control Unit Registers .................................................................................7-7
7.7.2.1 Refresh Base Address Register ......................................................................7-8
7.7.2.2 Refresh Clock Interval Register .......................................................................7-8
7.7.2.3 Refresh Control Register .................................................................................7-9
7.7.2.4 Refresh Address Register .............................................................................7-10
7.7.3 Programming Example ...........................................................................................7-11
7.8 REFRESH OPERATION AND BUS HOLD.................................................................. 7-13
CHAPTER 8
INTERRUPT CONTROL UNIT
8.1 FUNCTIONAL OVERVIEW: THE INTERRUPT CONTROLLER................................... 8-1
8.2 INTERRUPT PRIORITY AND NESTING....................................................................... 8-4
8.3 OVERVIEW OF THE 8259A ARCHITECTURE............................................................. 8-4
8.3.1 A Typical Interrupt Sequence Using the 8259A Module ...........................................8-6
8.3.2 Interrupt Requests ....................................................................................................8-9
8.3.2.1 Edge and Level Triggering ..............................................................................8-9
8.3.2.2 The Interrupt Request Register .......................................................................8-9
8.3.2.3 Spurious Interrupts ........................................................................................8-10
8.3.3 The Priority Resolver and Priority Resolution .........................................................8-10

vii
CONTENTS
8.3.3.1 Default (Fixed) Priority ...................................................................................8-11
8.3.3.2 Changing the Default Priority: Specific Rotation ............................................8-11
8.3.3.3 Changing the Default Priority: Automatic Rotation ........................................8-12
8.3.4 The In-Service Register ..........................................................................................8-12
8.3.4.1 Clearing the In-Service Bits: Non-Specific End-Of-Interrupt ..........................8-13
8.3.4.2 Clearing the In-Service Bits: Specific End-Of-Interrupt .................................8-13
8.3.4.3 Automatic End-Of-Interrupt Mode .................................................................8-13
8.3.5 Masking Interrupts ..................................................................................................8-14
8.3.6 Cascading 8259As ..................................................................................................8-14
8.3.6.1 Master/Slave Connection ..............................................................................8-14
8.3.6.2 The Cascaded Interrupt Acknowledge Cycle: An Example ...........................8-16
8.3.6.3 Master Cascade Configuration ......................................................................8-17
8.3.6.4 Slave ID .........................................................................................................8-17
8.3.6.5 Issuing EOI Commands in a Cascaded System ............................................8-17
8.3.6.6 Spurious Interrupts in a Cascaded System ...................................................8-18
8.3.7 Alternate Modes of Operation: Special Mask Mode ................................................8-19
8.3.8 Alternate Modes of Operation: Special Fully Nested Mode ....................................8-19
8.3.9 Alternate Modes of Operation: The Poll Command ................................................8-20
8.4 PROGRAMMING THE 8259A MODULE..................................................................... 8-20
8.4.1 Initialization and Operation Command Words .........................................................8-20
8.4.2 Programming Sequence and Register Addressing .................................................8-21
8.4.3 Initializing the 8259A Module ..................................................................................8-21
8.4.3.1 8259A Initialization Sequence .......................................................................8-21
8.4.3.2 ICW1: Edge/Level Mode, Single/Cascade Mode ..........................................8-23
8.4.3.3 ICW2: Base Interrupt Type ............................................................................8-25
8.4.3.4 ICW3: Cascaded Pins/Slave Address ...........................................................8-26
8.4.3.5 ICW4: Special Fully Nested Mode, EOI Mode, Factory Test Modes .............8-26
8.4.4 The Operation Command Words ............................................................................8-30
8.4.4.1 Masking Interrupts: OCW1 ............................................................................8-30
8.4.4.2 EOI And Interrupt Priority: OCW2 .................................................................8-30
8.4.4.3 Special Mask Mode, Poll Mode and Register Reading: OCW3 .....................8-34
8.5 MODULE INTEGRATION: THE 80C186EC INTERRUPT CONTROL UNIT............... 8-36
8.5.1 Internal Interrupt Sources .......................................................................................8-36
8.5.1.1 Directly Supported Internal Interrupt Sources ...............................................8-37
8.5.1.2 Indirectly Supported Internal Interrupt Sources .............................................8-38
8.5.1.3 Using the Interrupt Request Latch Registers ................................................8-39
8.5.1.4 Using the Interrupt Request Latch Registers to Debug Interrupt Handlers ...8-40
8.6 HARDWARE CONSIDERATIONS WITH THE INTERRUPT CONTROL UNIT........... 8-42
8.6.1 Interrupt Latency and Response Time ....................................................................8-43
8.6.2 Resetting the Edge Detector ...................................................................................8-43
8.6.3 Ready Generation ...................................................................................................8-44
8.6.4 Connecting External 8259A Devices ......................................................................8-44
8.6.4.1 The External INTA Cycle ...............................................................................8-45
8.6.4.2 Timing Constraints ........................................................................................8-46
8.7 MODULE EXAMPLES................................................................................................. 8-47

CONTENTS
viii
CHAPTER 9
TIMER/COUNTER UNIT
9.1 FUNCTIONAL OVERVIEW............................................................................................ 9-1
9.2 PROGRAMMING THE TIMER/COUNTER UNIT .......................................................... 9-6
9.2.1 Initialization Sequence ............................................................................................9-11
9.2.2 Clock Sources .........................................................................................................9-12
9.2.3 Counting Modes ......................................................................................................9-12
9.2.3.1 Retriggering ...................................................................................................9-13
9.2.4 Pulsed and Variable Duty Cycle Output ..................................................................9-14
9.2.5 Enabling/Disabling Counters ...................................................................................9-15
9.2.6 Timer Interrupts .......................................................................................................9-16
9.2.7 Programming Considerations ..................................................................................9-16
9.3 TIMING........................................................................................................................ 9-16
9.3.1 Input Setup and Hold Timings .................................................................................9-16
9.3.2 Synchronization and Maximum Frequency .............................................................9-17
9.3.2.1 Timer/Counter Unit Application Examples .....................................................9-17
9.3.3 Real-Time Clock .....................................................................................................9-17
9.3.4 Square-Wave Generator .........................................................................................9-17
9.3.5 Digital One-Shot ......................................................................................................9-17
CHAPTER 10
DIRECT MEMORY ACCESS UNIT
10.1 FUNCTIONAL OVERVIEW.......................................................................................... 10-1
10.1.1 The DMA Transfer ..................................................................................................10-1
10.1.1.1 DMA Transfer Directions ...............................................................................10-3
10.1.1.2 Byte and Word Transfers ..............................................................................10-3
10.1.2 Source and Destination Pointers ............................................................................10-3
10.1.3 DMA Requests ........................................................................................................10-3
10.1.4 External Requests ...................................................................................................10-4
10.1.4.1 Source Synchronization ................................................................................10-5
10.1.4.2 Destination Synchronization ..........................................................................10-5
10.1.5 Internal Requests ....................................................................................................10-6
10.1.5.1 Integrated Peripheral Requests .....................................................................10-6
10.1.5.2 Timer 2-Initiated Transfers ............................................................................10-6
10.1.5.3 Serial Communications Unit Transfers ..........................................................10-7
10.1.5.4 Unsynchronized Transfers ............................................................................10-7
10.1.6 DMA Transfer Counts .............................................................................................10-7
10.1.7 Termination and Suspension of DMA Transfers .....................................................10-7
10.1.7.1 Termination at Terminal Count ......................................................................10-8
10.1.7.2 Software Termination ....................................................................................10-8
10.1.7.3 Suspension of DMA During NMI ...................................................................10-8
10.1.7.4 Software Suspension ....................................................................................10-8
10.1.8 DMA Unit Interrupts ................................................................................................10-8
10.1.9 DMA Cycles and the BIU ........................................................................................10-8
10.1.10 The Two-Channel DMA Module ..............................................................................10-9
10.1.10.1 DMA Channel Arbitration ...............................................................................10-9

ix
CONTENTS
10.1.11 DMA Module Integration .......................................................................................10-12
10.1.11.1 DMA Unit Structure .....................................................................................10-13
10.2 PROGRAMMING THE DMA UNIT ............................................................................ 10-15
10.2.1 DMA Channel Parameters ....................................................................................10-15
10.2.1.1 Programming the Source and Destination Pointers ....................................10-15
10.2.1.2 Selecting Byte or Word Size Transfers ........................................................10-19
10.2.1.3 Selecting the Source of DMA Requests ......................................................10-22
10.2.1.4 Arming the DMA Channel ............................................................................10-23
10.2.1.5 Selecting Channel Synchronization .............................................................10-23
10.2.1.6 Programming the Transfer Count Options ...................................................10-24
10.2.1.7 Generating Interrupts on Terminal Count ....................................................10-25
10.2.1.8 Setting the Relative Priority of a Channel ....................................................10-26
10.2.2 Setting the Inter-Module Priority ...........................................................................10-26
10.2.3 Using the DMA Unit with the Serial Ports ..............................................................10-26
10.2.4 Suspension of DMA Transfers Using the DMA Halt Bits .......................................10-27
10.2.5 Initializing the DMA Unit ........................................................................................10-27
10.3 HARDWARE CONSIDERATIONS AND THE DMA UNIT ......................................... 10-28
10.3.1 DRQ Pin Timing Requirements .............................................................................10-29
10.3.2 DMA Latency ........................................................................................................10-29
10.3.3 DMA Transfer Rates .............................................................................................10-29
10.3.4 Generating a DMA Acknowledge ..........................................................................10-30
10.4 DMA UNIT EXAMPLES............................................................................................. 10-30
CHAPTER 11
SERIAL COMMUNICATIONS UNIT
11.1 INTRODUCTION ......................................................................................................... 11-1
11.1.1 Asynchronous Communications ..............................................................................11-1
11.1.1.1 RX Machine ...................................................................................................11-2
11.1.1.2 TX Machine ...................................................................................................11-4
11.1.1.3 Modes 1, 3 and 4 ...........................................................................................11-6
11.1.1.4 Mode 2 ..........................................................................................................11-7
11.1.2 Synchronous Communications ...............................................................................11-8
11.2 PROGRAMMING......................................................................................................... 11-9
11.2.1 Baud Rates ...........................................................................................................11-10
11.2.2 Asynchronous Mode Programming .......................................................................11-13
11.2.2.1 Modes 1, 3 and 4 for Stand-alone Serial Communications .........................11-13
11.2.2.2 Modes 2 and 3 for Multiprocessor Communications ...................................11-14
11.2.2.3 Sending and Receiving a Break Character .................................................11-14
11.2.3 Programming in Mode 0 ........................................................................................11-18
11.3 HARDWARE CONSIDERATIONS FOR THE SERIAL PORT................................... 11-18
11.3.1 CTS Pin Timings ...................................................................................................11-18
11.3.2 BCLK Pin Timings .................................................................................................11-18
11.3.3 Mode 0 Timings ....................................................................................................11-20
11.3.3.1 CLKOUT as Baud Timebase Clock .............................................................11-20
11.3.3.2 BCLK as Baud Timebase Clock ..................................................................11-21

CONTENTS
x
11.4 SERIAL COMMUNICATIONS UNIT INTERRUPTS.................................................. 11-21
11.5 SERIAL PORT EXAMPLES....................................................................................... 11-21
11.5.1 Asynchronous Mode Example ..............................................................................11-21
11.5.2 Mode 0 Example ...................................................................................................11-23
11.5.3 Master/Slave Example ..........................................................................................11-24
CHAPTER 12
WATCHDOG TIMER UNIT
12.1 FUNCTIONAL OVERVIEW.......................................................................................... 12-1
12.2 USING THE WATCHDOG TIMER AS A SYSTEM WATCHDOG ............................... 12-1
12.2.1 Reloading the Watchdog Timer Down Counter .......................................................12-3
12.2.2 Watchdog Timer Reload Value ...............................................................................12-4
12.2.3 Initialization .............................................................................................................12-5
12.3 USING THE WATCHDOG TIMER AS A GENERAL-PURPOSE TIMER .................... 12-6
12.4 DISABLING THE WATCHDOG TIMER....................................................................... 12-6
12.5 WATCHDOG TIMER REGISTERS.............................................................................. 12-8
12.6 INITIALIZATION EXAMPLE....................................................................................... 12-12
CHAPTER 13
INPUT/OUTPUT PORTS
13.1 FUNCTIONAL OVERVIEW.......................................................................................... 13-1
13.1.1 Bidirectional Port .....................................................................................................13-1
13.1.2 Output Port ..............................................................................................................13-3
13.1.3 Open-Drain Bidirectional Port .................................................................................13-3
13.1.4 Port Pin Organization ..............................................................................................13-3
13.1.4.1 Port 1 Organization .......................................................................................13-6
13.1.4.2 Port 2 Organization .......................................................................................13-6
13.1.4.3 Port 3 Organization .......................................................................................13-7
13.2 PROGRAMMING THE I/O PORT UNIT....................................................................... 13-7
13.2.1 Port Control Register ..............................................................................................13-7
13.2.2 Port Direction Register ............................................................................................13-8
13.2.3 Port Data Latch Register .........................................................................................13-9
13.2.4 Port Pin State Register .........................................................................................13-10
13.2.5 Initializing the I/O Ports .........................................................................................13-11
13.3 PROGRAMMING EXAMPLE..................................................................................... 13-12
CHAPTER 14
MATH COPROCESSING
14.1 OVERVIEW OF MATH COPROCESSING.................................................................. 14-1
14.2 AVAILABILITY OF MATH COPROCESSING.............................................................. 14-1
14.3 THE 80C187 MATH COPROCESSOR........................................................................ 14-2
14.3.1 80C187 Instruction Set ...........................................................................................14-2
14.3.1.1 Data Transfer Instructions .............................................................................14-3

xi
CONTENTS
14.3.1.2 Arithmetic Instructions ...................................................................................14-3
14.3.1.3 Comparison Instructions ................................................................................14-5
14.3.1.4 Transcendental Instructions ..........................................................................14-5
14.3.1.5 Constant Instructions .....................................................................................14-6
14.3.1.6 Processor Control Instructions ......................................................................14-6
14.3.2 80C187 Data Types ................................................................................................14-7
14.4 MICROPROCESSOR AND COPROCESSOR OPERATION...................................... 14-7
14.4.1 Clocking the 80C187 .............................................................................................14-10
14.4.2 Processor Bus Cycles Accessing the 80C187 ......................................................14-10
14.4.3 System Design Tips ..............................................................................................14-11
14.4.4 Exception Trapping ...............................................................................................14-13
14.5 EXAMPLE MATH COPROCESSOR ROUTINES...................................................... 14-13
CHAPTER 15
ONCE MODE
15.1 ENTERING/LEAVING ONCE MODE........................................................................... 15-1
APPENDIX A
80C186 INSTRUCTION SET ADDITIONS AND EXTENSIONS
A.1 80C186 INSTRUCTION SET ADDITIONS................................................................... A-1
A.1.1 Data Transfer Instructions ......................................................................................A-1
A.1.2 String Instructions ...................................................................................................A-2
A.1.3 High-Level Instructions ...........................................................................................A-2
A.2 80C186 INSTRUCTION SET ENHANCEMENTS......................................................... A-8
A.2.1 Data Transfer Instructions ......................................................................................A-8
A.2.2 Arithmetic Instructions ............................................................................................A-9
A.2.3 Bit Manipulation Instructions ...................................................................................A-9
A.2.3.1 Shift Instructions .............................................................................................A-9
A.2.3.2 Rotate Instructions .......................................................................................A-10
APPENDIX B
INPUT SYNCHRONIZATION
B.1 WHY SYNCHRONIZERS ARE REQUIRED................................................................. B-1
B.2 ASYNCHRONOUS PINS.............................................................................................. B-2
APPENDIX C
INSTRUCTION SET DESCRIPTIONS
APPENDIX D
INSTRUCTION SET OPCODES AND CLOCK CYCLES
INDEX

CONTENTS
xii
FIGURES
Figure Page
2-1 Simplified Functional Block Diagram of the 80C186 Family CPU................................2-2
2-2 Physical Address Generation.......................................................................................2-3
2-3 General Registers ........................................................................................................2-4
2-4 Segment Registers.......................................................................................................2-6
2-5 Processor Status Word ................................................................................................2-9
2-6 Segment Locations in Physical Memory.....................................................................2-10
2-7 Currently Addressable Segments...............................................................................2-11
2-8 Logical and Physical Address ....................................................................................2-12
2-9 Dynamic Code Relocation..........................................................................................2-14
2-10 Stack Operation..........................................................................................................2-16
2-11 Flag Storage Format ..................................................................................................2-19
2-12 Memory Address Computation...................................................................................2-29
2-13 Direct Addressing.......................................................................................................2-30
2-14 Register Indirect Addressing......................................................................................2-31
2-15 Based Addressing......................................................................................................2-31
2-16 Accessing a Structure with Based Addressing...........................................................2-32
2-17 Indexed Addressing....................................................................................................2-33
2-18 Accessing an Array with Indexed Addressing............................................................2-33
2-19 Based Index Addressing ............................................................................................2-34
2-20 Accessing a Stacked Array with Based Index Addressing.........................................2-35
2-21 String Operand...........................................................................................................2-36
2-22 I/O Port Addressing....................................................................................................2-36
2-23 80C186 Modular Core Family Supported Data Types................................................2-38
2-24 Interrupt Control Unit..................................................................................................2-39
2-25 Interrupt Vector Table.................................................................................................2-40
2-26 Interrupt Sequence.....................................................................................................2-41
2-27 Interrupt Response Factors........................................................................................2-46
2-28 Simultaneous NMI and Exception ..............................................................................2-47
2-29 Simultaneous NMI and Single Step Interrupts............................................................2-48
2-30 Simultaneous NMI, Single Step and Maskable Interrupt............................................2-49
3-1 Physical Data Bus Models............................................................................................3-2
3-2 16-Bit Data Bus Byte Transfers....................................................................................3-3
3-3 16-Bit Data Bus Even Word Transfers.........................................................................3-4
3-4 16-Bit Data Bus Odd Word Transfers...........................................................................3-5
3-5 8-Bit Data Bus Word Transfers.....................................................................................3-6
3-6 Typical Bus Cycle.........................................................................................................3-8
3-7 T-State Relation to CLKOUT........................................................................................3-8
3-8 BIU State Diagram .......................................................................................................3-9
3-9 T-State and Bus Phases ............................................................................................3-10
3-10 Address/Status Phase Signal Relationships..............................................................3-11
3-11 Demultiplexing Address Information...........................................................................3-12
3-12 Data Phase Signal Relationships...............................................................................3-14
3-13 Typical Bus Cycle with Wait States............................................................................3-15
3-14 READY Pin Block Diagram.........................................................................................3-15

xiii
CONTENTS
FIGURES
Figure Page
3-15 Generating a Normally Not-Ready Bus Signal...........................................................3-16
3-16 Generating a Normally Ready Bus Signal..................................................................3-17
3-17 Normally Not-Ready System Timing ..........................................................................3-18
3-18 Normally Ready System Timings ...............................................................................3-19
3-19 Typical Read Bus Cycle .............................................................................................3-22
3-20 Read-Only Device Interface .......................................................................................3-23
3-21 Typical Write Bus Cycle..............................................................................................3-24
3-22 16-Bit Bus Read/Write Device Interface.....................................................................3-25
3-23 Interrupt Acknowledge Bus Cycle...............................................................................3-27
3-24 Typical 82C59A Interface...........................................................................................3-28
3-25 HALT Bus Cycle.........................................................................................................3-31
3-26 Returning to HALT After a HOLD/HLDA Bus Exchange............................................3-32
3-27 Returning to HALT After a Refresh Bus Cycle...........................................................3-33
3-28 Returning to HALT After a DMA Bus Cycle................................................................3-34
3-29 Exiting HALT (Powerdown Mode) ..............................................................................3-35
3-30 Exiting HALT (Active/Idle Mode).................................................................................3-36
3-31 DEN and DT/R Timing Relationships.........................................................................3-37
3-32 Buffered AD Bus System............................................................................................3-38
3-33 Qualifying DEN with Chip-Selects..............................................................................3-39
3-34 Timing Sequence Entering HOLD..............................................................................3-42
3-35 Refresh Request During HOLD..................................................................................3-44
3-36 Latching HLDA ...........................................................................................................3-45
3-37 Exiting HOLD..............................................................................................................3-46
4-1 PCB Relocation Register..............................................................................................4-2
5-1 Clock Generator...........................................................................................................5-1
5-2 Ideal Operation of Pierce Oscillator..............................................................................5-2
5-3 Crystal Connections to Microprocessor........................................................................5-3
5-4 Equations for Crystal Calculations................................................................................5-4
5-5 Simple RC Circuit for Powerup Reset ..........................................................................5-7
5-6 Cold Reset Waveform ..................................................................................................5-8
5-7 Warm Reset Waveform................................................................................................5-9
5-8 Clock Synchronization at Reset..................................................................................5-10
5-9 Power Control Register ..............................................................................................5-12
5-10 Entering Idle Mode.....................................................................................................5-13
5-11 HOLD/HLDA During Idle Mode...................................................................................5-14
5-12 Entering Powerdown Mode ........................................................................................5-17
5-13 Powerdown Timer Circuit ...........................................................................................5-19
5-14 Power-Save Register .................................................................................................5-21
5-15 Power-Save Clock Transition.....................................................................................5-22
6-1 Common Chip-Select Generation Methods..................................................................6-2
6-2 Chip-Select Block Diagram...........................................................................................6-3
6-3 Chip-Select Relative Timings.......................................................................................6-4
6-4 UCS Reset Configuration.............................................................................................6-5
6-5 START Register Definition...........................................................................................6-7

CONTENTS
xiv
FIGURES
Figure Page
6-6 STOP Register Definition.............................................................................................6-8
6-7 Wait State and Ready Control Functions...................................................................6-12
6-8 Overlapping Chip-Selects...........................................................................................6-13
6-9 Using Chip-Selects During HOLD ..............................................................................6-15
6-10 Typical System...........................................................................................................6-16
6-11 Guarded Memory Detector.........................................................................................6-20
7-1 Refresh Control Unit Block Diagram.............................................................................7-1
7-2 Refresh Control Unit Operation Flow Chart..................................................................7-3
7-3 Refresh Address Formation..........................................................................................7-4
7-4 Suggested DRAM Control Signal Timing Relationships...............................................7-6
7-5 Formula for Calculating Refresh Interval for RFTIME Register....................................7-7
7-6 Refresh Base Address Register...................................................................................7-8
7-7 Refresh Clock Interval Register....................................................................................7-9
7-8 Refresh Control Register............................................................................................7-10
7-9 Refresh Address Register ..........................................................................................7-11
7-10 Regaining Bus Control to Run a DRAM Refresh Bus Cycle......................................7-14
8-1 Interrupt Control Unit Block Diagram............................................................................8-2
8-2 Interrupt Acknowledge Cycle........................................................................................8-3
8-3 8259A Module Block Diagram......................................................................................8-5
8-4 Priority Cell...................................................................................................................8-7
8-5 Spurious Interrupts.....................................................................................................8-10
8-6 Default Priority............................................................................................................8-11
8-7 Specific Rotation ........................................................................................................8-11
8-8 Automatic Rotation.....................................................................................................8-12
8-9 Typical Cascade Connection......................................................................................8-15
8-10 Spurious Interrupts in a Cascaded System................................................................8-18
8-11 8259A Module Initialization Sequence.......................................................................8-23
8-12 ICW1 Register............................................................................................................8-24
8-13 ICW2 Register............................................................................................................8-25
8-14 ICW3 Register — Master Cascade Configuration......................................................8-27
8-15 ICW3 Register — Slave ID.........................................................................................8-28
8-16 ICW4 Register............................................................................................................8-29
8-17 OCW1 — Interrupt Mask Register..............................................................................8-31
8-18 OCW2 Register ..........................................................................................................8-32
8-19 OCW3 Register ..........................................................................................................8-34
8-20 Poll Status Byte..........................................................................................................8-35
8-21 Interrupt Request Latch Register Function.................................................................8-37
8-22 Default Slave 8259 Module Priority............................................................................8-38
8-23 Multiplexed Interrupt Requests...................................................................................8-39
8-24 DMA Interrupt Request Latch Register.......................................................................8-40
8-25 Serial Communications Interrupt Request Latch Register..........................................8-41
8-26 Timer Interrupt Request Latch Register .....................................................................8-42
8-27 Interrupt Resolution Time...........................................................................................8-43
8-28 Resetting the Edge Detection Circuit..........................................................................8-44

xv
CONTENTS
FIGURES
Figure Page
8-29 Typical Cascade Connection for 82C59A-2...............................................................8-45
8-30 Software Wait State for External 82C59A-2...............................................................8-46
9-1 Timer/Counter Unit Block Diagram...............................................................................9-2
9-2 Counter Element Multiplexing and Timer Input Synchronization..................................9-3
9-3 Timers 0 and 1 Flow Chart...........................................................................................9-4
9-4 Timer/Counter Unit Output Modes................................................................................9-6
9-5 Timer 0 and Timer 1 Control Registers........................................................................9-7
9-6 Timer 2 Control Register ..............................................................................................9-9
9-7 Timer Count Registers................................................................................................9-10
9-8 Timer Maxcount Compare Registers..........................................................................9-11
9-9 TxOUT Signal Timing.................................................................................................9-15
10-1 Typical DMA Transfer.................................................................................................10-2
10-2 DMA Request Minimum Response Time ...................................................................10-4
10-3 Source-Synchronized Transfers.................................................................................10-5
10-4 Destination-Synchronized Transfers..........................................................................10-6
10-5 Two-Channel DMA Module......................................................................................10-10
10-6 Examples of DMA Priority.........................................................................................10-11
10-7 Internal DMA Request Multiplexer............................................................................10-12
10-8 80C186EC/C188EC DMA Unit.................................................................................10-14
10-9 DMA Source Pointer (High-Order Bits).....................................................................10-16
10-10 DMA Source Pointer (Low-Order Bits).....................................................................10-17
10-11 DMA Destination Pointer (High-Order Bits)..............................................................10-18
10-12 DMA Destination Pointer (Low-Order Bits)...............................................................10-19
10-13 DMA Control Register...............................................................................................10-20
10-14 DMA Module Priority Register..................................................................................10-24
10-15 Transfer Count Register...........................................................................................10-25
10-16 DMA Module HALT Register....................................................................................10-28
11-1 Typical 10-Bit Asynchronous Data Frame..................................................................11-2
11-2 RX Machine................................................................................................................11-3
11-3 TX Machine................................................................................................................11-5
11-4 Mode 1 Waveform......................................................................................................11-6
11-5 Mode 3 Waveform......................................................................................................11-7
11-6 Mode 4 Waveform......................................................................................................11-7
11-7 Mode 0 Waveforms ....................................................................................................11-8
11-8 Serial Receive Buffer Register (SxRBUF)..................................................................11-9
11-9 Serial Transmit Buffer Register (SxTBUF) ...............................................................11-10
11-10 Baud Rate Counter Register (BxCNT).....................................................................11-11
11-11 Baud Rate Compare Register (BxCMP)...................................................................11-12
11-12 Calculating the BxCMP Value for a Specific Baud Rate...........................................11-12
11-13 Serial Port Control Register (SxCON)......................................................................11-15
11-14 Serial Port Status Register (SxSTS).........................................................................11-16
11-15 CTS Recognition Sequence.....................................................................................11-19
11-16 BCLK Synchronization .............................................................................................11-19
11-17 Mode 0, BxCMP > 2.................................................................................................11-20

CONTENTS
xvi
FIGURES
Figure Page
11-18 Master/Slave Example .............................................................................................11-25
12-1 Block Diagram of the Watchdog Timer Unit ...............................................................12-2
12-2 Watchdog Timer Reset Circuit....................................................................................12-2
12-3 Generating Interrupts with the Watchdog Timer.........................................................12-3
12-4 WDTOUT Waveforms.................................................................................................12-6
12-5 WDT Reload Value (High)..........................................................................................12-9
12-6 WDT Reload Value (Low).........................................................................................12-10
12-7 WDT Count Value (High)..........................................................................................12-11
12-8 WDT Count Value (Low)...........................................................................................12-12
13-1 Simplified Logic Diagram of a Bidirectional Port Pin..................................................13-2
13-2 Simplified Logic Diagram of an Output Port Pin.........................................................13-4
13-3 Simplified Logic Diagram of an Open-Drain Bidirectional Port...................................13-5
13-4 Port Control Register (PxCON) ..................................................................................13-8
13-5 Port Direction Register (PxDIR)..................................................................................13-9
13-6 Port Data Latch Register (PxLTCH).........................................................................13-10
13-7 Port Pin State Register (PxPIN)...............................................................................13-11
14-1 80C187-Supported Data Types..................................................................................14-8
14-2 80C186 Modular Core Family/80C187 System Configuration....................................14-9
14-3 80C187 Configuration with a Partially Buffered Bus.................................................14-12
14-4 80C187 Exception Trapping via Processor Interrupt Pin..........................................14-14
15-1 Entering/Leaving ONCE Mode...................................................................................15-1
A-1 Formal Definition of ENTER........................................................................................A-3
A-2 Variable Access in Nested Procedures.......................................................................A-4
A-3 Stack Frame for Main at Level 1..................................................................................A-4
A-4 Stack Frame for Procedure A at Level 2 .....................................................................A-5
A-5 Stack Frame for Procedure B at Level 3 Called from A...............................................A-6
A-6 Stack Frame for Procedure C at Level 3 Called from B ..............................................A-7
B-1 Input Synchronization Circuit.......................................................................................B-1

xvii
CONTENTS
TABLES
Table Page
1-1 Comparison of 80C186 Modular Core Family Products...............................................1-2
1-2 Related Documents and Software................................................................................1-3
2-1 Implicit Use of General Registers.................................................................................2-5
2-2 Logical Address Sources............................................................................................2-13
2-3 Data Transfer Instructions..........................................................................................2-18
2-4 Arithmetic Instructions................................................................................................2-20
2-5 Arithmetic Interpretation of 8-Bit Numbers.................................................................2-21
2-6 Bit Manipulation Instructions ......................................................................................2-21
2-7 String Instructions.......................................................................................................2-22
2-8 String Instruction Register and Flag Use....................................................................2-23
2-9 Program Transfer Instructions....................................................................................2-25
2-10 Interpretation of Conditional Transfers.......................................................................2-26
2-11 Processor Control Instructions ...................................................................................2-27
2-12 Supported Data Types ...............................................................................................2-37
3-1 Bus Cycle Types ........................................................................................................3-12
3-2 Read Bus Cycle Types...............................................................................................3-20
3-3 Read Cycle Critical Timing Parameters......................................................................3-21
3-4 Write Bus Cycle Types...............................................................................................3-24
3-5 Write Cycle Critical Timing Parameters......................................................................3-26
3-6 HALT Bus Cycle Pin States........................................................................................3-30
3-7 Signal Condition Entering HOLD................................................................................3-42
4-1 Peripheral Control Block...............................................................................................4-3
5-1 Suggested Values for Inductor L1in Third Overtone Oscillator Circuit.........................5-4
5-2 Summary of Power Management Modes...................................................................5-24
6-1 Chip-Select Unit Registers...........................................................................................6-5
6-2 Memory and I/O Compare Addresses........................................................................6-10
6-3 Example Adjustments for Overlapping Chip-Selects..................................................6-14
7-1 Identification of Refresh Bus Cycles.............................................................................7-5
8-1 Operation Command Word Addressing......................................................................8-30
8-2 OCW2 Instruction Field Decoding..............................................................................8-32
9-1 Timer 0 and 1 Clock Sources.....................................................................................9-12
9-2 Timer Retriggering......................................................................................................9-13
10-1 DMA Unit Naming Conventions and Signal Connections.........................................10-13
11-1 BxCMP Values for Typical Baud Rates and CPU Frequencies................................11-13
13-1 Port 1 Multiplexing Options ........................................................................................13-6
13-2 Port 2 Multiplexing Options ........................................................................................13-6
13-3 Port 3 Multiplexing Options ........................................................................................13-7
14-1 80C187 Data Transfer Instructions.............................................................................14-3
14-2 80C187 Arithmetic Instructions...................................................................................14-4
14-3 80C187 Comparison Instructions...............................................................................14-5
14-4 80C187 Transcendental Instructions..........................................................................14-5
14-5 80C187 Constant Instructions....................................................................................14-6
14-6 80C187 Processor Control Instructions......................................................................14-6
14-7 80C187 I/O Port Assignments..................................................................................14-10

CONTENTS
xviii
TABLES
Table Page
C-1 Instruction Format Variables........................................................................................C-1
C-2 Instruction Operands...................................................................................................C-2
C-3 Flag Bit Functions........................................................................................................C-3
C-4 Instruction Set .............................................................................................................C-4
D-1 Operand Variables ......................................................................................................D-1
D-2 Instruction Set Summary.............................................................................................D-2
D-3 Machine Instruction Decoding Guide...........................................................................D-9
D-4 Mnemonic Encoding Matrix.......................................................................................D-20
D-5 Abbreviations for Mnemonic Encoding Matrix...........................................................D-22

xix
CONTENTS
EXAMPLES
Example Page
5-1 Initializing the Power Management Unit for Idle or Powerdown Mode.......................5-16
5-2 Initializing the Power Management Unit for Power-Save Mode.................................5-23
6-1 Initializing the Chip-Select Unit...................................................................................6-17
7-1 Initializing the Refresh Control Unit............................................................................7-12
8-1 Initializing the Interrupt Control Unit...........................................................................8-47
8-2 Template for a Simple Interrupt Handler ....................................................................8-50
8-3 Using the Poll Command............................................................................................8-51
9-1 Configuring a Real-Time Clock...................................................................................9-18
9-2 Configuring a Square-Wave Generator......................................................................9-21
9-3 Configuring a Digital One-Shot...................................................................................9-22
10-1 Initializing the DMA Unit ...........................................................................................10-31
10-2 DMA-Driven Serial Transfers....................................................................................10-34
10-3 Timed DMA Transfers..............................................................................................10-37
11-1 Asynchronous Mode 4 Example...............................................................................11-22
11-2 Mode 0 Example ......................................................................................................11-23
11-3 Master/Slave — Implementing the Master/Slave Routines......................................11-26
11-4 Master/Slave — The _select_slave Routine.............................................................11-27
11-5 Master/Slave — The slave_1 Routine......................................................................11-29
11-6 Master/Slave — The _send_slave_command Routine ............................................11-32
12-1 Reload Sequence (Peripheral Control Block Located in I/O Space)..........................12-4
12-2 Reload Sequence (Peripheral Control Block Located in Memory Space)..................12-5
12-3 Disabling the Watchdog Timer (Peripheral Control Block in I/O Space) ....................12-7
12-4 Disabling the Watchdog Timer (Peripheral Control Block in Memory Space)............12-8
12-5 Initializing the Watchdog Timer (Peripheral Control Block Located in I/O Space)....12-13
13-1 I/O Port Programming Example................................................................................13-12
14-1 Initialization Sequence for 80C187 Math Coprocessor ............................................14-15
14-2 Floating Point Math Routine Using FSINCOS..........................................................14-16