Intel 855GM Guide

Intel®855GM/855GME Chipset Platform
Design Guide
May 2004
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Document Number: 252616-004

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2 Intel®855GM/855GME Chipset Platform Design Guide
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py
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ht © Intel Cor
p
oration 2001-2004

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Intel® 855GM/855GME Chipset Platform Design Guide 3
Contents
1. Introduction .................................................................................................................................21
1.1. Referenced Documents .................................................................................................23
2. System Overview........................................................................................................................25
2.1. Platform Component Features.......................................................................................25
2.2. Intel 855GM Platform Component Features..................................................................26
2.2.1. Intel®Pentium®M Processor and Intel Celeron M Processor .......................26
2.2.2. Intel®855GM Chipset Graphics Memory Controller Hub (GMCH) ................27
2.2.2.1. Intel Pentium M Processor and Intel Celeron M Processor FSB
Support............................................................................................27
2.2.2.2. Integrated System Memory DRAM Controller ................................27
2.2.2.3. Internal Graphics Controller ............................................................27
2.2.2.4. Package/Power ...............................................................................28
2.2.3. Intel®82801DBM I/O Controller Hub 4-Mobile (ICH4-M)...............................28
2.2.4. Intel®Pro/Wireless Network Connection........................................................29
2.3. Intel 855GME Platform Component Features ...............................................................30
2.3.1. Intel Pentium®M Processor on 90 nm Process with 2 MB L2 Cache ...........30
2.3.2. Intel 855GME Chipset Graphics Memory Controller Hub (GMCH) ...............31
2.3.2.1. Accelerated Graphics Port (AGP) Interface....................................31
3. General Design Considerations .................................................................................................33
3.1. Nominal Board Stack-Up ...............................................................................................33
3.2. Alternate Stack Ups .......................................................................................................34
4. Intel Pentium M/Celeron M Front Side Bus Design Guidelines..................................................37
4.1. Intel Pentium M Processor / Intel Celeron M FSB Design Recommendations .............37
4.1.1. Recommended Stack-up Routing and Spacing Assumptions .......................37
4.1.1.1. Trace Space to Trace – Reference Plane Separation Ratio ..........37
4.1.1.2. Trace Space to Trace Width Ratio..................................................38
4.1.2. Common Clock Signals..................................................................................38
4.1.2.1. Processor Common Clock Signal Package Length Compensation39
4.1.3. Source Synchronous Signals General Routing Guidelines ...........................40
4.1.3.1. Source Synchronous Signal Length Matching Constraints ............43
4.1.3.2. Package Length Compensation......................................................43
4.1.3.3. Source Synchronous – Data Group................................................44
4.1.3.4. Source Synchronous – Address Group ..........................................45
4.1.3.5. Intel Pentium M / Intel Celeron M Processor and Intel
855GM/GME Chipset GMCH PSB Signal Package Lengths .........46
4.1.4. Asynchronous Signals....................................................................................49
4.1.4.1. Topology 1A: Open Drain (OD) Signals Driven by the Processor –
IERR#..............................................................................................50
4.1.4.2. Topology 1B: Open Drain (OD) Signals Driven by the Processor –
FERR# and THERMTRIP# .............................................................50
4.1.4.3. Topology 1C: Open Drain (OD) Signals Driven by the Processor –
PROCHOT# ....................................................................................51
4.1.4.4. Topology 2A: Open Drain (OD) Signals Driven by ICH4-M –
PWRGOOD.....................................................................................52
4.1.4.5. Topology 2B: CMOS Signals Driven by ICH4-M – DPSLP# ..........53
4.1.4.6. Topology 2C: CMOS Signals Driven by ICH4-M – LINT0/INTR,
LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK# ...........53
4.1.4.7. Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH –
INIT#................................................................................................54

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4.1.4.8. Voltage Translation Logic ............................................................... 55
4.1.5. Processor RESET# Signal ............................................................................ 55
4.1.5.1. Processor RESET# Routing Example............................................ 57
4.1.6. Processor and GMCH Host Clock Signals .................................................... 57
4.1.7. Processor GTLREF Layout and Routing Recommendations........................ 58
4.1.8. AGTL+ I/O Buffer Compensation .................................................................. 60
4.1.8.1. Processor AGTL+ I/O Buffer Compensation .................................. 60
4.1.9. Intel Pentium M / Intel Celeron M Front Side Bus Strapping and
Debug Port..................................................................................................... 63
4.1.10. Processor VCCSENSE/VSSSENSE Design Recommendations.............................. 64
4.2. Intel System Validation Debug Support ........................................................................ 64
4.2.1. ITP Support.................................................................................................... 65
4.2.1.1. Background/Justification................................................................. 65
4.2.1.2. Implementation ............................................................................... 65
4.2.2. Intel Pentium M / Intel Celeron M Processor Logic Analyzer Support
(FSB LAI) ....................................................................................................... 65
4.2.2.1. Background/Justification................................................................. 65
4.2.2.2. Implementation ............................................................................... 66
4.2.3. Intel Pentium M / Intel Celeron M Processor On-Die Logic Analyzer
Trigger (ODLAT) Support .............................................................................. 66
4.3. Onboard Debug Port Routing Guidelines ..................................................................... 66
4.3.1. ITP Signal Routing Guidelines....................................................................... 66
4.3.1.1. ITP Signal Routing Example........................................................... 69
4.3.1.2. ITP_CLK Routing to ITP700FLEX Connector ................................ 70
4.3.1.3. ITP700FLEX Design Guidelines for Production Systems .............. 72
4.3.2. Recommended ITP Interposer Debug Port Implementation ......................... 72
4.3.2.1. ITP_CLK Routing to ITP Interposer................................................ 72
4.3.2.2. ITP Interposer Design Guidelines for Production Systems ............ 73
4.3.3. Logic Analyzer Interface (LAI) ....................................................................... 74
4.3.3.1. Mechanical Considerations ............................................................ 74
4.3.3.2. Electrical Considerations ................................................................ 74
5. Intel®Mobile Voltage Positioning IV General Description.......................................................... 75
6. System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration ..................... 76
6.1. Length Matching and Length Formulas......................................................................... 77
6.2. Package Length Compensation .................................................................................... 78
6.3. Topologies and Routing Guidelines .............................................................................. 78
6.3.1. Clock Signals – SCK[5:0], SCK#[5:0] ............................................................ 78
6.3.2. Clock Topology Diagram ............................................................................... 78
6.3.3. Memory Clock Routing Guidelines ................................................................ 79
6.3.3.1. Clock Length Matching Requirements ........................................... 80
6.3.3.2. Clock Reference Lengths ............................................................... 81
6.3.3.3. Clock Package Length Table ......................................................... 82
6.3.3.4. Clock Routing Example .................................................................. 82
6.3.4. Data Signals – SDQ[71:0], SDM[8:0], SDQS[8:0] ......................................... 83
6.3.4.1. Data Bus Topology ......................................................................... 84
6.3.4.2. SDQS to Clock Length Matching Requirements ............................ 85
6.3.4.3. Data to Strobe Length Matching Requirements ............................. 87
6.3.4.4. SDQ to SDQS Mapping.................................................................. 88
6.3.4.5. SDQ/SDQS Signal Package Lengths............................................. 89
6.3.4.6. Memory Data Routing Example...................................................... 91
6.3.5. Control Signals – SCKE[3:0], SCS#[3:0] ....................................................... 91
6.3.5.1. Control Signal Topology ................................................................. 92

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6.3.5.2. Control Signal Routing Guidelines..................................................93
6.3.5.3. Control to Clock Length Matching Requirements ...........................94
6.3.5.4. Memory Control Routing Example ..................................................96
6.3.5.5. Control Group Package Length Table ............................................97
6.3.6. Command Signals – SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#.......97
6.3.6.1. Command Topology 1.....................................................................97
6.3.6.2. Command Topology 1 Routing Guidelines .....................................98
6.3.6.3. Command Topology 1 Length Matching Requirements .................99
6.3.6.4. Command Topology 2...................................................................101
6.3.6.5. Command Topology 2 Routing Guidelines ...................................102
6.3.6.6. Command Topology 2 Length Matching Requirements ...............103
6.3.6.7. Command Topology 2 Routing Example ......................................105
6.3.6.8. Command Topology 3...................................................................106
6.3.6.9. Command Topology 3 Routing Guidelines ...................................107
6.3.6.10. Command Topology 3 Length Matching Requirements ...............108
6.3.6.11. Command Group Package Length Table .....................................110
6.3.7. CPC Signals – SMA[5,4,2,1], SMAB[5,4,2,1]...............................................111
6.3.7.1. CPC Signal Topology....................................................................112
6.3.7.2. CPC Signal Routing Guidelines ....................................................112
6.3.7.3. CPC to Clock Length Matching Requirements .............................113
6.3.7.4. CPC Group Package Length Table ..............................................114
6.3.8. Feedback – RCVENOUT#, RCVENIN#.......................................................115
6.4. Routing Updates for “High-Density” Memory Device Support.....................................115
6.5. ECC Disable Guidelines ..............................................................................................115
6.5.1. GMCH ECC Functionality Disable ...............................................................115
6.5.2. DDR Memory ECC Functionality Disable ....................................................116
6.6. System Memory Compensation...................................................................................116
6.7. SMVREF Generation ...................................................................................................116
6.8. DDR Power Delivery....................................................................................................116
6.9. External Thermal Sensor Based Throttling (ETS#) .....................................................116
6.9.1. ETS# Usage Model ......................................................................................117
6.9.2. ETS# Design Guidelines ..............................................................................117
6.9.3. Thermal Sensor Routing and Placement Guidelines...................................117
7. System Memory Design Guidelines (DDR-SDRAM) for Memory Down Configuration ...........120
7.1. Length Matching and Length Formulas .......................................................................122
7.2. Package Length Compensation ..................................................................................122
7.3. Topologies and Routing Guidelines.............................................................................123
7.3.1. Clock Signals – SCK[4,3,1,0], SCK#[4,3,1,0] ..............................................123
7.3.2. Clock Topology Diagram..............................................................................123
7.3.3. DDR Clock Routing Guidelines....................................................................125
7.3.3.1. Clock Length Matching Requirements..........................................126
7.3.3.2. Clock Reference Lengths..............................................................127
7.3.3.3. Clock Package Length Table ........................................................129
7.3.4. Data Signals – SDQ[63:0], SDM[7:0], SDQS[7:0]........................................129
7.3.4.1. Data Bus Topology........................................................................131
7.3.4.2. SDQS to Clock Length Matching Requirements...........................133
7.3.4.3. Data to Strobe Length Matching Requirements............................134
7.3.4.4. SDQ to SDQS Mapping ................................................................135
7.3.4.5. SDQ/SDQS Signal Package Lengths ...........................................137
7.3.5. Control Signals – SCKE[3:0], SCS#[3:0] .....................................................138
7.3.5.1. Control Signal Topology................................................................140
7.3.5.2. Control Signal Routing Guidelines................................................142

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7.3.5.3. Control to Clock Length Matching Requirements......................... 143
7.3.5.4. Control Group Package Length Table.......................................... 144
7.3.6. Command Signals – SMAA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#.. 145
7.3.6.1. Command Topology ..................................................................... 145
7.3.6.2. Command Topology Routing Guidelines...................................... 148
7.3.6.3. Command Topology Length Matching Requirements.................. 149
7.3.6.4. Command Group Package Length Table..................................... 151
7.3.7. CPC Signals – SMA[5,4,2,1], SMAB[5,4,2,1] .............................................. 152
7.3.7.1. CPC Signal Topology ................................................................... 153
7.3.7.2. CPC Signal Routing Guidelines ................................................... 155
7.3.7.3. CPC to Clock Length Matching Requirements............................. 156
7.3.7.4. CPC Group Package Length Table.............................................. 157
8. Integrated Graphics Display Port ............................................................................................. 159
8.1. Analog RGB/CRT Guidelines...................................................................................... 159
8.1.1. RAMDAC/Display Interface ......................................................................... 159
8.1.2. Reference Resistor (REFSET) .................................................................... 159
8.1.3. RAMDAC Board Design Guidelines ............................................................ 160
8.1.4. RAMDAC Routing Guidelines...................................................................... 161
8.1.5. DAC Power Requirements .......................................................................... 163
8.1.6. HSYNC and VSYNC Design Considerations .............................................. 164
8.1.7. DDC and I2C Design Considerations.......................................................... 164
8.2. LVDS Transmitter Interface......................................................................................... 164
8.2.1. LVDS Length Matching Constraints ............................................................ 165
8.2.2. LVDS Package Length Compensation........................................................ 165
8.2.3. LVDS Routing Guidelines............................................................................ 165
8.3. Digital Video Out Port.................................................................................................. 168
8.3.1. Length Matching Requirements................................................................... 168
8.3.2. Package Length Compensation .................................................................. 169
8.3.3. DVOB and DVOC Routing Guidelines ........................................................ 169
8.3.4. DVOB and DVOC Assumptions, Definitions, and Specifications ................ 171
8.3.5. DVOB and DVOC Simulation Method ......................................................... 172
8.4. DVOB and DVOC port Flexible (Modular) Design ...................................................... 173
8.4.1. DVOB and DVOC Module Design ............................................................... 173
8.4.1.1. Generic Connector Model............................................................. 173
8.5. DVO GMBUS and DDC Interface Considerations ...................................................... 174
8.5.1. Leaving the GMCH DVOB or DVOC Port Unconnected ............................. 175
8.5.2. Miscellaneous Input Signals and Voltage Reference.................................. 175
8.5.3. PM_SUS_CLK/AGP_PIPE# Design Consideration .................................... 175
9. AGP Port Design Guidelines.................................................................................................... 177
9.1. AGP Interface .............................................................................................................. 177
9.1.1. AGP Interface Signal Groups ...................................................................... 177
9.2. AGP Routing Guidelines ............................................................................................. 179
9.2.1. 1x Timing Domain Routing Guidelines ........................................................ 179
9.2.1.1. Trace Length Requirements for AGP 1X...................................... 179
9.2.1.2. Trace Spacing Requirements....................................................... 179
9.2.1.3. Trace Length Mismatch ................................................................ 179
9.2.2. 2x/4x Timing Domain Routing Guidelines ................................................... 180
9.2.2.1. Trace Length Requirements for AGP 2X/4X ................................ 180
9.2.2.2. Trace Spacing Requirements....................................................... 180
9.2.2.3. Trace Length Mismatch Requirements ........................................ 181
9.2.3. AGP Clock Skew ......................................................................................... 182
9.2.4. AGP Signal Noise Decoupling Guidelines................................................... 182

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9.2.5. AGP Interface Package Lengths..................................................................183
9.2.6. AGP Routing Ground Reference .................................................................184
9.2.7. Pull-ups ........................................................................................................184
9.2.8. AGP VDDQ and VCC...................................................................................186
9.2.9. VREF Generation for AGP 2.0 (2X and 4X).................................................186
9.2.9.1. 1.5-V AGP Interface (2X/4X).........................................................186
9.2.10. AGP Compensation .....................................................................................186
9.2.11. PM_SUS_CLK/AGP_PIPE# Design Consideration.....................................186
10. Hub Interface ............................................................................................................................187
10.1. Hub Interface Compensation .......................................................................................187
10.2. Hub Interface Data HL[10:0] and Strobe Signals ........................................................188
10.2.1. HL[10:0] and Strobe Signals Internal Layer Routing ...................................188
10.2.2. Terminating HL[11].......................................................................................190
10.3. Hub VREF/VSWING Generation/Distribution ..............................................................190
10.3.1. Single Generation Voltage Reference Divider Circuit..................................190
10.3.2. Locally Generated Voltage Reference Divider Circuit .................................191
10.3.3. Single GMCH and ICH4-M Voltage Generation / Separate Divider
Circuit for VSWING/VREF............................................................................192
10.3.4. Separate GMCH and ICH4-M Voltage Generation / Separate Divider
Circuits for VREF and VSWING...................................................................193
10.4. Hub Interface Decoupling Guidelines ..........................................................................193
11. I/O Subsystem ..........................................................................................................................195
11.1. IDE Interface ................................................................................................................195
11.1.1. Cabling .........................................................................................................195
11.1.2. Primary IDE Connector Requirements.........................................................196
11.1.3. Secondary IDE Connector Requirements....................................................197
11.1.4. Mobile IDE Swap Bay Support.....................................................................198
11.1.4.1. ICH4-M IDE Interface Tri-State Feature .......................................198
11.1.4.2. S5/G3 to S0 Boot Up Procedures for IDE Swap Bay ...................199
11.1.4.3. Power Down Procedures for Mobile Swap Bay ............................199
11.1.4.4. Power Up Procedures After Device “Hot” Swap Completed ........199
11.2. PCI 200
11.3. AC’97 200
11.3.1. AC’97 Routing ..............................................................................................204
11.3.2. Motherboard Implementation .......................................................................205
11.3.2.1. Valid Codec Configurations ..........................................................205
11.3.3. SPKR Pin Configuration...............................................................................205
11.4. USB 2.0 Guidelines and Recommendations ...............................................................206
11.4.1. Layout Guidelines ........................................................................................206
11.4.1.1. General Routing and Placement...................................................206
11.4.1.2. USB 2.0 Trace Separation ............................................................207
11.4.1.3. USBRBIAS Connection.................................................................207
11.4.1.4. USB 2.0 Termination.....................................................................208
11.4.1.5. USB 2.0 Trace Length Pair Matching ...........................................208
11.4.1.6. USB 2.0 Trace Length Guidelines ................................................208
11.4.2. Plane Splits, Voids, and Cut-Outs (Anti-Etch)..............................................208
11.4.2.1. VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)......................209
11.4.2.2. GND Plane Splits, Voids, and Cut-Outs (Anti-Etch) .....................209
11.4.3. USB Power Line Layout Topology ...............................................................209
11.4.4. EMI Considerations......................................................................................210
11.4.4.1. Common Mode Chokes ................................................................210
11.4.5. ESD ..............................................................................................................211

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11.4.6. USB Selective Suspend............................................................................... 211
11.5. I/O APIC (I/O Advanced Programmable Interrupt Controller) ..................................... 212
11.6. SMBus 2.0/SMLink Interface....................................................................................... 212
11.6.1. SMBus Architecture and Design Considerations ........................................ 214
11.6.1.1. SMBus Design Considerations..................................................... 214
11.6.1.2. General Design Issues/Notes....................................................... 214
11.6.1.3. High Power/Low Power Mixed Architecture ................................. 214
11.6.1.4. Calculating the Physical Segment Pull-Up Resistor..................... 215
11.7. FWH 216
11.7.1. FWH Decoupling.......................................................................................... 216
11.7.2. In Circuit FWH Programming....................................................................... 216
11.7.3. FWH INIT# Voltage Compatibility................................................................ 216
11.7.4. FWH VPP Design Guidelines........................................................................ 217
11.7.5. FWH INIT# Assertion/Deassertion Timings................................................. 217
11.8. RTC 218
11.8.1. RTC Crystal ................................................................................................. 219
11.8.2. External Capacitors ..................................................................................... 220
11.8.3. RTC Layout Considerations ........................................................................ 221
11.8.4. RTC External Battery Connections.............................................................. 221
11.8.5. RTC External RTCRST# Circuit .................................................................. 222
11.8.6. VBIAS DC Voltage and Noise Measurements ............................................... 223
11.8.7. SUSCLK....................................................................................................... 223
11.8.8. RTC-Well Input Strap Requirements ........................................................... 223
11.9. Internal LAN Layout Guidelines .................................................................................. 223
11.9.1. Footprint Compatibility ................................................................................. 224
11.9.2. Intel®82801DBM ICH4-M – LAN Connect Interface Guidelines................. 225
11.9.2.1. Bus Topologies............................................................................. 226
11.9.2.1.1. LAN On Motherboard Point-To-Point Interconnect .... 226
11.9.2.2. Signal Routing and Layout ........................................................... 226
11.9.2.3. Crosstalk Consideration ............................................................... 227
11.9.2.4. Impedances .................................................................................. 227
11.9.2.5. Line Termination........................................................................... 227
11.9.2.6. Terminating Unused LAN Connect Interface Signals................... 227
11.9.3. Intel 82562ET / Intel 82562 EM Guidelines................................................. 227
11.9.3.1. Guidelines for Intel 82562ET / Intel 82562EM Component
Placement 228
11.9.3.2. Crystals and Oscillators................................................................ 228
11.9.3.3. Intel 82562ET / Intel 82562EM Termination Resistors................. 228
11.9.3.4. Critical Dimensions....................................................................... 229
11.9.3.4.1. Distance from Magnetics Module to
RJ-45 (Distance A) ..................................................... 229
11.9.3.4.2. Distance from Intel 82562ET / 82562ET to
Magnetics Module (Distance B) ................................. 230
11.9.3.5. Reducing Circuit Inductance ........................................................ 230
11.9.3.5.1. Terminating Unused Connections.............................. 230
11.9.3.5.2. Termination Plane Capacitance ................................. 230
11.9.4. Intel 82562ET/EM Disable Guidelines......................................................... 231
11.9.5. Design and Layout Consideration for Intel 82540EP / 82551QM ............... 232
11.9.6. General Intel 82562ET / 82562EM / 82551QM / 82540EP Differential Pair
Trace Routing Considerations ..................................................................... 232
11.9.6.1.1. Trace Geometry and Length ...................................... 234
11.9.6.1.2. Signal Isolation ........................................................... 234

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11.9.6.1.3. Magnetics Module General Power and Ground Plane
Considerations ............................................................234
11.9.6.2. Common Physical Layout Issues..................................................236
11.10. Power Management Interface......................................................................................237
11.10.1. SYS_RESET# Usage Model........................................................................237
11.10.2. PWRBTN# Usage Model .............................................................................237
11.10.3. Power Well Isolation Control Strap Requirements.......................................237
11.11. CPU I/O Signal Considerations ...................................................................................238
12. Platform Clock Routing Guidelines...........................................................................................239
12.1. System Clock Groups ..................................................................................................239
12.2. Clock Group Topologies and Routing Constraints ......................................................240
12.2.1. Host Clock Group.........................................................................................241
12.2.1.1. Host Clock Group General Routing Guidelines ............................243
12.2.1.2. Clock to Clock Length Matching and Compensation....................243
12.2.1.3. Host Clock to CLK66 Routing Recommendations........................243
12.2.1.4. EMI Constraints.............................................................................244
12.2.2. CLK66 Clock Group .....................................................................................245
12.2.3. CLK33 Clock Group .....................................................................................247
12.2.4. PCI Clock Group ..........................................................................................248
12.2.5. CLK14 Clock Group .....................................................................................249
12.2.6. DOTCLK Clock Group..................................................................................250
12.2.7. SSCCLK Clock Group..................................................................................251
12.2.8. USBCLK Clock Group..................................................................................252
12.3. CK-408 Clock Updates for Intel Pentium M Processor and
Intel Celeron M Processor Platforms...........................................................................253
12.4. CK-408 PWRDWN# Signal Connections ....................................................................253
13. Intel 855GM/GME Chipset Based System Power Delivery Guidelines....................................255
13.1. Definitions ....................................................................................................................255
13.2. Platform Power Requirements.....................................................................................255
13.2.1. Platform Power Delivery Architectural Block Diagram.................................256
13.3. Voltage Supply.............................................................................................................257
13.3.1. Power Management States..........................................................................257
13.3.2. Power Supply Rail Descriptions...................................................................257
13.4. 855GM/GME Chipset Based System Power-Up Sequence........................................258
13.4.1. Processor Power Sequence Requirement...................................................258
13.4.2. GMCH Power Sequencing Requirements ...................................................258
13.4.3. ICH4-M Power Sequencing Requirements..................................................259
13.4.3.1. 3.3/1.5 V Power Sequencing ........................................................261
13.4.3.2. V5REF Sequencing..........................................................................261
13.4.3.3. V5REFSUS Design Guidelines...........................................................262
13.4.4. DDR Memory Power Sequencing Requirements ........................................263
13.5. Intel 855GM/GME Chipset Based System Power Delivery Guidelines.......................264
13.5.1. 855GM/GME Chipset GMCH Decoupling Guidelines..................................265
13.5.1.1. GMCH VCCSM Decoupling ..........................................................266
13.5.1.2. DDR Memory Device VDD Decoupling ........................................266
13.5.1.3. DDR VTT Decoupling Placement and Layout Guidelines ............266
13.5.2. DDR Memory Power Delivery Design Guidelines........................................266
13.5.2.1. 2.5-V Power Delivery Guidelines ..................................................267
13.5.2.2. GMCH and DDR SMVREF Design Recommendations................267
13.5.2.3. DDR SMRCOMP Resistive Compensation ..................................268
13.5.2.4. DDR VTT Termination ..................................................................268

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10 Intel®855GM/855GME Chipset Platform Design Guide
13.5.2.5. DDR SMRCOMP and VTT 1.25-V Supply Disable in
S3/Suspend .................................................................................. 269
13.5.3. Other GMCH Reference Voltage and Analog Power Delivery .................... 269
13.5.3.1. GMCH GTLVREF ......................................................................... 269
13.5.3.2. GMCH AGTL+ I/O Buffer Compensation ..................................... 270
13.5.3.3. GMCH AGTL+ Reference Voltage ............................................... 271
13.5.3.4. GMCH Analog Power ................................................................... 271
13.5.4. ICH4-M Decoupling / Power Delivery Guidelines........................................ 272
13.5.4.1. ICH4-M Decoupling ...................................................................... 272
13.5.5. Hub Interface Decoupling ............................................................................ 273
13.5.6. FWH Decoupling.......................................................................................... 273
13.5.7. General LAN Decoupling............................................................................. 273
14. Intel Pro/Wireless 2100/2100A – Bluetooth Coexistence Interface Design Requirements ..... 275
14.1. PCB Interface Requirements ...................................................................................... 275
14.2. DC Power Requirements for Bluetooth ....................................................................... 276
14.3. Start Up Conditions and Logic Protection ................................................................... 276
14.4. USB Selective Suspend .............................................................................................. 277
15. Reserved, NC, and Test Signals.............................................................................................. 279
15.1. Intel Pentium M Processor and Intel Celeron M Processor RSVD Signals ................ 279
15.2. Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache
Processor RSVD Signals ............................................................................................ 279
15.3. Intel 855GM/GME Chipset GMCH RSVD Signals ...................................................... 280
16. Platform Design Checklist ........................................................................................................ 281
16.1. General Information..................................................................................................... 281
16.2. Customer Implementation of Voltage Rails................................................................. 282
16.3. Design Checklist Implementation................................................................................ 282
16.4. Intel Pentium M Processor / Intel Celeron M Processor ............................................. 284
16.4.1. Resistor Recommendations ........................................................................ 284
16.4.2. In Target Probe (ITP)................................................................................... 287
16.4.3. Decoupling Recommendations.................................................................... 287
16.4.3.1. VCCP (I/O).................................................................................... 287
16.4.3.2. VCCA (PLL) .................................................................................. 288
16.4.3.3. VCC (CORE) ................................................................................ 288
16.5. CK-408 Clock Checklist............................................................................................... 289
16.5.1. Resistor Recommendations ........................................................................ 289
16.6. Intel 855GM/855GME Checklist................................................................................. 291
16.6.1. System Memory........................................................................................... 291
16.6.1.1. GMCH System Memory Interface ................................................ 291
16.6.1.2. DDR SO-DIMM Interface.............................................................. 293
16.6.1.3. SODIMM Decoupling Recommendation ...................................... 293
16.6.2. FSB .............................................................................................................. 294
16.6.3. Hub Interface ............................................................................................... 295
16.6.4. Graphics Interfaces...................................................................................... 295
16.6.4.1. LVDS .................................................................................... 295
16.6.4.2. DVO .................................................................................... 296
16.6.4.3. DAC .................................................................................... 297
16.6.5. Miscellaneous .............................................................................................. 298
16.6.6. GMCH Decoupling Recommendations ....................................................... 299
16.7. ICH4-M Checklist ........................................................................................................ 301
16.7.1. PCI Interface and Interrupts ........................................................................ 301
16.7.2. GPIO ............................................................................................................ 302

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Intel® 855GM/855GME Chipset Platform Design Guide 11
16.7.3. AGP_BUSY# Design Requirement..............................................................303
16.7.4. (SMBus) System Management Interface .....................................................303
16.7.5. AC ’97 Interface ...........................................................................................304
16.7.6. ICH4-M Power Management Interface ........................................................305
16.7.7. FWH/LPC Interface ......................................................................................305
16.7.8. USB Interface ...............................................................................................306
16.7.9. Hub Interface................................................................................................306
16.7.10. RTC Circuitry................................................................................................308
16.7.11. LAN Interface ...............................................................................................309
16.7.12. Primary IDE Interface...................................................................................309
16.7.13. Secondary IDE Interface ..............................................................................310
16.7.14. Miscellaneous Signals..................................................................................310
16.7.15. ICH4-M Decoupling Recommendations ......................................................311
16.8. USB Power Checklist...................................................................................................311
16.8.1. Downstream Power Connection ..................................................................311
16.9. FWH Checklist .............................................................................................................312
16.9.1. Resistor Recommendations.........................................................................312
16.10. LAN / HomePNA Checklist ..........................................................................................313
16.10.1. Resistor Recommendations (for 82562ET / 82562EM) ...............................313
16.10.2. Decoupling Recommendations ....................................................................314
17. Schematics ...............................................................................................................................315

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12 Intel®855GM/855GME Chipset Platform Design Guide
Figures
Figure 1. Intel Pentium M Processor and Intel 855GM Chipset Block Diagram...................... 26
Figure 2. Intel Pentium M, Intel Pentium M Processor on 90 nm Process with 2 MB L2 Cache,
Intel Celeron M Processor and 855GME Chipset System Block Diagram .............. 30
Figure 3. Recommended Board Stack-Up Dimensions ........................................................... 34
Figure 4. Trace Spacing vs. Trace to Reference Plane Example............................................ 38
Figure 5. Three to One Trace Spacing to Trace Width Example............................................. 38
Figure 6. Common Clock Topology ......................................................................................... 40
Figure 7. Layer 6 PSB Source Synchronous Signals GND Referencing to Layer 5 ............... 42
Figure 8. Layer 3 PSB Source Synchronous Signals .............................................................. 43
Figure 9. Routing Illustration for Topology 1A ......................................................................... 50
Figure 10. Routing Illustration for Topology 1B ....................................................................... 51
Figure 11. Routing Illustration for Topology 1C ....................................................................... 52
Figure 12. Routing Illustration for Topology 2A ....................................................................... 52
Figure 13. Routing Illustration for Topology 2B ....................................................................... 53
Figure 14. Routing Illustration for Topology 2C ....................................................................... 54
Figure 15. Routing Illustration for Topology 3 .......................................................................... 54
Figure 16. Voltage Translation Circuit...................................................................................... 55
Figure 17. Processor RESET# Signal Routing Topology with NO ITP700FLEX Connector... 56
Figure 18. Processor RESET# Signal Routing Topology with ITP700FLEX Connector ......... 56
Figure 19. Processor RESET# Signal Routing Example with ITP700FLEX Debug Port ........57
Figure 20. Processor and GMCH Host Clock Layout Routing Example ................................. 58
Figure 21. Processor GTLREF Voltage Divider Network ........................................................ 59
Figure 22. Processor GTLREF Motherboard Layout............................................................... 60
Figure 23. Processor COMP[2] & COMP[0] Resistive Compensation .................................... 61
Figure 24. Processor COMP[3] & COMP[1] Resistive Compensation .................................... 61
Figure 25. Processor COMP[3:0] Resistor Layout................................................................... 62
Figure 26. Processor COMP[1:0] Resistor Alternative Primary Side Layout........................... 62
Figure 27. COMP2 & COMP0 27.4-ΩTraces.......................................................................... 63
Figure 28. VCCSENSE/VSSSENSE Routing Example ....................................................................... 64
Figure 29. ITP700FLEX Debug Port Signals ........................................................................... 67
Figure 30. ITP700FLEX Signals Layout Example ................................................................... 71
Figure 31. ITP_CLK to ITP700FLEX Connector Layout Example ........................................... 71
Figure 32. ITP_CLK to CPU ITP Interposer Layout Example.................................................. 73
Figure 33. Memory Clock Routing Topology SCK/SCK#[5:0] ................................................. 79
Figure 34. Memory Clock Trace Length Matching Diagram .................................................... 81
Figure 35. Clock Signal Routing Example ............................................................................... 83
Figure 36. Data Signal Routing Topology................................................................................ 84
Figure 37. SDQS to Clock Trace Length Matching Diagram................................................... 87
Figure 38. SDQ/SDM to SDQS Trace Length Matching Diagram ........................................... 89
Figure 39. Data Signals Group Routing Example.................................................................... 91
Figure 40. Control Signal Routing Topology............................................................................ 92
Figure 41. Control Signal to Clock Trace Length Matching Diagram ...................................... 95
Figure 42. Control Signals Group Routing Example................................................................ 96
Figure 43. Command Routing for Topology 1.......................................................................... 98
Figure 44. Topology 1 Command Signal to Clock Trace Length Matching Diagram ............ 100
Figure 45. Command Routing Topology 2.............................................................................101
Figure 46. Topology 2 Command Signal to Clock Trace Length Matching Diagram ............ 104
Figure 47. Example of Command Signal Group ....................................................................105
Figure 48. Command Routing Topology 3.............................................................................106
Figure 49. Topology 3 Command Signal to Clock Trace Length Matching Diagram ............ 109

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Intel® 855GM/855GME Chipset Platform Design Guide 13
Figure 50. Command per Clock Signal Routing Topology .................................................... 112
Figure 51. CPC Signals to Clock Length Matching Diagram ................................................ 114
Figure 52. DDR Memory Thermal Sensor Placement........................................................... 118
Figure 53. Recommended Device Order for Micro-DIMM/Memory Down Combination...... 120
Figure 54. DDR Clock Routing to Micro-DIMM .................................................................... 123
Figure 55. DDR Clock Routing to Memory Down Two Load BGA ........................................ 124
Figure 56. DDR Clock Routing to Memory Down Two Load TSOP...................................... 124
Figure 57. DDR Clock Routing to Memory Down 4 Load BGA............................................. 124
Figure 58. DDR Clock Trace Length Matching Diagram....................................................... 128
Figure 59. Data Signal Routing GMCH to 1x16 TSOP/BGA & /1x8 BGA Configuration ...... 131
Figure 60. Data Signal Routing GMCH to 2x16 BGA Configuration ..................................... 131
Figure 61. SDQS to Clock Trace Length Matching Diagram ................................................ 134
Figure 62. SDQ/SDM to SDQS Trace Length Matching Diagram ........................................ 136
Figure 63. Control Signal Routing GMCH to Micro-DIMM Pad ............................................. 140
Figure 64. Control Signal Routing GMCH to Memory Down 1x16 4 Load TSOP................. 140
Figure 65. Control Signal Routing GMCH to Memory Down 1x16/2x16 4 Load BGA .......... 141
Figure 66. Control Signal Routing GMCH to Memory Down 1x8 8 Loads BGA ................... 141
Figure 67. Control Signal to Clock Trace Length Matching Diagram.................................... 144
Figure 68. CMD Signal Routing GMCH to Micro-DIMM and Mem Down TSOP 4 Load ...... 146
Figure 69. CMD Signal Routing GMCH to Micro-DIMM and Mem Down BGA 4 Load......... 146
Figure 70. CMD Signal Routing GMCH to Micro-DIMM and Memory Down BGA 8-Load ... 147
Figure 71. Topology 1 Command Signal to Clock Trace Length Matching Diagram........... 150
Figure 72. Command Per Clock Signal Routing Topology 4 Load BGA............................... 153
Figure 73. CPC Signal Routing Topology 4 Load TSOP ...................................................... 153
Figure 74. CPC Signal Routing 8 Load BGA Topology......................................................... 154
Figure 75. CPC Signal Routing Micro-DIMM......................................................................... 154
Figure 76. CPC Signals to Clock Length Matching Diagram ................................................ 157
Figure 77. Refset Placement ................................................................................................. 160
Figure 78. GMCH DAC Routing Guidelines with Docking Connector................................... 161
Figure 79. DAC R, G, B Routing and Resistor Layout example............................................ 163
Figure 80. DVOB and DVOC Simulations Model .................................................................. 172
Figure 81. Driver-Receiver Waveforms Relationship Specification ...................................... 172
Figure 82. DVO Enabled Simulation Model........................................................................... 173
Figure 83. Generic Module Connector Parasitic Model ........................................................ 174
Figure 84. GVREF Reference Voltage .................................................................................. 176
Figure 85. AGP Layout Guidelines........................................................................................ 180
Figure 86. DPMS Circuit........................................................................................................ 186
Figure 87. Hub Interface Routing Example ........................................................................... 187
Figure 88. Single VREF/VSWING Voltage Generation Circuit for Hub Interface ................. 191
Figure 89. ICH4-M and GMCH Locally Generated Reference Voltage Divider Circuit......... 192
Figure 90. Shared GMCH & ICH4-M Reference Voltage with Separate Voltage Divider Circuit
for VSWING and VREF.......................................................................................... 192
Figure 91. Individual HIVREF and HI_VSWING Voltage Reference Divider Circuits for ICH4-M
and GMCH ............................................................................................................. 193
Figure 92. Connection Requirements for Primary IDE Connector ........................................ 196
Figure 93. Connection Requirements for Secondary IDE Connector ................................... 197
Figure 94. PCI Bus Layout Example ..................................................................................... 200
Figure 95. Intel 82801DBM ICH4-M AC’97 – Codec Connection ......................................... 201
Figure 96. Intel 82801DBM ICH4-M AC’97 – AC_BIT_CLK Topology ................................. 202
Figure 97. Intel 82801DBM AC’97 – AC_SDOUT/AC_SYNC Topology............................... 202
Figure 98. Intel 82801DBM AC’97 – AC_SDIN Topology ..................................................... 203
Figure 99. Example Speaker Circuit...................................................................................... 206
Figure 100. Recommended USB Trace Spacing .................................................................. 207

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14 Intel®855GM/855GME Chipset Platform Design Guide
Figure 101. USBRBIAS Connection ...................................................................................... 208
Figure 102. Good Downstream Power Connection ............................................................... 210
Figure 103. Common Mode Choke Schematic...................................................................... 210
Figure 104. SMBUS 2.0/SMLink Protocol..............................................................................213
Figure 105. High Power/Low Power Mixed VCC_SUSPEND/VCC_CORE Architecture ................... 214
Figure 106. FWH VPP Isolation Circuitry...............................................................................217
Figure 107. RTCX1 and SUSCLK Relationship in ICH4-M ................................................... 218
Figure 108. External Circuitry for the ICH4-M Where the Internal RTC is Not Used............. 218
Figure 109. External Circuitry for the ICH4-M RTC ............................................................... 219
Figure 110. Diode Circuit to Connect RTC External Battery ................................................. 222
Figure 111. RTCRST# External Circuit for the ICH4-M RTC ................................................ 222
Figure 112. Intel 82801DBM ICH4-M/Platform LAN Connect Section .................................. 224
Figure 113. Single Solution Interconnect...............................................................................226
Figure 114. LAN_CLK Routing Example ............................................................................... 227
Figure 115. Intel 82562ET / Intel 82562EM Termination ....................................................... 228
Figure 116. Critical Dimensions for Component Placement..................................................229
Figure 117. Termination Plane............................................................................................... 231
Figure 118. Intel 82562ET/EM Disable and Power Down Circuitry ....................................... 231
Figure 119. Trace Routing ..................................................................................................... 233
Figure 120. Ground Plane Separation ...................................................................................235
Figure 121. ICH4-M CPU I/O Signals with Processor and FWH ........................................... 238
Figure 122. Clock Distribution Diagram .................................................................................240
Figure 123. Source Shunt Termination Topology .................................................................. 241
Figure 124. BCLK to GCLKIN Timing Requirement .............................................................. 244
Figure 125. CLK66 Clock Group Topology............................................................................ 245
Figure 126. CLK33 Group Topology ...................................................................................... 247
Figure 127. PCI Clock Group Topology.................................................................................248
Figure 128. CLK14 Clock Group Topology............................................................................ 249
Figure 129. DOTCLK Clock Topology ...................................................................................250
Figure 130. SSCCLK Clock Topology.................................................................................... 251
Figure 131. USBCLK Clock Topology.................................................................................... 252
Figure 132. Platform Power Delivery Map ............................................................................. 256
Figure 133. GMCH Power-Up Sequence .............................................................................. 259
Figure 134. ICH4-M Power-Up Sequence ............................................................................. 260
Figure 135. Example V5REF / V5REFSUS Sequencing Circuitry .................................................. 262
Figure 136. V5REFSUS With +V5ALWAYS Connection Option ........................................... 262
Figure 137. V5REFSUS With +V3ALWAYS and +V5S or +V5 Connection Option .............. 263
Figure 138. Example for Minimizing Loop Inductance...........................................................264
Figure 139. DDR Power Delivery Block Diagram ..................................................................267
Figure 140. GMCH SMRCOMP Resistive Compensation.....................................................268
Figure 141. GMCH System Memory Reference Voltage Generation Circuit ........................ 268
Figure 142. GMCH HDVREF[2:0] Reference Voltage Generation Circuit.............................269
Figure 143. GMCH HAVREF Reference Voltage Generation Circuit.................................... 270
Figure 144. GMCH HCCVREF Reference Voltage Generation Circuit .................................270
Figure 145. GMCH HXRCOMP and HYRCOMP Resistive Compensation........................... 270
Figure 146. GMCH HXSWING and HYSWING Reference Voltage Generation Circuit........271
Figure 147. Example Analog Supply Filter............................................................................. 271
Figure 148. Recommended Topology for Coexistence Traces ............................................. 276
Figure 149. Routing Illustration for INIT# ............................................................................... 286
Figure 150. Voltage Translation Circuit for PROCHOT# .......................................................286
Figure 151. Clock Power-down Implementation .................................................................... 290
Figure 152. Reference Voltage Level for SMVREF ............................................................... 293
Figure 153. GMCH HXSWING & HYSWING Reference Voltage Generation Circuit............294

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Intel® 855GM/855GME Chipset Platform Design Guide 15
Figure 154. DPMS Clock Implementation ............................................................................. 297
Figure 155. Single or Locally Generated GMCH and ICH4-M HIVREF/HI_VSWING Circuit 307
Figure 156. Single Generated GMCH and ICH4-M VSWING/VREF Reference Voltage/ Local
Voltage Divider Circuit for VSWING/VREF............................................................ 307
Figure 157. External Circuitry for the RTC ............................................................................ 308
Figure 158. Good Downstream Power Connection............................................................... 312
Figure 159. LAN_RST# Design Recommendation ............................................................... 313

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16 Intel®855GM/855GME Chipset Platform Design Guide
Tables
Table 1. Conventions and Terminology ................................................................................... 21
Table 2. Processor System Bus Common Clock Signal Internal Layer Routing Guidelines... 39
Table 3. Processor and GMCH PSB Common Clock Signal Package Lengths and Minimum
Board Trace Lengths................................................................................................ 40
Table 4. Processor PSB Data Source Synchronous Signal Trace Length Mismatch Mapping44
Table 5. Processor System Bus Source Synchronous Data Signal Routing Guidelines ........45
Table 6. Processor PSB Address Source Synchronous Signal Trace Length Mismatch
Mapping.................................................................................................................... 45
Table 7. Processor PSB Source Synchronous Address Signal Routing Guidelines ............... 46
Table 8. Intel Pentium M / Intel Celeron M Processor and GMCH Source Synchronous FSB
Signal Package Lengths........................................................................................... 47
Table 9. Asynchronous AGTL+ Nets ....................................................................................... 49
Table 10. Layout Recommendations for Topology 1A............................................................. 50
Table 11. Layout Recommendations for Topology 1B............................................................. 51
Table 12. Layout Recommendations for Topology 1C ............................................................ 52
Table 13. Layout Recommendations for Topology 2A............................................................. 53
Table 14. Layout Recommendations for Topology 2B............................................................. 53
Table 15. Layout Recommendations for Topology 2C ............................................................ 54
Table 16. Layout Recommendations for Topology 3 ............................................................... 55
Table 17. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector ........ 57
Table 18. ITP Signal Default Strapping When ITP Debug Port Not Used ............................... 64
Table 19. Recommended ITP700FLEX Signal Terminations .................................................. 69
Table 20. GMCH Chipset Memory Signal Groups................................................................... 76
Table 21. Intel 855GM Chipset GMCH DDR 200/266 Length Matching Formulas ................. 77
Table 22. Intel 855GME Chipset GMCH DDR 200/266/333 Length Matching Formulas........ 77
Table 23. Clock Signal Mapping .............................................................................................. 78
Table 24. Clock Signal Group Routing Guidelines .................................................................. 79
Table 25. Memory Clock Package Lengths ............................................................................. 82
Table 26. Memory Data Signal Group Routing Guidelines...................................................... 85
Table 27. SDQ/SDM to SDQS Mapping .................................................................................. 88
Table 28. Memory SDQ/SDM/SDQS Package Lengths .......................................................... 89
Table 29. Control Signal to SO-DIMM Mapping ...................................................................... 92
Table 30. Control Signal Routing Guidelines........................................................................... 93
Table 31. Control Group Package Lengths ............................................................................. 97
Table 32. Command Topology 1 Routing Guidelines .............................................................. 98
Table 33. Command Topology 2 Routing Guidelines ............................................................ 102
Table 34. Command Topology 3 Routing Guidelines ............................................................ 107
Table 35. Command Group Package Lengths ...................................................................... 110
Table 36. CPC Signal to SO-DIMM Mapping ........................................................................ 111
Table 37. CPC Signal Routing Guidelines.............................................................................112
Table 38. CPC Group Package Lengths ............................................................................... 114
Table 39. Supported Memory Configurations - Micro-DIMM .................................................120
Table 40. Supported Memory Configurations - Memory Down ............................................. 121
Table 41. Montara-GM GMCH Chipset DDR Signal Groups................................................. 121
Table 42. Length Matching Formulas .................................................................................... 122
Table 43. Clock Signal Mapping ............................................................................................ 123
Table 44. Clock Signal Group Routing Guidelines ................................................................ 125
Table 45. DDR Clock Package Lengths ................................................................................129

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Intel® 855GM/855GME Chipset Platform Design Guide 17
Table 46. Data Signal Group Routing Guidelines ................................................................. 132
Table 47. SDQ/SDM to SDQS Mapping................................................................................ 135
Table 48. DDR SDQ/SDM/SDQS Package Lengths............................................................. 137
Table 49. Control Signal to Micro-DIMM/Memory Down Mapping........................................ 139
Table 50. Control Signal Routing Guidelines ........................................................................ 142
Table 51. Control Group Package Lengths........................................................................... 144
Table 52. Command Topology 1 Routing Guidelines ........................................................... 148
Table 53. Command Group Package Lengths...................................................................... 151
Table 54. CPC Signal to SO-DIMM Micro-Dimm and/or Memory Down Mapping................ 152
Table 55. CPC Signal Routing Guidelines ............................................................................ 155
Table 56. CPC Group Package Lengths ............................................................................... 157
Table 57. Recommended GMCH DAC Components............................................................ 162
Table 58. Signal Group and Signal Pair Names ................................................................... 165
Table 59. LVDS Signal Group Routing Guidelines ............................................................... 166
Table 60. LVDS Package Lengths ........................................................................................ 167
Table 61. DVO Interface Signal Groups................................................................................ 168
Table 62. DVO Interface Trace Length Mismatch Requirements ......................................... 169
Table 63. DVOB and DVOC Routing Guideline Summary.................................................... 170
Table 64. DVO Interface Package Lengths........................................................................... 171
Table 65. Allowable Interconnect Skew Calculation ............................................................. 172
Table 66. DVO Enabled Routing Guideline Summary .......................................................... 173
Table 67. GMBUS Pair Mapping and Options....................................................................... 174
Table 68. AGP 2.0 Signal Groups ......................................................................................... 178
Table 69. AGP 2.0 Data/Strobe Associations ....................................................................... 178
Table 70. Layout Routing Guidelines for AGP 1X Signals .................................................... 179
Table 71. Layout Routing Guidelines for AGP 2X/4X Signals............................................... 181
Table 72. AGP 2.0 Data Lengths Relative to Strobe Length................................................. 181
Table 73. AGP 2.0 Routing Guideline Summary................................................................... 182
Table 74. AGP Interface Package Length............................................................................. 183
Table 75. AGP Pull-Up/Pull-Down Requirements and Straps .............................................. 185
Table 76. AGP 2.0 Pull-up Resistor Values .......................................................................... 185
Table 77. Hub Interface RCOMP Resistor Values ................................................................ 187
Table 78. Hub Interface Signals Internal Layer Routing Summary....................................... 188
Table 79. Hub Interface Package Lengths for ICH4-M ......................................................... 189
Table 80. Hub Interface Package Lengths for GMCH........................................................... 189
Table 81. Hub Interface VREF/VSWING Reference Voltage Specifications ........................ 190
Table 82. Recommended Resistor Values for Single VREF/VSWING Divider Circuit ......... 191
Table 83. Recommended Resistor Values for Separate HIVREF and HI_VSWING Divider
Circuits ................................................................................................................... 192
Table 84. Recommended Resistor Values for HIVREF and HI_VSWING Divider Circuits for
ICH4-M................................................................................................................... 193
Table 85. AC’97 AC_BIT_CLK Routing Summary ................................................................ 202
Table 86. AC’97 AC_SDOUT/AC_SYNC Routing Summary ................................................ 203
Table 87. AC’97 AC_SDIN Routing Summary ...................................................................... 203
Table 88. Supported Codec Configurations .......................................................................... 205
Table 89. USBRBIAS/USBRBIAS# Routing Summary ......................................................... 208
Table 90. USB 2.0 Trace Length Guidelines (With Common-mode Choke) ........................ 208
Table 91. Bus Capacitance Reference Chart........................................................................ 215
Table 92. Bus Capacitance/Pull-Up Resistor Relationship ................................................... 215
Table 93. RTC Routing Summary ......................................................................................... 219
Table 94. LAN Component Connections/Features ............................................................... 224
Table 95. LAN Design Guide Section Reference.................................................................. 225
Table 96. LAN LOM Routing Summary................................................................................. 226

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18 Intel®855GM/855GME Chipset Platform Design Guide
Table 97. Intel 82562ET/EM Control Signals......................................................................... 232
Table 98. Individual Clock Breakdown...................................................................................239
Table 99. Host Clock Group Routing Constraints.................................................................. 242
Table 100. Clock Package Length ......................................................................................... 243
Table 101. CLK66 Clock Group Routing Constraints ............................................................ 246
Table 102. CLK33 Clock Group Routing Constraints ............................................................ 247
Table 103. PCICLK Clock Group Routing Constraints .......................................................... 248
Table 104. CLK14 Clock Group Routing Constraints ............................................................ 249
Table 105. DOTCLK Clock Routing Constraints.................................................................... 250
Table 106. SSCCLK Clock Routing Constraints.................................................................... 251
Table 107. USBCLK Clock Routing Constraints.................................................................... 252
Table 108. Power Delivery Definitions ................................................................................... 255
Table 109. Power Management States on Intel Reference Board ........................................ 257
Table 110. Power Supply Rail Descriptions on Intel Reference Board ................................. 257
Table 111. Timing Sequence Parameters ICH4-M................................................................261
Table 112. DDR Power-Up Initialization Sequence ............................................................... 263
Table 113. GMCH Decoupling Recommendations................................................................ 265
Table 114. Analog Supply Filter Requirements ..................................................................... 272
Table 115. ICH4-M Decoupling Requirements ...................................................................... 273
Table 116. Processor RSVD and TEST Signal Pin-Map Locations ...................................... 279
Table 117. Intel 855GM/GME Chipset GMCH RSVD and NC Signal Pin-Map Locations ....280

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Intel® 855GM/855GME Chipset Platform Design Guide 19
Revision History
Revision
Number
Description Revision Date
001 Initial Release March 2003
002 Updates Include:
• Added 855GME design guidelines
September 2003
003 Updates Include:
• Added Intel Celeron M processor support
January 2004
004 Updates include:
• Added section 7 Memory Down/Micro-DIMM design guidelines
• Added section 9 AGP Port Design guidelines
• Added support for Intel®Pentium®M on 90 nm Process with 2 MB L2
Cache
May 2004

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20 Intel®855GM/855GME Chipset Platform Design Guide
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