Intel 8XC196NT User manual

8XC196NT
Microcontroller
User’s Manual

8XC196NT
Microcontroller
User’s Manual
June 1995 Order Number 272317-003

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Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including
infringement of any patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions
of Sale for such products.
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errorswhich may appear
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Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
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© INTEL CORPORATION, 1996

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CONTENTS
CHAPTER 1
GUIDE TO THIS MANUAL
1.1 MANUAL CONTENTS................................................................................................... 1-1
1.2 NOTATIONAL CONVENTIONS AND TERMINOLOGY ................................................ 1-3
1.3 RELATED DOCUMENTS.............................................................................................. 1-5
1.4 ELECTRONIC SUPPORT SYSTEMS........................................................................... 1-8
1.4.1 FaxBack Service .......................................................................................................1-8
1.4.2 Bulletin Board System (BBS) ....................................................................................1-9
1.4.2.1 How to Find MCS®96 Microcontroller Files on the BBS ......................................1-9
1.4.2.2 How to Find
Ap BUILDER Software and Hypertext Documents on the BBS ......1-10
1.4.3 CompuServe Forums ..............................................................................................1-10
1.4.4 World Wide Web .....................................................................................................1-10
1.5 TECHNICAL SUPPORT.............................................................................................. 1-11
1.6 PRODUCT LITERATURE............................................................................................ 1-11
1.7 TRAINING CLASSES.................................................................................................. 1-11
CHAPTER 2
ARCHITECTURAL OVERVIEW
2.1 TYPICAL APPLICATIONS............................................................................................. 2-1
2.2 DEVICE FEATURES ..................................................................................................... 2-1
2.3 BLOCK DIAGRAM......................................................................................................... 2-1
2.3.1 CPU Control ..............................................................................................................2-3
2.3.2 Register File ..............................................................................................................2-3
2.3.3 Register Arithmetic-logic Unit (RALU) .......................................................................2-3
2.3.3.1 Code Execution ....................................................................................................2-4
2.3.3.2 Instruction Format ................................................................................................2-4
2.3.4 Memory Controller ....................................................................................................2-5
2.3.5 Interrupt Service ........................................................................................................2-5
2.4 INTERNAL TIMING........................................................................................................ 2-6
2.5 INTERNAL PERIPHERALS........................................................................................... 2-7
2.5.1 I/O Ports ....................................................................................................................2-8
2.5.2 Serial I/O (SIO) Port ..................................................................................................2-8
2.5.3 Synchronous Serial I/O (SSIO) Port ..........................................................................2-8
2.5.4 Slave Port .................................................................................................................2-9
2.5.5 Event Processor Array (EPA) and Timer/Counters ...................................................2-9
2.5.6 Analog-to-digital Converter .....................................................................................2-10
2.5.7 Watchdog Timer ......................................................................................................2-10
2.6 SPECIAL OPERATING MODES ................................................................................. 2-10
2.6.1 Reducing Power Consumption ...............................................................................2-10
2.6.2 Testing the Printed Circuit Board ............................................................................2-11

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2.6.3 Programming the Nonvolatile Memory ....................................................................2-11
CHAPTER 3
PROGRAMMING CONSIDERATIONS
3.1 OVERVIEW OF THE INSTRUCTION SET.................................................................... 3-1
3.1.1 BIT Operands ............................................................................................................3-2
3.1.2 BYTE Operands ........................................................................................................3-2
3.1.3 SHORT-INTEGER Operands ....................................................................................3-2
3.1.4 WORD Operands ......................................................................................................3-3
3.1.5 INTEGER Operands .................................................................................................3-3
3.1.6 DOUBLE-WORD Operands ......................................................................................3-3
3.1.7 LONG-INTEGER Operands ......................................................................................3-4
3.1.8 QUAD-WORD Operands ..........................................................................................3-4
3.1.9 Converting Operands ................................................................................................3-4
3.1.10 Conditional Jumps ....................................................................................................3-4
3.1.11 Floating Point Operations .........................................................................................3-5
3.1.12 Extended Instructions ...............................................................................................3-5
3.2 ADDRESSING MODES................................................................................................. 3-6
3.2.1 Direct Addressing ......................................................................................................3-7
3.2.2 Immediate Addressing ..............................................................................................3-7
3.2.3 Indirect Addressing ...................................................................................................3-7
3.2.3.1 Extended Indirect Addressing ..............................................................................3-8
3.2.3.2 Indirect Addressing with Autoincrement ...............................................................3-8
3.2.3.3 Extended Indirect Addressing with Autoincrement ...............................................3-8
3.2.3.4 Indirect Addressing with the Stack Pointer ...........................................................3-9
3.2.4 Indexed Addressing ..................................................................................................3-9
3.2.4.1 Short-indexed Addressing ....................................................................................3-9
3.2.4.2 Long-indexed Addressing ....................................................................................3-9
3.2.4.3 Extended Indexed Addressing ...........................................................................3-10
3.2.4.4 Zero-indexed Addressing ...................................................................................3-10
3.2.4.5 Extended Zero-indexed Addressing ...................................................................3-10
3.3 ASSEMBLY LANGUAGE ADDRESSING MODE SELECTIONS................................ 3-11
3.3.1 Direct Addressing ....................................................................................................3-11
3.3.2 Indexed Addressing ................................................................................................3-11
3.3.3 Extended Addressing ..............................................................................................3-11
3.4 DESIGN CONSIDERATIONS FOR 1-MBYTE DEVICES............................................ 3-11
3.5 SOFTWARE STANDARDS AND CONVENTIONS ..................................................... 3-11
3.5.1 Using Registers .......................................................................................................3-12
3.5.2 Addressing 32-bit Operands ...................................................................................3-12
3.5.3 Addressing 64-bit Operands ...................................................................................3-12
3.5.4 Linking Subroutines ................................................................................................3-13
3.6 SOFTWARE PROTECTION FEATURES AND GUIDELINES .................................... 3-14

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CONTENTS
CHAPTER 4
MEMORY PARTITIONS
4.1 MEMORY MAP OVERVIEW.......................................................................................... 4-1
4.2 MEMORY PARTITIONS................................................................................................ 4-3
4.2.1 External Memory .......................................................................................................4-5
4.2.2 Program and Special-purpose Memory ....................................................................4-5
4.2.2.1 Program Memory in Page FFH ............................................................................4-5
4.2.2.2 Special-purpose Memory .....................................................................................4-6
4.2.2.3 Reserved Memory Locations ...............................................................................4-7
4.2.2.4 Interrupt and PTS Vectors ....................................................................................4-7
4.2.2.5 Security Key .........................................................................................................4-7
4.2.2.6 Chip Configuration Bytes .....................................................................................4-8
4.2.3 Special-function Registers (SFRs) ............................................................................4-8
4.2.3.1 Memory-mapped SFRs ........................................................................................4-8
4.2.3.2 Peripheral SFRs ...................................................................................................4-9
4.2.4 Internal RAM (Code RAM) ......................................................................................4-11
4.2.5 Register File ............................................................................................................4-12
4.2.5.1 General-purpose Register RAM .........................................................................4-13
4.2.5.2 Stack Pointer (SP) ..............................................................................................4-13
4.2.5.3 CPU Special-function Registers (SFRs) .............................................................4-14
4.3 WINDOWING............................................................................................................... 4-15
4.3.1 Selecting a Window ................................................................................................4-16
4.3.2 Addressing a Location Through a Window .............................................................4-17
4.3.2.1 32-byte Windowing Example ..............................................................................4-19
4.3.2.2 64-byte Windowing Example ..............................................................................4-19
4.3.2.3 128-byte Windowing Example ............................................................................4-19
4.3.2.4 Unsupported Locations Windowing Example .....................................................4-20
4.3.2.5 Using the Linker Locator to Set Up a Window ....................................................4-20
4.3.3 Windowing and Addressing Modes .........................................................................4-22
4.4 REMAPPING INTERNAL OTPROM (87C196NT ONLY)............................................ 4-23
4.5 FETCHING CODE AND DATA IN THE 1-MBYTE AND 64-KBYTE MODES.............. 4-24
4.5.1 Fetching Instructions ...............................................................................................4-24
4.5.2 Accessing Data .......................................................................................................4-24
4.5.2.1 Using Extended Instructions ..............................................................................4-25
4.5.3 Code Fetches in the 1-Mbyte Mode ........................................................................4-26
4.5.4 Code Fetches in the 64-Kbyte Mode ......................................................................4-26
4.5.5 Data Fetches in the 1-Mbyte and 64-Kbyte Modes .................................................4-27
4.6 MEMORY CONFIGURATION EXAMPLES................................................................. 4-28
4.6.1 Example 1: A 64-Kbyte Mode 87C196NT System ..................................................4-28
4.6.2 Example 2: A 64-Kbyte 87C196NT System with Additional Data Storage ..............4-30
4.6.3 Example 3: A 1-Mbyte 87C196NT System with a 16-bit Bus ..................................4-32
4.6.4 Example 4: A 1-Mbyte 8XC196NT System with an 8-bit Bus .................................4-34

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CHAPTER 5
STANDARD AND PTS INTERRUPTS
5.1 OVERVIEW OF INTERRUPTS...................................................................................... 5-1
5.2 INTERRUPT SIGNALS AND REGISTERS ................................................................... 5-3
5.3 INTERRUPT SOURCES AND PRIORITIES.................................................................. 5-4
5.3.1 Special Interrupts ......................................................................................................5-6
5.3.1.1 Unimplemented Opcode ......................................................................................5-6
5.3.1.2 Software Trap .......................................................................................................5-6
5.3.1.3 NMI .......................................................................................................................5-6
5.3.2 External Interrupt Pins ..............................................................................................5-6
5.3.3 Multiplexed Interrupt Sources ...................................................................................5-7
5.3.4 End-of-PTS Interrupts ...............................................................................................5-7
5.4 INTERRUPT LATENCY................................................................................................. 5-7
5.4.1 Situations that Increase Interrupt Latency ................................................................5-8
5.4.2 Calculating Latency ...................................................................................................5-8
5.4.2.1 Standard Interrupt Latency ...................................................................................5-9
5.4.2.2 PTS Interrupt Latency ..........................................................................................5-9
5.5 PROGRAMMING THE INTERRUPTS......................................................................... 5-10
5.5.1 Programming the Multiplexed Interrupts .................................................................5-11
5.5.2 Modifying Interrupt Priorities ...................................................................................5-14
5.5.3 Determining the Source of an Interrupt ...................................................................5-16
5.5.3.1 Determining the Source of Multiplexed Interrupts ..............................................5-16
5.6 INITIALIZING THE PTS CONTROL BLOCKS............................................................. 5-18
5.6.1 Specifying the PTS Count .......................................................................................5-19
5.6.2 Selecting the PTS Mode .........................................................................................5-20
5.6.3 Single Transfer Mode ..............................................................................................5-21
5.6.4 Block Transfer Mode ...............................................................................................5-24
5.6.5 A/D Scan Mode .......................................................................................................5-26
5.6.5.1 A/D Scan Mode Cycles ......................................................................................5-29
5.6.5.2 A/D Scan Mode Example 1 ................................................................................5-29
5.6.5.3 A/D Scan Mode Example 2 ................................................................................5-30
5.6.6 PWM Modes ...........................................................................................................5-31
5.6.6.1 PWM Toggle Mode Example .............................................................................5-33
5.6.6.2 PWM Remap Mode Example .............................................................................5-37
CHAPTER 6
I/O PORTS
6.1 I/O PORTS OVERVIEW ................................................................................................ 6-1
6.2 INPUT-ONLY PORT 0................................................................................................... 6-1
6.2.1 Standard Input-only Port Operation ..........................................................................6-2
6.2.2 Standard Input-only Port Considerations ..................................................................6-3
6.3 BIDIRECTIONAL PORTS 1, 2, 5, AND 6 ...................................................................... 6-3
6.3.1 Bidirectional Port Operation ......................................................................................6-5
6.3.2 Bidirectional Port Pin Configurations .........................................................................6-9

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CONTENTS
6.3.3 Bidirectional Port Pin Configuration Example .........................................................6-10
6.3.4 Bidirectional Port Considerations ............................................................................6-11
6.3.5 Design Considerations for External Interrupt Inputs ...............................................6-14
6.4 BIDIRECTIONAL PORTS 3 AND 4 (ADDRESS/DATA BUS)...................................... 6-14
6.4.1 Bidirectional Ports 3 and 4 (Address/Data Bus) Operation .....................................6-15
6.4.2 Using Ports 3 and 4 as I/O ......................................................................................6-17
6.4.3 Design Considerations for Ports 3 and 4 ................................................................6-18
6.5 EPORT ........................................................................................................................ 6-18
6.5.1 EPORT Operation ...................................................................................................6-19
6.5.1.1 Reset ..................................................................................................................6-21
6.5.1.2 Output Enable ....................................................................................................6-21
6.5.1.3 Complementary Output Mode ............................................................................6-21
6.5.1.4 Open-drain Output Mode ...................................................................................6-21
6.5.1.5 Input Mode .........................................................................................................6-23
6.5.2 Configuring EPORT Pins ........................................................................................6-24
6.5.2.1 Configuring EPORT Pins for Extended-address Functions ................................6-24
6.5.2.2 Configuring EPORT Pins for I/O ........................................................................6-24
6.5.3 EPORT Considerations ...........................................................................................6-25
6.5.3.1 EPORT Status During Reset, CCB Fetch, Idle, Powerdown, and Hold .............6-25
6.5.3.2 EP_REG Settings for Pins Configured as Extended-address Signals ...............6-25
6.5.3.3 EPORT Status During Instruction Execution ......................................................6-26
6.5.3.4 Design Considerations .......................................................................................6-26
CHAPTER 7
SERIAL I/O (SIO) PORT
7.1 SERIAL I/O (SIO) PORT FUNCTIONAL OVERVIEW ................................................... 7-1
7.2 SERIAL I/O PORT SIGNALS AND REGISTERS .......................................................... 7-2
7.3 SERIAL PORT MODES................................................................................................. 7-4
7.3.1 Synchronous Mode (Mode 0) ....................................................................................7-4
7.3.2 Asynchronous Modes (Modes 1, 2, and 3) ...............................................................7-5
7.3.2.1 Mode 1 .................................................................................................................7-5
7.3.2.2 Mode 2 .................................................................................................................7-6
7.3.2.3 Mode 3 .................................................................................................................7-7
7.3.2.4 Mode 2 and 3 Timings ..........................................................................................7-7
7.3.2.5 Multiprocessor Communications ..........................................................................7-7
7.4 PROGRAMMING THE SERIAL PORT.......................................................................... 7-8
7.4.1 Configuring the Serial Port Pins ................................................................................7-8
7.4.2 Programming the Control Register ............................................................................7-8
7.4.3 Programming the Baud Rate and Clock Source .......................................................7-8
7.4.4 Enabling the Serial Port Interrupts ..........................................................................7-11
7.4.5 Determining Serial Port Status ................................................................................7-12
7.5 PROGRAMMING EXAMPLE USING AN INTERRUPT-DRIVEN ROUTINE............... 7-13

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CHAPTER 8
SYNCHRONOUS SERIAL I/O (SSIO) PORT
8.1 SYNCHRONOUS SERIAL I/O (SSIO) PORT FUNCTIONAL OVERVIEW.................... 8-1
8.2 SSIO PORT SIGNALS AND REGISTERS .................................................................... 8-2
8.3 SSIO OPERATION........................................................................................................ 8-3
8.4 SSIO HANDSHAKING................................................................................................... 8-6
8.4.1 SSIO Handshaking Configuration .............................................................................8-6
8.4.2 SSIO Handshaking Operation ...................................................................................8-7
8.5 PROGRAMMING THE SSIO PORT.............................................................................. 8-9
8.5.1 Configuring the SSIO Port Pins ................................................................................8-9
8.5.2 Programming the Baud Rate and Enabling the Baud-rate Generator .......................8-9
8.5.3 Controlling the Communications Mode and Handshaking ......................................8-11
8.5.4 Enabling the SSIO Interrupts ..................................................................................8-13
8.5.5 Determining SSIO Port Status ................................................................................8-13
8.6 PROGRAMMING CONSIDERATIONS........................................................................ 8-13
8.7 PROGRAMMING EXAMPLE....................................................................................... 8-15
CHAPTER 9
SLAVE PORT
9.1 SLAVE PORT FUNCTIONAL OVERVIEW.................................................................... 9-2
9.2 SLAVE PORT SIGNALS AND REGISTERS................................................................. 9-2
9.3 HARDWARE CONNECTIONS ...................................................................................... 9-6
9.4 SLAVE PORT MODES.................................................................................................. 9-8
9.4.1 Standard Slave Mode Example ................................................................................9-8
9.4.1.1 Master Device Program .......................................................................................9-8
9.4.1.2 Slave Device Program .........................................................................................9-9
9.4.1.3 Demultiplexed Bus Timings ................................................................................9-10
9.4.2 Shared Memory Mode Example ..............................................................................9-11
9.4.2.1 Master Device Program .....................................................................................9-11
9.4.2.2 Slave Device Program .......................................................................................9-12
9.4.2.3 Multiplexed Bus Timings ....................................................................................9-13
9.5 CONFIGURING THE SLAVE PORT............................................................................ 9-14
9.5.1 Programming the Slave Port Control Register (SLP_CON) ....................................9-14
9.5.2 Enabling the Slave Port Interrupts ..........................................................................9-16
9.6 DETERMINING SLAVE PORT STATUS..................................................................... 9-16
9.7 USING STATUS BITS TO SYNCHRONIZE MASTER AND SLAVE........................... 9-16
CHAPTER 10
EVENT PROCESSOR ARRAY (EPA)
10.1 EPA FUNCTIONAL OVERVIEW ................................................................................. 10-1
10.2 EPA AND TIMER/COUNTER SIGNALS AND REGISTERS....................................... 10-2
10.3 TIMER/COUNTER FUNCTIONAL OVERVIEW........................................................... 10-6
10.3.1 Cascade Mode (Timer 2 Only) ................................................................................10-7

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CONTENTS
10.3.2 Quadrature Clocking Mode .....................................................................................10-7
10.4 EPA CHANNEL FUNCTIONAL OVERVIEW............................................................... 10-9
10.4.1 Operating in Capture Mode ...................................................................................10-11
10.4.1.1 Handling EPA Overruns ...................................................................................10-12
10.4.2 Operating in Compare Mode .................................................................................10-13
10.4.2.1 Generating a Low-speed PWM Output ............................................................10-14
10.4.2.2 Generating a Medium-speed PWM Output ......................................................10-15
10.4.2.3 Generating a High-speed PWM Output ...........................................................10-16
10.4.2.4 Generating the Highest-speed PWM Output ....................................................10-16
10.5 PROGRAMMING THE EPA AND TIMER/COUNTERS............................................. 10-17
10.5.1 Configuring the EPA and Timer/Counter Port Pins ...............................................10-17
10.5.2 Programming the Timers .......................................................................................10-17
10.5.3 Programming the Capture/Compare Channels .....................................................10-20
10.5.4 Programming the Compare-only Channels ...........................................................10-25
10.6 ENABLING THE EPA INTERRUPTS ........................................................................ 10-26
10.7 DETERMINING EVENT STATUS.............................................................................. 10-27
10.8 SERVICING THE MULTIPLEXED EPA INTERRUPT WITH SOFTWARE................ 10-29
10.8.1 Using the TIJMP Instruction to Reduce Interrupt Service Overhead ....................10-31
10.9 PROGRAMMING EXAMPLES FOR EPA CHANNELS............................................. 10-33
10.9.1 EPA Compare Event Program ..............................................................................10-33
10.9.2 EPA Capture Event Program ................................................................................10-34
10.9.3 EPA PWM Output Program ..................................................................................10-35
CHAPTER 11
ANALOG-TO-DIGITAL CONVERTER
11.1 A/D CONVERTER FUNCTIONAL OVERVIEW........................................................... 11-1
11.2 A/D CONVERTER SIGNALS AND REGISTERS ........................................................ 11-2
11.3 A/D CONVERTER OPERATION................................................................................. 11-3
11.4 PROGRAMMING THE A/D CONVERTER.................................................................. 11-4
11.4.1 Programming the A/D Test Register .......................................................................11-5
11.4.2 Programming the A/D Result Register (for Threshold Detection Only) ...................11-6
11.4.3 Programming the A/D Time Register ......................................................................11-6
11.4.4 Programming the A/D Command Register ..............................................................11-8
11.4.5 Enabling the A/D Interrupt .......................................................................................11-9
11.5 DETERMINING A/D STATUS AND CONVERSION RESULTS.................................. 11-9
11.6 DESIGN CONSIDERATIONS.................................................................................... 11-10
11.6.1 Designing External Interface Circuitry ...................................................................11-11
11.6.1.1 Minimizing the Effect of High Input Source Resistance ....................................11-12
11.6.1.2 Suggested A/D Input Circuit .............................................................................11-13
11.6.1.3 Analog Ground and Reference Voltages .........................................................11-13
11.6.1.4 Using Mixed Analog and Digital Inputs ............................................................11-14
11.6.2 Understanding A/D Conversion Errors ..................................................................11-14