Intel Agilex F Series User manual

Intel® Agilex™ F-Series FPGA (Two
F-Tiles) Development Kit User Guide
Online Version
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Version: 2022.09.21

Contents
1. Overview........................................................................................................................ 4
1.1. Block Diagram.......................................................................................................4
1.2. Feature Summary..................................................................................................5
1.3. Box Contents........................................................................................................ 6
1.4. Recommended Operating Conditions........................................................................ 6
2. Getting Started............................................................................................................... 7
2.1. Intel Quartus® Prime Software and Driver Installation................................................ 7
2.2. Design Examples................................................................................................... 7
3. Power Up the Development Kit....................................................................................... 9
3.1. Default Settings.................................................................................................... 9
3.2. Applying Power to the Development Board.............................................................. 10
4. Board Test System........................................................................................................ 12
4.1. Set Up BTS GUI Running Environment.................................................................... 12
4.1.1. Download OpenJDK.................................................................................. 13
4.1.2. Download OpenJFX.................................................................................. 13
4.1.3. Install OpenJDK and OpenJFX.................................................................... 13
4.1.4. Install the Intel Quartus Prime Software .....................................................14
4.1.5. Run BTS GUI........................................................................................... 14
4.2. Test the Functionality of the Development Kit.......................................................... 16
4.2.1. The Bottom Info Bar.................................................................................16
4.2.2. The Configure Menu................................................................................. 16
4.2.3. The Sys Info Tab...................................................................................... 17
4.2.4. The GPIO Tab.......................................................................................... 18
4.2.5. The XCVR Tab..........................................................................................19
4.2.6. The Memory Tab...................................................................................... 23
4.3. Control On-Board Clock through Clock Controller GUI............................................... 25
4.4. Monitor On-Board Power Regulator through Power Monitor GUI.................................. 26
4.5. BTS Test Areas.................................................................................................... 27
4.6. Identify Test Pass- or Fail-based on BTS GUI Test Status........................................... 27
5. Development Kits Hardware and Configuration.............................................................28
5.1. JTAG Configuration Mode...................................................................................... 28
5.2. Active Serial (AS) x4 Configuration Mode................................................................ 28
5.3. Avalon-ST x16 Configuration Mode......................................................................... 28
6. Custom Projects for the Development Kit..................................................................... 30
6.1. Add SmartVID Settings in the Intel Quartus Prime QSF File....................................... 30
6.2. Golden Top......................................................................................................... 30
7. Revision History............................................................................................................31
A. Development Kit Components....................................................................................... 32
A.1. Board Overview and Components...........................................................................32
A.1.1. Board Overview....................................................................................... 32
A.1.2. Board Components...................................................................................32
A.1.3. Intel MAX 10 CPLD System Controller......................................................... 36
Contents
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A.2. FPGA Configuration.............................................................................................. 36
A.2.1. Programming the FPGA over On-Board Intel FPGA Download Cable II............. 37
A.2.2. Programming the FPGA over an External Intel FPGA Download Cable II........... 37
A.3. Default Switch and Jumper Settings....................................................................... 37
A.3.1. Switch Description................................................................................... 38
A.3.2. Jumper Description.................................................................................. 39
A.4. Input and Output Components...............................................................................40
A.4.1. Push Buttons...........................................................................................40
A.4.2. Switches.................................................................................................40
A.4.3. LEDs...................................................................................................... 41
A.5. Components and Interfaces...................................................................................41
A.5.1. PCI Express (PCIe) Interface..................................................................... 41
A.5.2. QSFP-DD Interface...................................................................................44
A.5.3. QSFP Interface........................................................................................ 46
A.5.4. CXL Interface.......................................................................................... 47
A.5.5. DDR4 DIMM1 Interface.............................................................................48
A.5.6. DDR4 DIMM2 Interface.............................................................................52
A.5.7. DDR4 Component Interface.......................................................................57
A.5.8. HPS I/O48 Interface.................................................................................60
A.6. I2C.................................................................................................................... 61
A.7. Intel MAX 10 SPI Bus........................................................................................... 63
A.8. Clock Circuits...................................................................................................... 63
A.9. HPS Daughter Card.............................................................................................. 64
A.10. System Power................................................................................................... 66
A.11. Power Guidelines............................................................................................... 67
A.11.1. In a Standard PCIe-Compliant System...................................................... 67
A.11.2. As a Standalone Evaluation Board Powered by Included Power Supply........... 67
A.12. Power Distribution System.................................................................................. 68
A.13. Power Measurement........................................................................................... 69
A.14. Thermal Limitations and Protection.......................................................................69
B. Additional Information................................................................................................. 70
B.1. Safety and Regulatory Information.........................................................................70
B.1.1. Safety Warnings...................................................................................... 71
B.1.2. Safety Cautions....................................................................................... 72
B.2. Compliance Information........................................................................................75
Contents
Send Feedback Intel® Agilex™ F-Series FPGA (Two F-Tiles) Development Kit User Guide
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1. Overview
The Intel® Agilex™ FPGA Development Kit provides a hardware development platform
for evaluating the performance and features of the Intel Agilex F-Series FPGA with two
F-tiles.
Table 1. Ordering Information
Development Kit Version Ordering Code Device Part Number
Intel Agilex F-Series FPGA (Two F-Tiles
Edition) Development Kit (ES)
DK-DEV-AGF027F1ES AGFB027R24C2E2VR2(1)
For more information about the Intel Agilex ES Device Errata Sheet and User
Guidelines (ES-1069), contact Intel Premier Support and quote ID #15011992053.
1.1. Block Diagram
Figure 1. Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit Block Diagram
MCIO x4
QSFP-56
QSFPDD-56
I2C
I2C
128K
EEPROM
FRUID
EEPROM
LEDs,
Switches,
Push buttons IO
EXP
PCIe 4.0 x16
Gold Fingers
4-TX/RX
4-TX/RX
8-TX/RX
F-TILE
(U20-12C)
2D 2C 2F 2E
3A 3B 3C 3D HPS
X40 HPS
DDR4
COMP
(1,600 MHz)
x48
16-TX/RX
F-TILE
(U12-13A)
SDM
MSEL
Switches
ASx4
Avalon®
Streaming x16
JTAG
MSEL
QSPI
Flash
QSPI
Flash
Intel® MAX®
FPGA
System
Controller
USB
PHY
JTAG
CTRL
SPI
I2C
I2C
I2C
Nios®
Flash
Clock
Circuitry
IEEE1588
Support
Board PWR
Circuitry
PWR
Input
uUSB
DDR4 x72 DIMM / DDR-T (1 rank up to 3,200 Mbps)
DDR4 x72 DIMM / DDR-T (1 rank up to 3,200 Mbps)
IO48
Daughter
Card
MAC
EEPROM Temp Sensors
Intel ®
Agilex ™
FPGA SoC
AGFB027R24C2E2VR2
(1) AGFB027R24C2E2VR2 supports PCIe* x8 interface and not PCIe x16 interface.
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Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

1.2. Feature Summary
• Intel Agilex F-Series (AGFB027) device in 2340A BGA package
— Quad-core 64-bit Arm Cortex-A53 hard processor (HPS)
— 0.8 V VID-adjustable VCC core
— Dual F-tile transceivers supporting 56 Gbps (PAM4) and 32 Gbps (NRZ) data
rates
— 2.69M logic elements (LE)
— 3.65M adaptive logic modules (ALM)
— 8.5K digital signal processing (DSP) blocks
• FPGA configuration
— Avalon®-ST x16 and active serial (AS) x4 configuration modes support
— 2 Gb flash for AS x4
— Dual 2 Gb flash for Avalon-ST x16
— JTAG header for device programming
— Built-in Intel FPGA Download Cable II for device programming
• Programmable clock sources
• Transceiver interfaces
— PCI Express* (PCIe) x16 interface supporting Gen 4 end-point connected to a
PCIe x16 edge connector (gold edge fingers)
— 1x QSFP optical module interface connected to F-tile transceiver
— 1x QSFPDD optical module interface connected to F-tile transceiver
— 1x PCIe/CXL interface supporting x4 interface connected to MCIO connector
• Memory interfaces
— Two x72 DIMM sockets supporting DDR4-2666 or DDR-T Intel Optane™
persistent memory module
— Single x40 DDR4 component interface for HPS processor memory
• Communication ports
— JTAG header
— Micro USB on-board Intel FPGA Download Cable II
— System I2C header
• Buttons, switches, and LEDs
— CPU reset push button
— PCIe reset push button
— CXL reset push button
— HPS reset push button
— Four dedicated user LEDs
— Board power good LED
— FPGA configuration done LED
1. Overview
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• Heatsink and fan
— Air-cooled heatsink assembly
— Red over-temperature warning LED
• Power
— PCIe input power including required 2x4 auxiliary power connector
— Blue power-good status LED
— On/off slide power switch for benchtop operation
— On-board power and temperature measurement circuitry
• Mechanical
— PCIe standard height form-factor (full height, ¾ length, dual-width)
— 4.375” x 10.0” board size
— Two slots height with heatsink/fan assembly
• Operating environment
— Maximum ambient temperature of 0-35°C
1.3. Box Contents
• Intel Agilex F-Series (Two F-Tiles)FPGA Development Kit
• 1x DDR4 DIMM module
• 1x IO48 HPS daughter board
• USB 2.0 MicroUSB cable
• 240W power adapter and NA/EU/JP/UK cords
1.4. Recommended Operating Conditions
Table 2. Recommended Operating Conditions
Operating Condition Range of Values
Ambient operating temperature range 0°C to 35°C
Maximum ICC load current 150 A
Maximum ICC load transient percentage 30%
FPGA maximum power supported by active heatsink/fan 150 W
When handling the board, it is important to observe static discharge precautions.
Caution: Without proper anti-static handling, the board can be damaged. Therefore, use anti-
static handling precautions when touching the development kit.
Caution: This development kit should not be operated in a vibration environment.
1. Overview
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2. Getting Started
2.1. Intel Quartus® Prime Software and Driver Installation
Intel Quartus® Prime design software is a multiplatform design environment that
easily adapts to your specific needs in all phases of FPGA, CPLD and SoC designs. The
Intel Quartus Prime software delivers the highest performance and productivity for
Intel FPGAs, CPLDs, and SoCs. Intel Quartus Prime Pro Edition software is optimized
to support the advanced features in next-generation FPGAs and SoCs with the Intel
Agilex, Intel Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 GX device families.
Intel Agilex F-Series (Two F-Tiles) Development Kit includes on-board Intel FPGA
Download Cable II circuits for FPGA and system Intel MAX® 10 programming.
However, for the host computer and board to communicate, you must install the Intel
FPGA Download Cable II driver on the host computer. Installation instructions for the
Intel FPGA Download Cable II driver for your operating system are available on the
Intel website.
On the Intel website, navigate to the Cable and Adapter Drivers Information link to
locate the table entry for your configuration and click the link to access the
instructions.
Related Information
•Quick-Start for Intel Quartus Prime Pro Edition Software
•Intel Quartus Prime Pro Edition User Guide: Getting Started
2.2. Design Examples
Unzip the install package which includes board design files, documents and examples
directories. The table below lists the file directory names and a description of their
contents.
Table 3. Installed Development Kit Directory Structure
Directory Name Description of Directory Contents
board_design_files Contains schematics, layout, assembly and bill of material
board design files. Use these files as a starting point for a
new prototype board design.
demos Contains demonstration applications when available.
documents Contains the development kit documentation.
examples Contains:
continued...
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Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

Directory Name Description of Directory Contents
• Board Test System: BTS GUI, Power GUI, and Clock GUI
• Golden Top project for pinout assignments management
• Design Examples: Memory, XCVR, GPIO, PCIe Gen 4
factory_recovery Contains the original data programmed onto the board
before shipment. Use this data to restore the board with its
original factory content.
2. Getting Started
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3. Power Up the Development Kit
This chapter describes how to apply power to the development board and provides
default switch and jumper settings.
3.1. Default Settings
The Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit ships with its board
switches preconfigured to support the design examples in the kit. If you suspect your
board might not be correctly configured with the default settings, follow the
instructions in the table below to return to its factory settings before proceeding.
Table 4. Factory Default Switch Settings
Switch Default Position Function
SW1[1:4] ON/OFF/OFF/OFF PCIe PRSNT x1/x4/x8/x16 settings switches. Default = x16.
PRSNT x16 PRSNT x8 PRSNT x4 PRSNT x1
ON OFF OFF OFF
SW2 ON Intel FPGA Download Cable II JTAG Selection switch. Default ON selects
the micro-USB port on-board blaster for FPGA programming.
SW3[1:4] ON/ON/ON/OFF Configuration mode selection, BMC JTAG selection, and HPS JTAG Bypass
switches.
SW3[1:2]—Configuration mode selection. MSEL0 is pulled high. Default
mode is AS x4.
Mode SW3[1] - MSEL1 SW3[2] - MSEL2
JTAG OFF OFF
Avalon-ST x16 ON OFF
AS x4 (Fast) ON ON
SW3[3]—BMC JTAG selection.
• ON selects the on-board blaster as JTAG master when no external
blaster is plugged
• OFF selects the PCIe RP as JTAG master when no external blaster is
plugged
• Default JTAG chain selects the FPGA
SW4[4]—HPS JTAG Enable.
• ON enables the HPS as part of the JTAG chain
• OFF bypasses the HPS from the JTAG chain
• The HPS is set to bypass by default
SW4[1:4] OFF/OFF/OFF/OFF Clock features selection switches.
continued...
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Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

Switch Default Position Function
SW4[4]—SI52204 (U25) PCIe clock power down.
• ON powers down the PCIe clocks
• OFF powers on the PCIe clocks (Default)
SW4[3]—PCIe refclk source selection.
• ON selects the local 100 Mhz clock source for PCIe
• OFF selects 100 Mhz clock source from the PCIe edge fingers
(Default)
SW4[2]—CXL refclk source selection.
•ON selects local 100 Mhz clock source for CXL refclk
• OFF select 100 Mhz clock source from CXL connector (Default)
SW4[1]—PCIe clock spread spectrum enable.
• ON—Enable 0.5% down-spread
• OFF—Spread spectrum disable (Default)
SW5 OFF Power switch. Slide to ON position to turn on the board. Default is OFF.
SW6 OFF Intel MAX 10 JTAG_EN switch.
• ON sets the JTAG pins to function as dual-purpose I/O pins and JTAG
function if the JTAG pin sharing option bit is enabled by the Intel
Quartus Prime software.
• OFF sets the JTAG pins to function as JTAG dedicated pins if the JTAG
pin sharing option bit is enabled by the Intel Quartus Prime software
(Default).
3.2. Applying Power to the Development Board
This development kit is designed to operate in two modes:
As a PCIe Add-In Card
When operating the card as a PCIe system, insert the card into an available PCIe slot
and connect a 2x4 pin PCIe power cable from the system to power connectors at J11
of the board.
Note: When operating as a PCIe add-in card, the board does not power on unless power is
supplied to J11.
In Bench-Top Mode
In bench-top mode, you must supply the board with the provided power 240 W power
supply connected to the power connector J11. The following describes the operation in
bench-top mode.
This development board ships with its switches preconfigured to support the design
examples in the kit.
If you suspect that your board may not be correctly configured with the default
settings, follow the instructions in the Default Switch and Jumper Settings section.
1. The development board ships with design examples stored in the flash memory
device for Avalon-ST x16. Ensure SW3[1] is ON and SW3[2] is OFF before
powering up the board.
2. Connect the supplied power supply to an outlet and the DC Power Jack to J11 on
the FPGA board.
3. Power Up the Development Kit
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Note: Use only the supplied power supply. Power regulation circuits on the board
can be damaged by power supplies with greater voltage.
3. Set the power switch (SW5) to the ON position.
When the board powers up, the blue power-on LED (D2) illuminates signaling the
board is ready for use. Since the default configuration mode is Avalon-ST x4, the
FPGA automatically downloads its configuration image from the QSPI flash device
connected to the FPGA's SDM interface. When the configuration is complete, green
LED (D12) illuminates signaling the device configured successfully. If the
configuration fails, D12 will not illuminate.
3. Power Up the Development Kit
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4. Board Test System
The Intel Agilex F-Series FPGA (Two F-Tiles) Development Kit includes design
examples and the board test system (BTS) GUI to test the functionality of this board.
The BTS provides an easy-to-use interface to alter functional settings and observe
results. You can use the BTS to test board components, modify functional parameters,
observe performance, and measure power usage.
While using the BTS, you reconfigure the FPGA several times with test designs specific
to the functionality that you are testing. The BTS is also useful as a reference for
designing systems. The BTS communicates over the JTAG bus to a test design running
in the Intel Agilex F-Series FPGA device.
The following figure shows the graphical user interface (GUI) of a board that is in
factory configuration.
Figure 2. BTS GUI
4.1. Set Up BTS GUI Running Environment
To run BTS GUI, including Power Monitor and Clock Controller GUI, you need to
download and install Java runtime including OpenJDK and OpenJFX on your systems
and set up the running environment. This is a one-time procedure, so if you have
already completed it before, you do not need to do it again unless the Java version
upgrade is needed.
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Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

4.1.1. Download OpenJDK
To download the Temurin OpenJDK, follow these steps:
1. Download the Temurin OpenJDK using this link: https://adoptium.net/
releases.html.
2. Select Architecture x64, Package Type JRE, and Version 11.
3. On Windows system, choose the JRE zip format file.
4. On Linux system, choose the JRE tar.gz format file.
Figure 3. OpenJDK Version
Note: The JDK version can be updated, download the latest version.
4.1.2. Download OpenJFX
To download the OpenJFX, follow these steps:
1. Download the OpenJFX using this link: https://gluonhq.com/products/javafx/.
2. Select JavaFX version 17.0.2.
3. For the Windows system, download the JavaFX Windows x64 SDK.
4. For Linux system, download the JavaFX Linux x64 SDK.
Figure 4. JavaFX Version
4.1.3. Install OpenJDK and OpenJFX
You have two downloaded zip files, follow these steps to install them.
1. On Windows system, Intel recommends you to unzip the files and put them in
the following directory:
— C:\Program Files\Java\jre
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— C:\Program Files\Java\jfx
Note: The unzipped folder name of JRE is jdk-11.0.xx+x-jre (for example,
jdk-11.0.15+10-jre), you need to rename it to jre. The unzipped folder
name of JFX is javafx-sdk-17.0.2, you need to rename it to jfx.
2. On Linux system, Intel recommends you to unzip the files and rename the folders
using the following commands:
# unzip openjfx-17.0.2_linux-x64_bin-sdk.zip -d /opt/Java/
# tar zxvf OpenJDK11U-jre_x64_linux_hotspot_11.0.15_10.tar.gz -C /opt/Java/
# cd /opt/Java
# mv javafx-sdk-17.0.2 jfx
# mv jdk-11.0.15+10-jre jre
You have the following two directories on your Linux system:
— /opt/Java/jre
— /opt/Java/jfx
4.1.4. Install the Intel Quartus Prime Software
You need to install the Intel Quartus Prime software that can support the silicon on the
development kit. The recommended version can be found in the README.txt file
under examples\board_test_system directory. If you choose to install individual
files, you must install the Intel Agilex device support.
The BTS communicates over JTAG to a test design running in the FPGA. The BTS and
Power Monitor share the JTAG with other applications like the Nios® II Gen 2 JTAG
Debug Module and the Signal Tap Logic Analyzer. Ensure closing other applications
before you use the BTS, because the BTS is designed based on the Intel Quartus
Prime software.
The BTS relies on the Intel Quartus Prime software's specific library. Before running
the BTS, open the Intel Quartus Prime software to automatically set the environment
variable QUARTUS_ROOTDIR. Otherwise, you can change it through the Environment
Variables in System Properties on Windows. The BTS uses this environment variable to
locate the Intel Quartus Prime library.
4.1.5. Run BTS GUI
With the power to the board off, follow these steps:
1. Connect the USB cable to your PC and the board.
2. Ensure the development board switches and jumpers are set according to your
preferences. For more information, refer to the Factory Default Switch Settings
section.
3. Check the external modules' status: QSFP/QSFPDD/DDR4 DIMM.
4. Turn on the board power switch.
Note: To ensure operating stability, keep the USB cable connected and the board
powered on when running the demonstration application. The BTS cannot
run correctly unless the USB cable is attached and the board is powered on.
Navigate to the <package dir>\examples\board_test_system directory. The
BTS release folder includes the following files.
4. Board Test System
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Figure 5. BTS Folder
You can run BTS GUI easily with the following scripts.
1. On Windows system, double click the .bat files to run BTS, Clock Controller, or
Power Monitor GUI.
Figure 6. Windows Console
2. On Linux system, you need to run the shell script with root privilege.
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Figure 7. Linux Console
Note: The .bat or shell script checks the Java environment settings, copy necessary files,
and give some prompts if the environment is not set up correctly.
The GUI displays the application tab corresponding to the design running in the FPGA.
If the design loaded in the FPGA is not supported by the BTS GUI, you receive a
message prompting you to configure your board with a valid BTS design. For more
information, refer to the Configure Menu section.
4.2. Test the Functionality of the Development Kit
This section describes each control in the BTS.
4.2.1. The Bottom Info Bar
The bottom information bar shows the status of the system connection, the Intel
Quartus Prime version and the JTAG clock.
•System Connected/Disconnected: Shows if the board is connected to the
system. The green sign turns gray if the board becomes disconnected.
•Intel Quartus Prime Version: Displays the current Intel Quartus Prime version
installed and active on your system. The text turns red if your version is older
than the required version. Change the QUARTUS_ROOTDIR environment variable if
you have installed the right version but the active version doesn’t meet the
requirement.
•JTAG: Displays the JTAG clock frequency.
4.2.2. The Configure Menu
Use the Configure Menu to select the design you want to use. Each design example
tests different functionality that corresponds to one or more application tabs.
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Figure 8. The Configure Menu
To configure the FPGA with a test system design, follow these steps:
1. On the Configure menu, click the Configure command that corresponds to the
functionality you want to test.
2. In the dialog box that appears, click Configure to download the corresponding
design's SRAM Object File (.sof) to the FPGA. The download process usually takes
less than a minute.
3. When configuration finishes, the design begins running in the FPGA. The
corresponding GUI application tabs that interface with the design are now
enabled. If you use the Intel Quartus Prime Programmer for configuration, instead
of the BTS GUI, you need to restart the GUI.
4.2.3. The Sys Info Tab
The Sys Info tab shows information about the board's current configuration. The tab
displays the board information, JTAG Chain devices and other details stored on the
board.
Figure 9. The Sys Info Tab
4. Board Test System
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The following sections describe the controls on the System Info tab.
Board Information
The board information control displays static information about your board.
•Board Name: Indicates the official name of the board given by the BTS.
•Board Revision: Indicates the revision of the board.
•MAX Version: Indicates the version of the system Intel MAX 10.
JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain.
Note: Both System Intel MAX 10 and FPGA must be in the JTAG chain when running the BTS
GUI.
4.2.4. The GPIO Tab
The GPIO tab allows you to interact with all the general-purpose user I/O components
on your board. You can turn LEDs on or off and detect I2C target devices connection
status.
Figure 10. The GPIO Tab
The following sections describe the controls on the GPIO tab.
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User LEDs
The User LEDs control displays the current state of the user LEDs. Toggle the LED
buttons to turn the board LEDs on and off. Click the All button to reverse the state of
all the LEDs.
I2C
The read-only I2C target device control displays the connection status of some
devices, which can be accessed by I2C bus. The status of QSFP and QSFPDD modules
can be updated in real time.
Platform Designer Memory Map
The Platform Designer Memory Map control shows the memory map of
bts_config.sof design running on your board.
4.2.5. The XCVR Tab
The XCVR tab allows you to run transceiver tests on your board. You can run the test
using either electrical loopback modules or optical fiber modules.
4.2.5.1. The QSFP NRZ Tab
Figure 11. The QSFP NRZ Tab
The following sections describe controls in the QSFP NRZ tab.
Status
The Status control displays the following status information during the loopback test:
•PLL Lock: Shows the PLL locked or unlocked state.
•Pattern Sync: Shows the pattern synced or not state. The pattern is considered
synced when the start of the data sequence is detected.
•Detail: Shows the PLL lock and pattern sync status of each channel. The number
of the error bits of each channel can be found here.
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PMA Setting
Allows you to make changes to the PMA parameters that affect the active transceiver
interface. The following settings are available for analysis:
•Serial Loopback: Displays the signal status between the transmitter and the
receiver.
•VOD: Specifies the voltage output differential of the transmitter buffer.
•Pre-emphasis tap:
— Pre-tap 1: Specifies the amount of pre-emphasis on the first pre-tap of the
transmitter buffer.
— Pre-tap 2: Specifies the amount of pre-emphasis on the second pre-tap of the
transmitter buffer.
— Post-tap 1: Specifies the amount of pre-emphasis on the post-tap of the
transmitter buffer.
Figure 12. QSFP NRZ-PMA Setting
Data Type
The Data Type control specifies the type of data pattern contained in the transactions.
Select the following available data types for analysis:
•PRBS7: pseudo-random 7-bit binary sequences
•PRBS15: pseudo-random 15-bit binary sequences
•PRBS23: pseudo-random 23-bit binary sequences
•PRBS31: pseudo-random 31-bit binary sequences (default)
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