Intel Agilex User manual

Intel® Agilex™ Embedded Memory
User Guide
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Contents
1. Intel® Agilex™ Embedded Memory Overview...................................................................3
1.1. Intel Agilex Embedded Memory Features...................................................................3
2. Intel Agilex Embedded Memory Architecture and Features............................................. 6
2.1. Byte Enable in Intel Agilex Embedded Memory Blocks.................................................6
2.1.1. Byte Enable Controls..................................................................................6
2.1.2. Data Byte Output.......................................................................................7
2.1.3. Byte Enable Behavior................................................................................. 8
2.2. Address Clock Enable Support................................................................................. 8
2.3. Asynchronous Clear and Synchronous Clear.............................................................10
2.4. Memory Blocks Error Correction Code Support......................................................... 12
2.4.1. Parity Bit................................................................................................ 13
2.4.2. ECC Parity Flip.........................................................................................13
2.4.3. ECC Read-During-Write Behavior................................................................13
2.4.4. Error Correction Code Truth Table...............................................................14
2.5. Intel Agilex Embedded Memory Clocking Modes....................................................... 14
2.5.1. Single Clock Mode....................................................................................15
2.5.2. Read/Write Clock Mode.............................................................................15
2.5.3. Input/Output Clock Mode.......................................................................... 15
2.5.4. Asynchronous/Synchronous Clears in Clocking Modes................................... 15
2.5.5. Output Read Data in Simultaneous Read/Write.............................................16
2.5.6. Independent Clock Enables in Clocking Modes..............................................16
2.6. Intel Agilex Embedded Memory Configurations.........................................................16
2.6.1. Mixed-Width Port Configurations................................................................ 16
2.7. Force-to-Zero...................................................................................................... 17
2.8. Coherent Read Memory........................................................................................ 17
2.8.1. Forwarding Logic......................................................................................20
2.9. Freeze Logic........................................................................................................22
2.10. True Dual Port Dual Clock Emulator...................................................................... 22
2.11. Initial Value of Read and Write Address Registers................................................... 26
3. Intel Agilex Embedded Memory Design Considerations.................................................27
3.1. Consider the Memory Block Selection..................................................................... 27
3.2. Consider the Concurrent Read Behavior.................................................................. 27
3.3. Customize Read-During-Write Behavior...................................................................28
3.3.1. Same-Port Read-During-Write Mode........................................................... 28
3.3.2. Mixed-Port Read-During-Write Mode........................................................... 29
3.4. Consider Power-Up State and Memory Initialization.................................................. 33
3.5. Reduce Power Consumption.................................................................................. 34
3.6. Advanced Settings in Intel Quartus Prime Software for Memory..................................34
4. Intel Agilex Embedded Memory Debugging...................................................................35
5. Document Revision History for the Intel Agilex Embedded Memory User Guide............ 36
Contents
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1. Intel® Agilex™ Embedded Memory Overview
Intel® Agilex™ embedded memory blocks are flexible and provide an optimal amount
of various sized memory arrays to fit your design requirements.
1.1. Intel Agilex Embedded Memory Features
The Intel Agilex devices contain three types of memory blocks: Embedded SRAM
(eSRAM) blocks, M20K blocks, and memory logic array blocks (MLABs).
• 18.432-Megabit (Mb) eSRAM blocks
— Fast path, low latency, high bandwidth and very high random transaction rate
(RTR) on-chip memory block
— Each block consists of 8 channels and each channel has 32 banks.
— Each bank is configurable to 1K depth and 72-bit data width
— Supports only simple dual-port RAM with concurrent read and write access per
channel
• 20-kilobit (Kb) M20K blocks
— Blocks of dedicated memory resources.
— Ideal for larger memory arrays, while providing a large number of independent
ports.
• 640-bit MLABs
— Enhanced memory blocks configured from dual-purpose logic array blocks
(LABs).
— Ideal for wide and shallow memory arrays.
— Optimized for implementation of shift registers for digital signal processing
(DSP) applications, wide and shallow FIFO buffers, and filter delay lines.
— Each MLAB is made up of ten adaptive logic modules (ALMs).
In Intel Agilex devices, you can configure each ALM in the MLAB as ten 32×2 blocks.
The Intel Agilex devices provide one 32×20 simple dual-port SRAM block per MLAB.
The Intel Agilex embedded memory blocks support the following operation modes:
• Single-port
• Simple dual-port
• True dual-port
• Simple quad-port
• ROM
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other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
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Registered

Table 1. Intel Agilex Embedded Memory Features
This table summarizes the features supported by the Intel Agilex embedded memory blocks.
Features eSRAM M20K MLAB
Maximum operating
frequency
750 MHz • 1 GHz (simple dual-port
RAM mode)
• 600 MHz (true dual-port
and simple quad-port
RAM mode)
1 GHz
Total RAM bits (including
parity bits)
18.432 Mb 20,480 bits 640 bits
Byte enable N/A Supported Supported
Address clock enable N/A Supported (only in simple
dual-port RAM mode)
Supported
Simple dual-port mixed
width
N/A Supported N/A
FIFO buffer mixed width N/A Supported N/A
Memory Initialization File
(.mif)
N/A Supported Supported
Dual-clock mode N/A Supported (only in simple
dual-port RAM mode)
Supported
Full synchronous memory N/A Supported Supported
Asynchronous memory N/A N/A Only for flow-through read
memory operations
Power-up state N/A Output ports are cleared • Registered output ports
are cleared
• Unregistered output
ports read memory
contents
Asynchronous/Synchronous
Clears
N/A • Output registers and
output latches
• Supports asynchronous
clear on read address
registers (only in simple
dual-port and simple
quad-port modes)
Output registers and output
latches
Write/read operation
triggering
Rising clock edges Rising clock edges Rising clock edges
Same-port read-during-write N/A Output ports set to New
Data, Old Data, or Don't
Care
Output ports set to Don't
Care
Mixed-port read-during-write Write-forwarding feature
• ON = New Data
• OFF = Old Data
• Simple Dual Port RAM:
Output ports set to Old
Data or Don't Care
• True Dual Port RAM:
Output ports set to Don't
Care
• Simple Quad Port:
Output ports set to
new_a_old_b
Output ports set to New
Data, Old Data, or Don't
Care
continued...
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Features eSRAM M20K MLAB
Error Correction Code (ECC)
support
• Soft IP using the Intel
Quartus® Prime software
• Built-in support ×64-
wide simple dual-port
mode
• Soft IP using the Intel
Quartus Prime software
• Hard IP
• Built-in support ×32-
wide simple dual-port
mode
• Parity bits
Soft IP using the Intel
Quartus Prime software
Force-to-Zero N/A Supported N/A
Coherent read memory N/A Supported N/A
Freeze logic N/A Supported N/A
True dual port (TDP) dual
clock emulator
N/A Supported N/A
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2. Intel Agilex Embedded Memory Architecture and
Features
The Intel Agilex embedded memory features include operation modes, clocking
modes, and configurations.
2.1. Byte Enable in Intel Agilex Embedded Memory Blocks
The Intel Agilex embedded memory blocks support byte enable controls.
• The byte enable controls mask the input data so that only specific bytes of data
are written. The unwritten bytes retain the values written previously.
•The write enable (wren) signal, together with the byte enable (byteena) signal,
control the write operations on the embedded memory blocks. By default, the
byteena signal is high (enabled) and only the wren signal controls the writing.
•The byte enable registers do not have a clear port.
•The LSB of the byteena signal corresponds to the LSB of the data bus.
• The byte enable signals are active high.
2.1.1. Byte Enable Controls
Table 2. Byte Enable Controls in ×10 Data Width (MLAB)
Byte Enable [1:0] Data Bits Written
11 (default) [9:5] [4:0]
10 [9:5] N/A
01 N/A [4:0]
00 N/A N/A
Table 3. Byte Enable Controls in ×20 Data Width (M20K)
Byte Enable [1:0] Data Bits Written
11 (default) [19:10] [9:0]
10 [19:10] N/A
01 N/A [9:0]
00 N/A N/A
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Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or
other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in
accordance with Intel's standard warranty, but reserves the right to make changes to any products and services
at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel
customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

Table 4. Byte Enable Controls in ×40 Data Width (M20K)
Byte Enable [3:0] Data Bits Written
1111 (default) [39:0] [29:0] [19:10] [9:0]
1110 [39:0] [29:0] [19:10] N/A
1101 [39:0] [29:0] N/A [9:0]
1100 [39:0] [29:0] N/A N/A
1011 [39:0] N/A [19:10] [9:0]
1010 [39:0] N/A [19:10] N/A
1001 [39:0] N/A N/A [9:0]
1000 [39:0] N/A N/A N/A
0111 N/A [29:0] [19:10] [9:0]
0110 N/A [29:0] [19:10] N/A
0101 N/A [29:0] N/A [9:0]
0100 N/A [29:0] N/A N/A
0011 N/A N/A [19:10] [9:0]
0010 N/A N/A [19:10] N/A
0001 N/A N/A N/A [9:0]
0000 N/A N/A N/A N/A
2.1.2. Data Byte Output
In M20K blocks or MLABs, when you de-assert a byte-enable bit to 0 during a write
cycle, the corresponding data byte output appears as the current data at that location.
You can control the output value for the masked byte in the M20K blocks or MLABs in
the same-port read-during-write mode by using the Platform Designer in Intel Quartus
Prime software.
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2.1.3. Byte Enable Behavior
Figure 1. Byte Enable Functional Waveform
This figure shows how the wren and byteena signals control the operations of the embedded memory blocks.
inclock
wren
address
data
byteena
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
current data: q (asynch)
an a0 a1 a2 a3 a4 a0
XXXXXXXX XXXXXXXX
ABCDEF12
ABCDEF12
XXXX XXXX1000 0100 0010 0001 1111
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFF12
FFFFFF12
FFFFEFFF
FFFFEFFF
FFCDFFFF
FFCDFFFF
ABFFFFFF
ABFFFFFF
doutn ABFFFFFFABCDEF12
2.2. Address Clock Enable Support
Intel Agilex embedded memory blocks support address clock enable. When you enable
address clock enable (addressstall = 1), it holds the previous address value.
Note: 1. Only simple dual-port mode supports this feature.
2. The addressstall signal cannot be asserted during the first clock cycle as this
can result the output having non-deterministic values.
When you configure the memory blocks in dual-port mode, each port has its own
independent address clock enable.
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Figure 2. Address Clock Enable
This figure shows an address clock enable block diagram.
address[0]
address[N]
addressstall
clock
1
0
address[0]
register
address[N]
register address[N]
address[0]
1
0
Figure 3. Address Clock Enable During Read Cycle
This figure shows the address clock enable behavior during read cycle.
inclock
rden
rdaddress
q (synch)
a0 a1 a2 a3 a4 a5 a6
q (asynch)
an a0 a4 a5
latched address
(inside memory)
dout0 dout1 dout4
dout4 dout5
addressstall
a1
doutn-1 doutn
doutn dout0 dout1
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Figure 4. Address Clock Enable During Write Cycle
This figure shows the address clock enable behavior during write cycle.
inclock
wren
wraddress a0 a1 a2 a3 a4 a5 a6
an a0 a4 a5
latched address
(inside memory)
addressstall
a1
data 00 01 02 03 04 05 06
contents at a0
contents at a1
contents at a2
contents at a3
contents at a4
contents at a5
XX
04
XX
00
03
01
XX 02
XX
XX
XX 05
2.3. Asynchronous Clear and Synchronous Clear
The Intel Agilex M20K and MLAB embedded memory blocks support asynchronous
clear and synchronous clear on output latches and output registers.
Note: The M20K blocks support asynchronous clear on read address registers, but is limited
only to simple dual-port and simple quad-port modes. If the read address registers
are cleared, M20K will read the memory content at address 0.
If your RAM does not use output registers, the RAM outputs are cleared using the
latch asynchronous clear (aclr). The (aclr) signal is generated at any time. The
internal logic extends the clear pulse until the next rising edge of the output clock.
When the aclr signal asserts, the outputs are cleared and stay cleared until the next
read cycle.
For the synchronous clear (sclr) signal, the RAM outputs are cleared at the next
rising edge of the output clock when the (sclr) signal is asserted. The outputs will
stay cleared until the next read cycle.
Note: Both aclr and sclr signals must be used separately for each RAM configuration.
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Figure 5. Behavior of Asynchronous Clear and Synchronous Clear in Registered Mode
R1 R2
RD1 RD2 0 RD4 RD5
R3 R4 R5 R6
RD1 0RD2 RD4 RD5
clk
asynclr
regdout
synclr
regdout
stay cleared until
next read cycle
cleared by asynclr when
asynclr signal asserts
stay cleared until
next read cycle
cleared by synclr at the
next rising edge of clk
when synclr signal asserts
Registered
Figure 6. Behavior for Asynchronous Clear and Synchronous Clear in Unregistered
Mode
R1 R2
RD1 RD2 0 RD5 RD6
R3 R4 R5 R6
0 RD5 RD6
clk
asynclr
unregdout
synclr
stay cleared until
next read cycle
cleared by asynclr when
asynclr signal asserts
stay cleared until
next read cycle
cleared by synclr at the
next rising edge of clk
when synclr signal asserts
Unregistered
unregdout
RD3
RD1 RD2 RD3
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Figure 7. Behavior When Asynchronous Clear is Used on Read Address Register in
Registered and Unregistered Modes
R1 R2
RD1 RD2 RD0 RD5
R3 R4 R5 R6
clk
asynclr
regdout
Output stays as
data at address 0
until this clock cycle
Output is data at
address 0
Output stays as
data at address 0
until this clock cycle
Output is data at
address 0
Registered/Unregistered
unregdout RD1 RD2 RD0 RD5 RD6
2.4. Memory Blocks Error Correction Code Support
ECC detects and corrects data errors at the output of the memory.
Only M20K blocks and eSRAM blocks support the ECC feature.
If you engage the ECC feature, you cannot use the following features:
• Byte enable
• Coherent read
• Mixed data width
M20K Blocks
For M20K blocks, ECC performs single-error correction, double-adjacent-error
correction, and triple-adjacent-error correction in a 32-bit word. However, ECC cannot
guarantee detection or correction of non-adjacent two-bit or more errors.
The M20K blocks have built-in support for ECC when in ×32-wide simple dual-port
mode.
• When you engage the ECC feature, the M20K runs slower than the non-ECC
simple dual-port mode. However, you can enable optional ECC pipeline registers
before the output decoder to achieve higher performance compared to non-
pipeline ECC mode at the expense of one-cycle latency.
•Two ECC status flag signals—e (error) and ue (uncorrectable error) indicate the
M20K ECC status. The status flags are part of the regular outputs from the
memory block.
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eSRAM Blocks
For eSRAM blocks, ECC performs single-error correction and double-error detection in
a 64-bit word.
The eSRAM blocks have built-in support for ECC when in ×64-wide simple dual-port
mode.
•Two ECC status flag signals—p{0..3}_eccflags[1] (error corrected) and
p{0..3}_eccflags[0] (error detected) indicate the eSRAM ECC status.
2.4.1. Parity Bit
The following describes the parity bit support for M20K blocks:
• 8 parity bits are generated through the ECC encoder based on 32-bit input data
width, resulting in up to a total of 40 bits of data width.
• You can inject and flip the parity bits by using the ECC parity flip feature.
2.4.2. ECC Parity Flip
The ECC parity flip feature dynamically flips the parity value generated in the encoder
of M20K blocks to observe the ECC behavior through simulation.
When the ECC Encoder Bypass (eccencbypass) port is high, the built-in ECC encoder
values are XOR-ed with the 8 parity bits through the parity ports to generate a new
set of encoder value. When the ECC Encoder Bypass port is low, the encoder
generates the parity bits according to the data input during a write process.
The following table shows an example to construct an 8-bit data width for the parity
port.
Table 5. Example of Setting the 8-Bit Parity Ports
Parity Bit Sequence ECC Feature Is the ECC Decoder able to
Recognize and Correct the
Data Bit?
00000001 Single-error correction Yes
00000011 Double-adjacent-error correction Yes
00000111 Triple-adjacent-error correction Yes
00000101 Triple-adjacent-error correction Yes
00010011 Non-adjacent double/triple correction/detection No guarantee
2.4.3. ECC Read-During-Write Behavior
For M20K blocks, you can select either Old Data or Don't Care output mode. By
default, the mixed port read-during-write mode is set to Don't Care. When the mixed
port read-during-write is set as Don't Care, both RAM data output and eccstatus will
be 'X'. However, if the mixed port read-during-write mode is set as Old Data, the RAM
data output will be the old data and the ECC status will be a deterministic value.
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2.4.4. Error Correction Code Truth Table
Table 6. ECC Status Flags Truth Table for M20K
Eccstatus[1]e Eccstatus[0]ue Status
0 0 No error.
0 1 Illegal/Invalid.
1 0 A correctable error occurred and the
error has been corrected at the
outputs; however, the memory array
has not been updated.
1 1 An uncorrectable error occurs and
uncorrectable data appears at the
outputs.
Figure 8. ECC Block Diagram for M20K Memory
Input
Register
32 Memory
Array
ECC
Decoder
Status Flag
Generation
Output
Register
40 40
40
40
ECC
Encoder 8
32
Optional
Pipeline
Register
32
8
2
ECC
Parity
Flip
8
XOR
(ecc_pipeline_stage_enabled == “TRUE”) ? 1:0
0
1
8
Table 7. ECC Status Flags Truth Table for eSRAM
p{0..3}_eccflags[0] p{0..3}_eccflags[1] Status
0 0 No error.
0 1 Illegal.
1 0 An error is detected but uncorrectable.
The uncorrectable data appears at the
outputs.
1 1 An error is detected and correctable.
The error has been corrected at the
outputs. The corrected data appears at
the outputs but the memory array is
not updated.
2.5. Intel Agilex Embedded Memory Clocking Modes
Each Intel Agilex embedded memory operation mode has supporting clocking modes.
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Table 8. Memory Blocks Clocking Modes Supported for Each Memory Mode
Clocking Mode Memory Mode
Single-Port Simple
Dual-Port
True Dual-Port Simple
Quad-Port
Single-Port
ROM
Dual-Port ROM
Single clock
mode
Yes Yes Yes Yes Yes Yes
Read/write
clock mode
N/A Yes N/A (1)N/A N/A N/A
Input/output
clock mode
Yes Yes Yes N/A (2)Yes Yes
Note: The clock enable signals are supported for write address, byte enable, and data input
registers on MLAB blocks.
2.5.1. Single Clock Mode
In the single clock mode, a single clock, together with a clock enable, controls all
registers of the embedded memory block.
2.5.2. Read/Write Clock Mode
In the read/write clock mode, a separate clock is available for each read and write
port.
• A read clock controls the data-output, read-address, and read-enable registers.
• A write clock controls the data-input, write-address, write-enable, and byte enable
registers.
2.5.3. Input/Output Clock Mode
In input/output clock mode, a separate clock is available for each input and output
port.
• An input clock controls all registers related to the data input to the embedded
memory block including data, address, byte enables, read enables, and write
enables.
• An output clock controls the data output registers.
2.5.4. Asynchronous/Synchronous Clears in Clocking Modes
In all clocking modes, asynchronous and synchronous clears are available only for
output latches and output registers.
In all clocking modes, asynchronous clear is available for read address registers on
simple dual-port and simple quad-port modes.
(1) The read/write clock mode is done through emulated true dual-port. For more information
about the emulated true dual-port, refer to the True Dual Port Dual Clock Emulator section.
(2) Both input and output modes share the same clock.
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2.5.5. Output Read Data in Simultaneous Read/Write
If you perform a simultaneous read/write to the same address location using the read/
write clock mode, the output read data is unknown. If you require the output read
data to be a known value, use single-clock or input/output clock mode and select the
appropriate read-during-write behavior.
2.5.6. Independent Clock Enables in Clocking Modes
Independent clock enables are supported in the following clocking modes:
• Read/write clock mode—supported for both read and write clocks.
• Input/output clock mode—supported for the registers of both ports.
To save power, you can control the shutdown of a particular register using the clock
enables.
2.6. Intel Agilex Embedded Memory Configurations
Table 9. Supported Embedded Memory Block Configurations
This table lists the maximum configurations supported for the Intel Agilex embedded memory blocks.
Embedded Memory Block Depth (bits) Programmable Width
MLAB 32 ×16, ×18, or ×20
M20K 512 ×32 or ×40
Note: For simple dual-port only.
1024 ×20
Note: For simple dual-port and true
dual-port.
2048 ×10
Note: For simple dual-port, true dual-
port, and simple quad-port.
eSRAM 2048×42 (3)x72 (3)
2.6.1. Mixed-Width Port Configurations
The mixed-width port configuration is supported only in simple dual-port RAM memory
operation modes.
Note: MLABs do not support mixed-width port configurations.
Table 10. Supported Mixed-width Ratios for Intel Agilex
Operation Mode Mixed-width Ratio
Without Byte Enable With Byte Enable
Simple dual-port 1, 2, 4, 8, 16, and 32 1, 2, and 4
continued...
(3) The eSRAM channel depth and width can be programmably reduced to realize power savings.
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Operation Mode Mixed-width Ratio
Without Byte Enable With Byte Enable
Note: 8, 16, and 32 are
emulated. For emulated
ratio, use the .mif
dimension of the larger
width port.
True dual-port N/A N/A
Simple quad-port N/A N/A
2.7. Force-to-Zero
The Force-to-Zero feature helps improve timing when a RAM memory block selected is
larger than a single memory block. This feature is applicable only for M20K blocks.
For example, if the selected RAM memory block has a memory depth of 4096, the
M20K block, which supports only a maximum memory depth of 2048, will require two
RAMs to be multiplexed together. When you engage with this feature, you can replace
OR gate with multiplexing circuitry at the output of the M20K block when performing
address width stitching. As the MSB of address controls the read enable signal in the
Force-to-Zero mode, the outputs of other memory blocks are forced to zero when the
read enable signal is deasserted. This results the data output being read out from the
output of the selected memory block only.
2.8. Coherent Read Memory
The coherent read memory feature allows you to read out the output data that will be
written into the same memory content in a single clock cycle. In other words, you will
experience the new data (flow through) behavior during the read-during-write
operation. This feature is applicable only for M20K blocks and supported only in single
clock configuration.
If the M20K blocks are configured with coherent read memory feature enabled with
registered output, both latch register and output registers of the M20K blocks are
cleared when asynchronous clear (aclr) or synchronous clear (sclr) is asserted.
This means that you may observe the output of the M20K blocks is cleared for an
extra clock cycle after the clear signal (aclr or sclr) is de-asserted, with a condition
that the M20K blocks does not read when the clear signal (aclr or sclr) is asserted
high.
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Figure 9. Coherent Read Memory Behavior for Intel Agilex Blocks
This figure shows an example of the coherent read memory behavior when the output is registered if the M20K
blocks does not read when the clear signal is asserted high.
rdaddress
wraddress
rden
wren
0000 0001 0002 0003 0004 0008
clk
data
2210C 00003 00000 712BB FB9AA
q
clk_enable
aclr
0000 0001 0002 0009 000A 0005 0006 0007 0008
2210C CCB48 8E088 3FODD F57D5 E697E 712BB FB9AA D86F9
0005 0006 0007
CCB48 8E088
Read data from latch
(Latch was cleared.
Hence, the output is 0)
aclr cleared both
output and latch
Read data from
address 3 (initialized
to data 3)
If you engage the coherent read memory feature, you cannot use the following
configurations:
• Operating modes other than simple dual-port
• Simple dual-port with different port width
• Byte enable
• ECC
• Wide simple dual-port
• Dual clock configuration
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Figure 10. Simplified Block Diagram of Coherent Read Memory Circuitry
writeData
wraddress
wren
rdaddress
rdren
Notes:
1. N = (rden_reg && wren && (rdaddress_reg == wraddress)) ? 1 : 0.
2. C = (rden_reg && wren_reg && (rdaddress_reg == wraddress_reg)) ? 1 : 0.
3. FWD2 = (forwarding_stage2) ? 1 : 0.
Memory
FWD2
OutReg
C || N
C && FWD2
M20K Block
wraddress_reg
wren_reg
rdaddress_reg
rden_reg
C! = N
1
0
1
0
1
0
1
0
Q output
Figure 11. Coherent Read Memory Behavior for Unregistered Output
This figure shows the waveform of the coherent read memory when the output is unregistered.
rdaddress
wraddress
rden
wren
0000 0001 0002 0003 0001 0005 0008 0009
clk
data
00000 F287D 22D76 75EA6 22D76 00000 1EDE0 1A4B4
q
clk_enable
aclr
0000 0001 0002 0009 000A 0005 0006 0007 0008 0009
Notes:
1. Data (data) forwarded to output data (q) at the same clock cycle.
2. rden is low, qholds the forwarded value.
3. One clock cycle is needed to recover the qafter clear (aclr)
for the unregistered condition.
(2)
(1)
F287D 22D76 75EA6 B3D1B 7A81B 1EDE0 F6EDE 16AD6 1A4B4 4AAD4
(3)
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Figure 12. Coherent Read Memory Behavior for Registered Output
This figure shows the waveform of the coherent read memory when the output is registered.
rdaddress
wraddress
rden
wren
0000 0001 0002 0003 0001 0008 0009 0005
clk
data
00000 F287D 22D76 00000 XXXXX 1EDE0
B3D1B
q
clk_enable
aclr
F287D 22D76 75EA6 B3D1B 7A81B 1EDE0 F6EDE 16AD6 1A4B4 4AAD4
0000 0001 0002 000A 0005 0006 0007 0008 0009
Notes:
1. Data (data) forwarded to output data (q) for the next clock cycle.
3. When clear (aclr) is asserted, the M20K block clears q.
4. At this interval, qwill latch from the M20K block, which is a Don’t Care value, due to the
read-during-write operation.
(3)
(2)
(1)
(4)
2. data forwarded to q at the same clock cycle as current wraddress is the same as previous rdaddress.
2.8.1. Forwarding Logic
In pipelining, you can use forwarding logic to perform data forwarding to reduce
instruction cycles.
With coherent read feature and forwarding logic, you can coherently read out the
data, perform operations (arithmetic or logical or both) on top of the data content,
and write the data back to the same memory location within a single clock cycle.
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