Intel Quark SE Series Assembly Instructions

Document Number: 334715-004EN
Intel® Quark™SE Microcontroller C1000
Platform Design Guide
June 2017

Intel® Quark™ SE Microcontroller C1000
Platform Design Guide June 2017
2 Document Number: 334715-004EN
You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products
described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject
matter disclosed herein.
No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.
All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product
specifications and roadmaps.
The products described may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by
visiting: http://www.intel.com/design/literature.htm
Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation.
Learn more at http://www.intel.com/ or from the OEM or retailer.
No computer system can be absolutely secure.
Intel, Quark, and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2017, Intel Corporation. All rights reserved.

Intel® Quark™ SE Microcontroller C1000
June 2017 Platform Design Guide
Document Number: 334715-004EN 3
Contents
1.0 Introduction.................................................................................................................................................8
1.1 Overview................................................................................................................................................................8
1.2 Audience and Purpose ....................................................................................................................................8
1.3 Terminology.........................................................................................................................................................9
1.4 Reference Documents .....................................................................................................................................9
2.0 System Assumptions ...............................................................................................................................10
2.1 General Assumptions.................................................................................................................................... 10
2.1.1 PCB Technology and Stackup................................................................................................ 11
2.1.2 PCB Technology Considerations .......................................................................................... 11
2.2 Backward and Forward Coupling Coefficient Calculation ............................................................ 13
2.3 Feature Set ........................................................................................................................................................ 14
2.4 Pin Mapping ...................................................................................................................................................... 15
3.0 Subsystem Details....................................................................................................................................23
3.1 Design Recommendations.......................................................................................................................... 23
3.2 General Design Guideline Assumptions ............................................................................................... 24
4.0 I2C Interface ...............................................................................................................................................25
4.1 I2C Interfaces Signals .................................................................................................................................... 25
4.2 Interface Routing Guidelines ..................................................................................................................... 25
5.0 Pulse Width Modulation (PWM) ............................................................................................................28
5.1 PWM Signaling................................................................................................................................................. 28
5.2 Functional Operation.................................................................................................................................... 29
6.0 UART ...........................................................................................................................................................31
6.1 Signal Descriptions ........................................................................................................................................ 31
6.2 Features .............................................................................................................................................................. 32
7.0 SPI................................................................................................................................................................34
7.1 Signal Descriptions ........................................................................................................................................ 34
7.2 Features .............................................................................................................................................................. 37
8.0 Clocking......................................................................................................................................................39
8.1 Signal Descriptions ........................................................................................................................................ 39
8.2 Features .............................................................................................................................................................. 41
9.0 General Purpose I/O (GPIO) ...................................................................................................................42
9.1 Signal Descriptions ........................................................................................................................................ 42
9.2 Features .............................................................................................................................................................. 43
10.0 JTAG............................................................................................................................................................44
10.1 Signal Descriptions ........................................................................................................................................ 44

Intel® Quark™ SE Microcontroller C1000
Platform Design Guide June 2017
4 Document Number: 334715-004EN
10.2 Features .............................................................................................................................................................. 45
11.0 Analog-to-Digital Converter (ADC).......................................................................................................46
11.1 Signal Descriptions ........................................................................................................................................ 46
11.2 Features .............................................................................................................................................................. 46
12.0 USB ..............................................................................................................................................................48
12.1 Signal Descriptions ........................................................................................................................................ 48
12.2 Features .............................................................................................................................................................. 49
13.0 Power ..........................................................................................................................................................51
13.1 Configuration for External VR ................................................................................................................... 51
13.2 Configuration for Internal VR .................................................................................................................... 53
14.0 Termination of Unused Pins ..................................................................................................................56
14.1 Guidelines for Terminating Unused Pins ............................................................................................. 56
14.2 Termination of Unused Pins for Intel® Quark™ SE Microcontroller C1000 ........................... 56
14.2.1 GPIO Pin Termination ................................................................................................................ 56
14.2.2 Sensor Subsystem SPI Pin Termination ............................................................................ 57
14.2.3 I2C Pin Termination..................................................................................................................... 58
14.2.4 UART Pin Termination ............................................................................................................... 59
14.2.5 JTAG Pin Termination................................................................................................................ 59
14.2.6 USB Pin Termination .................................................................................................................. 60
14.2.7 Pin Termination Summary....................................................................................................... 60
Figures
Figure 1. Intel® Quark™ SE Microcontroller C1000 CRB Block Diagram .................................................... 10
Figure 2. SoC Block Diagram......................................................................................................................................... 11
Figure 3. Single-Ended Microstrip Diagram ........................................................................................................... 12
Figure 4. Differential-Microstrip Diagram ............................................................................................................... 12
Figure 5. Backward Coupling Coefficient ................................................................................................................ 13
Figure 6. Forward Coupling Coefficient ................................................................................................................... 14
Figure 7. Single-Ended Kb Diagram........................................................................................................................... 14
Figure 8. Differential Kb Diagram ............................................................................................................................... 14
Figure 9. SoC Interfaces .................................................................................................................................................. 16
Figure 10. I2C Point-to-Point Topology...................................................................................................................... 26
Figure 11. Duty Cycle of 20%.......................................................................................................................................... 29
Figure 12. Duty Cycle of 50%.......................................................................................................................................... 29
Figure 13. Duty Cycle of 80%.......................................................................................................................................... 29
Figure 14. UART Point-to-Point Topology................................................................................................................ 31
Figure 15. SPI Point-to-Point Single Flash Topology........................................................................................... 34
Figure 16. SPI Point-to-Point Dual Flash Topology .............................................................................................. 35
Figure 17. SPI_CS Point-to-Point Dual Flash Topology ...................................................................................... 36
Figure 18. RTC Topology................................................................................................................................................... 39

Intel® Quark™ SE Microcontroller C1000
June 2017 Platform Design Guide
Document Number: 334715-004EN 5
Figure 19. GPIO Pin Routing Topology ....................................................................................................................... 42
Figure 20. JTAG Topology................................................................................................................................................ 44
Figure 21. Analog Shielding Requirement................................................................................................................. 46
Figure 22. USB Topology .................................................................................................................................................. 48
Figure 23. USB Topology –Block Diagram ............................................................................................................... 48
Figure 24. Configuration for External VR ................................................................................................................... 52
Figure 25. Power Sequence for External Regulator .............................................................................................. 52
Figure 26. Power Timings for External Regulator .................................................................................................. 53
Figure 27. Power Delivered by an Internal 1.8V VR Only ................................................................................... 54
Figure 28. Power Sequence for Internal Regulator ............................................................................................... 55
Figure 29. GPIO Pin Termination Example (External Pull-Down Resistor).................................................. 57
Figure 30. Sensor Subsystem SPI Pin Termination Example............................................................................ 58
Figure 31. I2C Pin Termination Example..................................................................................................................... 58
Figure 32. I2C Pin Termination Example (External Pull-up Resistor) ............................................................. 59
Figure 33. UART Pin Termination Example............................................................................................................... 59
Figure 34. JTAG Pin Termination Example ............................................................................................................... 60
Figure 35. USB Pin Termination Example.................................................................................................................. 60
Tables
Table 1. Terminology.........................................................................................................................................................9
Table 2. Reference Documents .....................................................................................................................................9
Table 3. Stackup Details................................................................................................................................................ 13
Table 4. Alphabetical Ball Listing for BGA package .......................................................................................... 16
Table 5. Good Layout Practices ................................................................................................................................. 24
Table 6. I2C Interface Signals....................................................................................................................................... 25
Table 7. I2C Point-to-Point Platform Routing Guidelines ............................................................................... 26
Table 8. Capacitance Estimates for Calculating Rpu Values ......................................................................... 27
Table 9. PWM Interface Signals ................................................................................................................................. 28
Table 10. PWM Timing...................................................................................................................................................... 29
Table 11. Timer Period ..................................................................................................................................................... 30
Table 12. UART Signals .................................................................................................................................................... 31
Table 13. UART Point-to-Point Topology Platform Routing Guidelines .................................................... 32
Table 14. SPI Signals ......................................................................................................................................................... 34
Table 15. SPI Single Flash Platform Routing Guidelines ................................................................................... 34
Table 16. SPI Dual Flash Platform Routing Guidelines....................................................................................... 36
Table 17. SPI_CS Dual Flash Platform Routing Guidelines............................................................................... 37
Table 18. Clocking Signals .............................................................................................................................................. 39
Table 19. RTC Signals........................................................................................................................................................ 40
Table 20. RTC Point-to-Point Topology Platform Routing Guidelines ....................................................... 40
Table 21. 32Mhz Crystal Oscillator specification.................................................................................................. 40
Table 22. 32Khz Crystal Oscillator specification................................................................................................... 41
Table 23. GPIO Signals ..................................................................................................................................................... 42
Table 24. GPIO Pin Routing Guidelines..................................................................................................................... 43

Intel® Quark™ SE Microcontroller C1000
Platform Design Guide June 2017
6 Document Number: 334715-004EN
Table 25. Generic Routing Requirements................................................................................................................. 44
Table 26. ADC Signals....................................................................................................................................................... 46
Table 27. USB Signals ....................................................................................................................................................... 48
Table 28. USB Routing Requirements........................................................................................................................ 49
Table 29. Timing Parameters for External Regulator.......................................................................................... 53
Table 30. Recommended Termination Methods for Unused Pins................................................................ 61

Intel® Quark™ SE Microcontroller C1000
June 2017 Platform Design Guide
Document Number: 334715-004EN 7
Revision History
Date
Revision
Description
June 2017
004
Corrections in Table 14. SPI Signals.
Added Chapter 14.0, describing optimal termination of unused pins.
February 2017
003
Corrections in external power supply section.
Added reference to HOST_1P8 voltage rail.
November 2016
002
Minor corrections to signal names.
Power delivery and clocking sections updated.
July 2016
001
Initial release.
§

Introduction
Intel® Quark™ SE Microcontroller C1000
Platform Design Guide June 2017
8 Document Number: 334715-004EN
1.0 Introduction
1.1 Overview
This design guide provides motherboard implementation recommendations for the
Intel® Quark™ SE microcontroller C1000 platform, based on the Intel® Quark™ SE
microcontroller processor. This document includes design guidelines for Intel®
Quark™ SE microcontroller platforms and the hardware integration aspects that
must be considered when designing a platform.
This design guide has been developed to ensure maximum flexibility for board
designers while reducing the risk of board-related issues. Design recommendations
are based on Intel's simulations and lab experience and are strongly recommended,
if not necessary, to meet the timing and signal quality specifications. Design
recommendations are based on the reference platforms designed by Intel. They
should be used as an example but may not be applicable to particular designs.
Note: The guidelines recommended in this document are based on experience,
simulation, and preliminary validation work done at Intel while developing the Intel®
Quark™ SE microcontroller C1000 processor-based platform. This work is ongoing,
and these recommendations are subject to change.
Caution: If the guidelines listed in this document are not followed, it is very important that
the designers perform thorough signal integrity and timing simulations. Even when
following these guidelines, Intel recommends the critical signals to be simulated to
ensure proper signal integrity and flight time. Any deviation from the guidelines
should be simulated.
Metric units are used in some sections in addition to the standard use of U.S.
customary system of units (USCS). If there is a discrepancy between the metric and
USCS units, assume the USCS unit is most accurate. The conversion factor used is
1 inch (1000 mils) = 25.4 mm.
1.2 Audience and Purpose
The Intel® Quark™ SE microcontroller C1000 is a highly integrated, ultra-low-power
part designed to enable innovative solutions with long battery life for
fitness/health/wellness monitors, smart watches, and so on.
This document is intended to aid platform hardware designers in system
implementation and reference design reuse through the following:
Documenting the hardware implementation of specific form factor solutions
based on the Intel® Quark™ SE microcontroller C1000 platform
Providing details such as block diagrams, which illustrate connectivity, system
level considerations, options, and design guidelines

Introduction
Intel® Quark™ SE Microcontroller C1000
June 2017 Platform Design Guide
Document Number: 334715-004EN 9
Describing the theory of operation or principles considered in deriving a design
guideline
1.3 Terminology
Table 1. Terminology
Term
Description
ADC
Analog-to-Digital Converter
CRB
Customer Reference Board
GPIO
General Purpose Input/Output
I2C
Inter-Integrated Circuit
I2S
Inter-IC Sound
JTAG
Joint Test Action Group
OSC
Oscillator
PWM
Pulse Width Modulation
RTC
Real-Time Clock
SIO
Serial I/O
SoC
System on Chip
SPI
Serial Peripheral Interface
UART
Universal Asynchronous Receiver Transmitter
VR
Voltage Regulator
XTAL
Crystal
1.4 Reference Documents
Table 2. Reference Documents
Document
Document
No./Location
Intel® Quark™SE Microcontroller C1000 Datasheet
334712
Intel® Quark™ SE Microcontroller C1000 Power Sequencing
Considerations Application Note
335277
§

System Assumptions
Intel® Quark™ SE Microcontroller C1000
Platform Design Guide June 2017
10 Document Number: 334715-004EN
2.0 System Assumptions
2.1 General Assumptions
This section covers general assumptions about the Intel® Quark™ SE SoC
microcontroller and Intel® Quark™ SE microcontroller C1000 Customer Reference
Board (CRB) system topology and interface connectivity.
The Intel® Quark™ SE microcontroller C1000 CRB is used as a baseline reference
example for guidelines.
Figure 1. Intel® Quark™ SE Microcontroller C1000 CRB Block Diagram

System Assumptions
Intel® Quark™ SE Microcontroller C1000
June 2017 Platform Design Guide
Document Number: 334715-004EN 11
Figure 2. SoC Block Diagram
SPI GPIO
ADC
Controller
I2C
AHB Fabric
Multi-Channel
DMA
Controller
JTAG/TAP/
DFx Test
Controller(s)
APB Fabric
WDT RTC
JTAG
Pin Muxing
Digital I/O Pads
Sensor Processor Subsystem
ARC DSP
Core
SAR ADC
USB 1.1 Device
Controller
Interrupts
SRAM
80kB
PERIPH
Comparator HIPs Analog I/O Pads
Flash
192kBx2
OTP
Flash
PWM
(Timer)
I2S + Fifo
Memories
2 x UART
SPI (2 Master & 1
Slave)
I2C (2 Master &
1 Slave)
AHB Bridge
Host Processor
Processor
Core
Local APIC
Interrupts
I/O APIC
System Control
Interface & Registers
System Control SubSystem
VRs/
LDOs
Interrupt
Routing
Wake Event
Routing
OSC
PLL
CRU
PMU
GPIO
DCCM
Memory
Pattern Matching
Engine
2.1.1 PCB Technology and Stackup
The system uses the PCB technology of a standard interconnect, Type 3, 6-layer
board, with no blind or buried vias. The BGA package also supports a standard
interconnect, Type 3, 4-layer PCB design technology. It is important to note that
variations in the stackup of a motherboard, such as changes in the dielectric height,
trace widths, and spacing, can impact the impedance or loss and jitter
characteristics of all interfaces. Such changes may be intentional or may be a result
of variations in the manufacturing process. In either case, they must be properly
considered when designing interconnects. This design guide applies the CRB PCB
stackup and trace width/spacing that is shown in Figure 3.
Note: All routing guidelines in this document are simulated based on the CRB stackup.
2.1.2 PCB Technology Considerations
The typical values, including the design and material tolerances, are centered on a
nominal single line impedance specification of 50𝛺 ± 15% for microstrip. Many
interfaces specify a different nominal single-ended impedance. For more details on
the nominal trace width to meet those impedance targets, refer to the individual
interface section.
Follow these general stackup recommendations:
Microstrip layers are assumed to be built from 1/2oz. foil, plated up nominally
another 1 oz. However, the defined trace thickness range allows for significant
process variance around this nominal.
Dual stripline is assumed to be built from 1 oz. copper, based on the Intel®
Quark™ SE Microcontroller C1000 layout layers 2/3/4/5.

System Assumptions
Intel® Quark™ SE Microcontroller C1000
Platform Design Guide June 2017
12 Document Number: 334715-004EN
All high-speed signals should reference solid planes over the length of their
routing and should not cross plane splits. Ground referencing is preferred.
Reference plane stitching vias must be used in conjunction with high-speed
signal layer transitions that include a reference plane change. Refer to each
signal group section for more specification.
The parameter values for internal and external traces are the final thickness and
width after the motherboard materials are laminated, conductors plated, and
etched. Intel uses these exact values to generate the associated electrical
models for simulation.
Figure 3. Single-Ended Microstrip Diagram
Figure 4. Differential-Microstrip Diagram

System Assumptions
Intel® Quark™ SE Microcontroller C1000
June 2017 Platform Design Guide
Document Number: 334715-004EN 13
Table 3. Stackup Details
2.2 Backward and Forward Coupling Coefficient Calculation
Some designs require a stackup build that is outside of the ranges provided. In this
case, compare the routing electrical characteristics to the Intel recommendation. It
is important to compare the single-ended and differential impedances. However,
crosstalk level, which is governed by trace spacing, is not implied by the impedance
target. In cases where the selected stackup varies from the Intel recommendation,
we recommend calculating and comparing the backward coupling coefficient to
choose proper trace spacing. The coupling coefficient represents the source voltage
percentage that is coupled to victim lines. As shown in Figure 5, Kb is defined as the
backward coupling coefficient. For backward (near-end) crosstalk, inductive and
capacitive coupling are of the same polarity and the noise magnitude is not a
function of trace length. The backward coupling coefficient (Kb) values can be used
to determine trace spacing. For forward (far-end) crosstalk, Kf inductive and
capacitive coupling are of opposite polarity, and the crosstalk magnitude (Vfe) is
proportional to both trace length and edge rate.
Kf is typically a very small value in most practical designs. Therefore, we have not
included the Kf values in the design guide. However, if the value is desired, the
equation for calculating Kf is provided in Figure 6.
Figure 5. Backward Coupling Coefficient

System Assumptions
Intel® Quark™ SE Microcontroller C1000
Platform Design Guide June 2017
14 Document Number: 334715-004EN
Figure 6. Forward Coupling Coefficient
Figure 7. Single-Ended Kb Diagram
Figure 8. Differential Kb Diagram
Breakout topologies are mainly decided by package ballout patterns and pitches.
Similar geometries will be used for various stackups. Refer to the interface sections
for the breakout maximum length allowed and signals not listed in Table 3.
2.3 Feature Set
A device can contain any feature set and capabilities supported on the Intel®
Quark™ SE microcontroller C1000.
The following is a feature set of a sample wearable device used in the Intel® Quark™
SE microcontroller C1000 form factor. Refer to the Intel® Quark™ SE Microcontroller
C1000 Datasheet for the latest features supported on the platform.
The Intel® Quark™ SE microcontroller C1000 has the following features:
Intel® Quark™ SE microcontroller SoC 32 MHz
384 KB Flash Memory (Internal)
8 KB OTP Flash (Internal)
8 KB OTP Data (Internal)
80 KB SRAM (Internal)
2x I2C (Master/Slave)
2x SPI Master Interfaces with support for SPI clock frequencies up to 16 MHz

System Assumptions
Intel® Quark™ SE Microcontroller C1000
June 2017 Platform Design Guide
Document Number: 334715-004EN 15
1x SPI Slave Interface with support for SPI clock frequencies up to 3.2 MHz
2x UART Interfaces supporting baud rates from 300 to 2M
19 ADC/Comparator Inputs
4x PWM Signals
32 GPIOs
Real-time Clock
Watchdog Timer
Brownout protection
The Intel® Quark™ SE microcontroller C1000 CRB has the following features:
Intel® Quark™ SE microcontroller C1000 main expansion options:
“Arduino Uno” like SIL sockets (1.8V and 3.3V IO)
Intel® Quark™ SE microcontroller C1000 on-board components:
Accelerometer, Gyroscope and Temperature sensors
UART/JTAG to USB convert for USB debug port
Other Intel® Quark™ SE microcontroller C1000 connectors:
2x USB 1.1 Device Port –micro Type B
The power sources for this platform are as follows:
External 5V DC input
Li-ion battery (external)
USB power (5V) via debug port
2.4 Pin Mapping
The Intel® Quark™ SE microcontroller C1000 has multiple functional modes, and the
interfaces and ball mapping are described below. Please refer to guides for BIOS
writers to familiarize yourself with the detailed firmware requirements for setting
the particular functions.

System Assumptions
Intel® Quark™ SE Microcontroller C1000
Platform Design Guide June 2017
16 Document Number: 334715-004EN
Figure 9. SoC Interfaces
Table 4. Alphabetical Ball Listing for BGA package
Ball
Assign
Function_0
Function_1
Function_2
Description
A1
VSS
Ground
A2
GPIO[27]
SPI0_M_CS_B[3]
GPIO[27]/SPI0 Master
Chip Select 3
A3
GPIO[21]
SPI0_M_SCK
GPIO[21]/SPI0 Master
Clock
A4
GPIO[18]
I2S_TSCK
GPIO[18]/I2S Transmit
Clock
A5
GPIO[13]
SPI1_M_CS_B[2]
GPIO[13]/SPI1 Master
Chip Select 2
A6
GPIO[10]
SPI1_M_MOSI
GPIO[10]/SPI1 Master
Master-Out Slave-In

System Assumptions
Intel® Quark™ SE Microcontroller C1000
June 2017 Platform Design Guide
Document Number: 334715-004EN 17
Ball
Assign
Function_0
Function_1
Function_2
Description
A7
SPI1_SS_CS_B[1]
SPI1 Sensor Subsystem
Chip Select 1
A8
SPI1_SS_MISO
SPI1 Sensor Subsystem
Master -Out Slave-In
A9
SPI0_SS_CS_B[0]
SPI0 Sensor Subsystem
Chip Select 0
A10
SPI0_SS_MISO
SPI0 Sensor Subsystem
Master-Out Slave-In
A11
I2C0_SS_SDA
I2C0 Sensor Subsystem
Serial Data
A12
VSS
Ground
B1
GPIO_SS[11]
PWM[1]
GPIO Sensor
Subsystem[11]/ PWM[1]
B2
GPIO[26]
SPI0_M_CS_B[2]
GPIO[26]/SPI0 Master
Chip Select 2
B3
GPIO[20]
I2S_TXD
GPIO[22]/I2S transmit
data
B4
GPIO[16]
I2S_RSCK
GPIO[16]/I2S Receive
Clock
B5
GPIO[12]
SPI1_M_CS_B[1]
GPIO[12]/SPI1 Master
Chip Select 1
B6
GPIO[9]
SPI1_M_MISO
GPIO[9]/SPI1 Master
Master-In Slave-Out
B7
SPI1_SS_MOSI
SPI1 Sensor Subsystem
Master-Out Slave-In
B8
SPI1_SS_SCK
SPI1 Sensor Subsystem
Clock
B9
SPI0_SS_CS_B[2]
GPIO[29]
SPI0 Sensor Subsystem
Chip Select 2/GPIO[29]
B10
SPI0_SS_MOSI
SPI0 Sensor Subsystem
Master-In Slave-Out
B11
I2C0_SS_SCL
I2C0 Sensor Subsystem
Serial Clock
B12
I2C0_SDA
I2C0 Serial Data
C1
GPIO_SS[13]
PWM[3]
GPIO Sensor Subsystem
[13]/Pulse Width
Modulation[3]
C2
GPIO[28]
GPIO[28]
C3
GPIO[22]
SPI0_M_MISO
GPIO[22]/SPI0 Master
Master-In Slave-Out
C4
GPIO[19]
I2S_TWS
GPIO[19]/I2S Transmit
Write Select
C5
GPIO[15]
I2S_RXD
GPIO[15]/I2S Receive
C6
GPIO[11]
SPI1_M_CS_B[0]
GPIO[11]/SPI1 Master
Chip Select 0

System Assumptions
Intel® Quark™ SE Microcontroller C1000
Platform Design Guide June 2017
18 Document Number: 334715-004EN
Ball
Assign
Function_0
Function_1
Function_2
Description
C7
SPI1_SS_CS_B[0]
SPI1Sensor Subsystem
Chip Select 0
C8
SPI0_SS_CS_B[3]
GPIO[30]
Chip select 3 for SPI0 on
Sensor Subsystem/
GPIO[30]
C9
SPI0_SS_SCK
SPI0 Sensor Subsystem
Serial Clock
C10
I2C1_SS_SDA
I2C1 Sensor Subsystem
Serial Data
C11
I2C1_SDA
I2C1Serial Data
C12
I2C0_SCL
I2C0 Serial Clock
D1
GPIO_SS[14]
PLT_CLK[0]
GPIO for Sensor
Subsystem[14]/ Platform
Clock 0
D2
GPIO_SS[10]
PWM[0]
GPIO for Sensor
Subsystem[10]/ PWM[0]
D3
GPIO[23]
SPI0_M_MOSI
GPIO[23]/SPI0 Master
Master-Out Slave-In
D4
GPIO[17]
I2S_RWS
GPIO[17]/I2S Receive
Write Select
D5
GPIO[14]
SPI1_M_CS_B[3]
GPIO[14]/SPI1 Master
Chip Select 3
D6
GPIO[8]
SPI1_M_SCK
GPIO[8]/SPI1 Master
Serial Clock
D7
SPI1_SS_CS_B[3]
UART0_RTS_B
SPI1 Sensor Subsystem
Chip Select 3/UART0
Ready to Send
D8
SPI1_SS_CS_B[2]
UART0_CTS_B
SPI1 Chip Select 2 on
Sensor Subsystem/
UART0 Clear to Send
Active low
D9
SPI0_SS_CS_B[1]
SPI0 Sensor Subsystem
Chip Select 1
D10
I2C1_SS_SCL
I2C1 Sensor Subsystem
Serial Clock
D11
I2C1_SCL
I2C1 Serial Clock
D12
GPIO[0]
AIN[0]
SPI_S_CS_B
GPIO[0]/Analog Input
[0]/SPI Slave Chip Select
E1
GPIO_SS[15]
PLT_CLK[1]
GPIO for Sensor
Subsystem[15]/
Platform Clock Output 1
E2
GPIO_SS[12]
PWM[2]
GPIO for Sensor
Subsystem[12]/ PWM[2]
E3
GPIO[25]
SPI0_M_CS_B[1]
GPIO[25]/SPI0 Master
Chip Select 1
E4
GPIO[24]
SPI0_M_CS_B[0]
GPIO[24]/ SPI0 Master
Chip Select 0

System Assumptions
Intel® Quark™ SE Microcontroller C1000
June 2017 Platform Design Guide
Document Number: 334715-004EN 19
Ball
Assign
Function_0
Function_1
Function_2
Description
E5
RST_B
Main reset for SoC
E6
GPIO_AON[5]
Always on GPIO[5]
E7
VSS
Ground
E8
UART0_RXD
AIN[18]
UART0 Receive/Analog
Input[18]
E9
UART0_TXD
GPIO[31]
UART0
Transmit/GPIO[31]
E10
GPIO[1]
AIN[1]
SPI_S_MISO
GPIO[1]/ Analog Input
[1]/SPI Slave Master-In
Slave-Out
E11
GPIO[2]
AIN[2]
SPI_S_SCK
GPIO[2]/Analog Input
[2]/SPI Slave Serial Clock
E12
GPIO[3]
AIN[3]
SPI_S_MOSI
GPIO[3]/Analog
Input[3]/SPI slave
Master-Out Slave-in
F1
GPIO_AON[4]
Always On GPIO [4]
F2
GPIO_AON[3]
Always On GPIO [3]
F3
GPIO_AON[0]
Always On GPIO [0]
F4
GPIO_AON[2]
Always On GPIO [2]
F5
GPIO_AON[1]
Always On GPIO [1]
F6
VCC_IO_AON
Ground for Always On
I/O
F7
VSS
Ground
F8
VSS_RTC
RTC Ground
F9
GPIO[4]
AIN[4]
GPIO[4]/ Analog input[4]
F10
GPIO[5]
AIN[5]
GPIO[5]/Analog input[5]
F11
GPIO_SS[0]
AIN[8]
UART1_CTS
GPIO for Sensor
Subsystem[0]/Analog
In[8]/UART1 Clear to
send
F12
GPIO_SS[1]
AIN[9]
UART1_RTS
GPIO for Sensor
Subsystem[1]/Analog
In[9]/UART1 Ready to
Send
G1
TRST_B
JTAG reset
G2
TCK
JTAG clock
G3
TMS
JTAG master select
G4
TDI
JTAG data in
G5
VCC_HOST_1P8_PG
1.8v from platform to
SoC
G6
VSS_IO_AON
Ground for Always On
I/O
G7
VSS
Ground

System Assumptions
Intel® Quark™ SE Microcontroller C1000
Platform Design Guide June 2017
20 Document Number: 334715-004EN
Ball
Assign
Function_0
Function_1
Function_2
Description
G8
VCC_IO_AON
Input voltage for Always
On I/O
G9
GPIO_SS[2]
AIN[10]
GPIO for Sensor
Subsystem[2]/Analog
input[10]
G10
GPIO_SS[3]
AIN[11]
GPIO for Sensor
Subsystem[3]/Analog
Input [11]
G11
GPIO_SS[4]
AIN[12]
GPIO for Sensor
Subsystem[4]/Analog
Input[12]
G12
GPIO_SS[5]
AIN[13]
GPIO for Sensor
Subsystem[5]/Analog
Input [13]
H1
OSC32K_OUT
H2
OSC32K_IN
H3
TDO
JTAG data out
H4
VCC_AON_1P8
1.8v supply voltage for
Always On counter
H5
VCC_AON_1P8
1.8v supply voltage for
Always On counter
H6
VSS_GNDSENSE_ESR1
Ground for switching
regulator 1
H7
VCC_PLL_1P8
1.8 PLL supply voltage
H8
VSS
Ground
H9
COMP_AREF
Analog reference voltage
H10
VCC_IO_AON
Input voltage for Always
On I/O
H11
GPIO_SS[8]
AIN[16]
UART1_TX
GPIO for Sensor
Subsystem[8]/ Analog-
In[16]/ UART1 Transmit
data
H12
GPIO_SS[9]
AIN[17]
UART1_RX
GPIO for Sensor
Subsystem[9]/
Analog[17]/UART1
Receive Data
J1
VCCOUT_AVD_OPM_2P6
2.6 Output voltage
supply for OPM
J2
VSS_GNDSENSE_ESR2
Ground sense on
switching regulator 2
J3
VSS_AVS_ESR2
Ground for switching
regulator 2
J4
VCC_RTC_1P8
1.8 supply voltage for
RTC
J5
VCC_SRAM_1P8
1.8 SRAM supply voltage