Intel Arria 10 series User manual

Intel® Arria® 10 SoC Development
Kit User Guide
Online Version
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Contents
1. Intel® Arria® 10 SoC Development Kit Overview............................................................. 4
1.1. General Description............................................................................................... 4
1.2. Board Component Blocks........................................................................................ 6
1.3. Recommended Operating Conditions........................................................................ 8
1.4. Handling the Board................................................................................................ 9
2. Getting Started............................................................................................................. 10
2.1. Board Inspection .................................................................................................10
2.2. Installing the Subscription Edition of the Quartus Prime Design Software.....................11
2.2.1. Activating Your License............................................................................. 12
2.3. Installing the Altera SoC Embedded Development Suite (EDS)................................... 12
2.4. Development Kit Installer......................................................................................13
2.5. Installing the USB-Blaster Driver............................................................................13
2.6. SD Card Image with Example Software...................................................................14
3. Development Board Setup.............................................................................................15
3.1. Applying Power to the Board..................................................................................15
3.2. Default Switch and Jumper Settings....................................................................... 16
4. Board Test System........................................................................................................ 20
4.1. Preparing the Board............................................................................................. 21
4.2. Running the Board Test System............................................................................. 22
4.3. Version Selector...................................................................................................22
4.4. Using the Board Test System................................................................................. 24
4.4.1. Using the Configure Menu......................................................................... 24
4.4.2. The System Info Tab................................................................................ 26
4.4.3. The GPIO Tab.......................................................................................... 27
4.4.4. The XCVR Tab..........................................................................................28
4.4.5. The PCIe Tab...........................................................................................30
4.4.6. The FMCA Tab..........................................................................................33
4.4.7. The FMCB Tab..........................................................................................36
4.4.8. The DDR3 Tab......................................................................................... 40
4.4.9. The DDR4 Tab......................................................................................... 42
4.4.10. The EEPROM Tab.................................................................................... 43
4.4.11. The Power Monitor................................................................................. 44
4.4.12. The Clock Control...................................................................................46
5. Board Components........................................................................................................48
5.1. Board Overview................................................................................................... 48
5.2. Featured Device: Arria 10 SoC ..............................................................................51
5.3. MAX V CPLD 5M2210 System Controller.................................................................. 52
5.4. Configuration...................................................................................................... 60
5.4.1. System Controller Configuration.................................................................60
5.4.2. FPGA and I/O MUX CPLD Programming over On-Board USB-Blaster II............. 61
5.4.3. FPGA Programming by HPS....................................................................... 63
5.4.4. FPGA Programming by EPCQ Device........................................................... 63
5.4.5. FPGA Programming over External USB-Blaster............................................. 63
5.5. Status Elements.................................................................................................. 64
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5.6. Setup Elements................................................................................................... 64
5.6.1. Board Settings DIP Switch.........................................................................64
5.6.2. JTAG Chain Control DIP Switch.................................................................. 65
5.6.3. Reference Clock Source Selection............................................................... 67
5.6.4. CPU Reset Push Button............................................................................. 67
5.6.5. Logic Reset Push Button............................................................................67
5.7. General User Input/Output....................................................................................67
5.7.1. Character LCD......................................................................................... 68
5.8. Clock Circuitry.....................................................................................................69
5.8.1. On-Board Oscillators................................................................................ 69
5.9. Components and Interfaces...................................................................................70
5.9.1. PCI Express.............................................................................................70
5.9.2. 10/100/1000 Ethernet (HPS).....................................................................72
5.9.3. 10/100/1000 Ethernet (FPGA)................................................................... 74
5.9.4. FMC....................................................................................................... 75
5.9.5. HPS Shared I/O....................................................................................... 88
5.9.6. USB 2.0 Port (HPS).................................................................................. 90
5.9.7. RS-232 UART (HPS)................................................................................. 90
5.9.8. Real-Time Clock (HPS).............................................................................. 91
5.9.9. SFP+......................................................................................................91
5.9.10. I2C Interface......................................................................................... 92
5.9.11. FPGA General I/O Configuration............................................................... 93
5.9.12. HPS SPIO Interface...............................................................................100
5.10. Memory.......................................................................................................... 105
5.10.1. FPGA External Memory..........................................................................106
5.10.2. HPS External Memory........................................................................... 112
5.10.3. HPS Boot Flash Interface....................................................................... 115
5.10.4. I2C EEPROM.........................................................................................115
5.10.5. Daughtercards..................................................................................... 116
5.11. Board Power Supply..........................................................................................117
5.11.1. Power Distribution System..................................................................... 118
5.11.2. Power Measurement............................................................................. 118
A. Additional Information............................................................................................... 119
A.1. Document Revision History for the Intel Arria 10 SoC Development Kit User Guide......119
A.2. Compliance and Conformity Statements................................................................121
A.2.1. CE EMI Conformity Caution......................................................................121
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1. Intel® Arria® 10 SoC Development Kit Overview
This document describes the hardware features of the Intel® Arria® 10 SoC
development board, including the detailed pin-out and component reference
information required to create custom FPGA designs that interface with all components
of the board.
1.1. General Description
The Arria 10 SoC development board provides a hardware platform for developing and
prototyping low-power, high-performance, and logic-intensive designs using Altera's®
Arria 10 SoC. The board provides a wide range of peripherals and memory interfaces
to facilitate the development of Arria 10 SoC designs.
Figure 1. Arria 10 SoC Block Diagram
Micro-
USB
2.0
On-Board
USB Blaster TM II
& USB Interface
MAX II
HiLO
HPS DC
HILO
FPGA DC
FMCA
V57.1
EPCQ
USB to UART
RS232 UART
Trace
Character
LCD Display
SDI Video
PCI Express
Display Port (TX)
MAX V CPLD
System Controller
SFP + Optical Ports
HPS
Ethernet
FPGA
Ethernet
FMCB
PCIE EP
I/O MAX V CPLD
x2
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products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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Figure 2. Overview of the Development Board Features
Character LCD
Display
SDI Video
J42 FMCA
Voltage
Display Port
J32 FMCB
Voltage
J30 FPGA
Power
Trace x 4
J33 Clock Cleaner
Source Select
On/Off
Switch
Clock Cleaner J58 FPGA
Power Jumper
FPGA
Memory
SFP + Optical Ports FPGA
Ethernet HPS
Ethernet
SMA Ports
HPS
Memory
Boot Memory
Daughtercard
USB
PCI Express x8
Storage Memory
Daughtercard
Warm/Cold
Reset
FMC B Daughtercard
Port
FMC A Daughtercard
Port
USB UART
FPGA HPS_DP[0-3]
Trace x16
12V AC
Adapter
USB Blaster II
JTAG Header
RS232 UART
MAX V CPLD
System Controller
FPGA_PB[0-3]
HPS_PB[0-3]
HPS_LED[0-3]
FPGA_LED[0-3]
SW1
HPS Clock Source Selection Jumper
SW3 JTAG Switch
SMA EXT Refclk
HPS EXT Refclk
Linear
Dongle
Header
SW4
For more information about the Arria 10 SoC device family, refer to the Arria 10 SoC
documentation support page.
Related Information
Arria 10 Documentation
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1.2. Board Component Blocks
The development board features the following major component blocks:
• Arria 10 Soc (10AS066N3F40E2SG) in a 1517-pin FBGA (FineLine Ball-Grid Array)
package
• FPGA configuration circuitry
— Active Serial (AS) x1 or x4 configuration (EPCQ1024L)
— MAX® V CPLD (5M2210ZF256) in a 256-pin FBGA package as the system
controller
— MAX V CPLD (5M2210ZF256) in a 256-pin FBGA package as the I/O multiplier
CPLD
• Clocking circuitry
— SI5338 programmable oscillator
— LMK04828 clock cleaner
— HPS clock options: 25 MHz, 33 MHz, and SMA input (2V5 LVCMOS)
— SI5112 100MHz clock generator for PCIe interface
— SI516 148.5 MHz voltage control oscillator for SDI interface
• Supported Memory
— HPS memory size (HILO card):
• 2GB DDR3 (256Mb x 40 x dual rank)
• 1GB DDR3 (256Mb x 40 x single rank)
• 1GB DDR4 (256Mb x 40 x single rank) - ships with kit
— FPGA memory size (HILO Card):
• 4GB DDR3 (256Mb x72 x dual rank)
• 2GB DDR3 (256Mb x72 x single rank)
• 2GB DDR4 (256Mb x 72 x single rank) - ships with kit
• 16MB QDRV (4Mb x 36)
• 128MB RLDRAM3(16Mb x 72)
— HPS Boot Flash (Flash card):
• NAND flash (x8) : 128MB (MT29F1G08ABBEAH4) - ships with kit
• QSPI flash: 128MB (MT25QU01GBBA8E12-0SIT) - ships with kit
• SD Micro flash card: 4GB (Kingston) - ships with kit
— Optional FPGA File Flash (Flash card):
• NAND flash (x8): 128MB (MT29F1G08ABBEAH4)
• QSPI flash: 128MB (MT25QU01GBBA8E12-0SIT)
• SD Micro flash card: 4GB (Kingston)
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• Communication ports
— HPS Communication ports:
• USB 2.0 port (PHY PN: USB3320C-EZK)
• RGMII 10/100/1000 Ethernet port (PHY PN: KSZ9031RNXCA)
• USB-UART port (FT232R)
• DB-9 RS-232 Port (MAX3221)
• I2C port (I2C1 of shared I/O bit 12 and 13)
— FPGA I/O connections:
• FPGA V57.1 High Pin Count FMC slot
• FPGA Altera Low Pin Count FMC slot
• FMC_PCIe Gen2 x8 EP cable
• FPGA PCIe GEN1/2/3 x8 RC slot
— FPGA Communication ports:
• 2x SGMII Gigabit Ethernet ports (PHY PN: 88E1111-B2-NDC2C000)
• 2x 10Gb/s SFP+ ports
• Display port (DP)
• SDI/SDO video port
• SPI port
• UART port
— FPGA Debug ports:
• 16-bit Trace port (FPGA Trace)
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• General user I/O
— LEDs and displays
• 4x FPGA user LEDs
• 4x HPS user LEDs
• Configuration load LED
• Configuration done LED
• Error LED
• 3x Configuration select LEDs
• 4x On-board USB-Blaster II status LEDs
• 2x FMC interface LEDs
• 2x UART data transmit and receive LEDs
• Power on LED
• Two-line character LCD display
— Push buttons
• CPU cold reset push button and one CPU warm reset push button
• Logic reset push button
• Program select push button
• Program configuration push button
• 4x FPGA user push buttons
• 4x HPS user push buttons
• External interrupt push button
— DIP Switches
• JTAG chain control DIP switch
• Board settings DIP switch
• FPGA configuration mode DIP switch
• General user DIP switch
— Power supply
• 12V DC Input
— Mechanical
• 7.175" x 9.3" rectangular form factor
1.3. Recommended Operating Conditions
• Recommended ambient operating temperature range: 0C to 45C
• Maximum ICC load current: 36A
• Maximum ICC load transient percentage: 30%
• FPGA maximum power supported by the supplied heatsink/fan: 40W
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1.4. Handling the Board
When handling the board, it is important to observe static discharge precautions.
Caution: Without proper anti-static handling, the board can be damaged. Therefore, use anti-
static handling precautions when touching the board.
Caution: This development kit should not be operated in a Vibration Environment.
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2. Getting Started
2.1. Board Inspection
To inspect each board, perform these steps:
1. Place the board on an anti-static surface and inspect it to ensure that it has not
been damaged during shipment.
Caution: Without proper anti-static handling, you can damage the board.
2. Verify that all components on the boards appear in place and intact.
For more information about power consumption and thermal modeling, refer to
AN358: Thermal Management for FPGAs.
Table 1. Arria 10 SoC Development Kit Contents
Item Quantity
Arria 10 SoC Development Board 1
USB Cable Mini 2
USB Cable Micro 1
Ethernet Cable 1
FMC Loopback Card 1
MicroSD Daughtercard 1
Quad SPI Daughtercard 1
NAND Daughtercard 1
DDR4 HILO Memory Card 2
Quick Start Guide 1
Related Information
AN358: Thermal Management for FPGAs
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specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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2.2. Installing the Subscription Edition of the Quartus Prime Design
Software
The Quartus® Prime Pro Edition software provides the necessary tools used for
developing hardware and software for Altera devices.
Included in the Quartus Prime Pro Edition software are the Quartus Prime software,
the Nios II EDS, and the MegaCore IP Library. To install the Altera development tools,
download the Quartus Prime Pro Edition Software from the Quartus Prime Pro Edition
page in the Download Center of the Altera website.
Related Information
Quartus Prime Software page
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2.2.1. Activating Your License
Purchasing this kit entitles you to a one-year license for the Development Kit Edition
(DKE) of the Quartus Prime software. After the year, your DKE license will no longer
be valid and you will not be permitted to use this version of the Quartus Prime
software. To continue using the Quartus Prime software, you should purchase a
subscription to Quartus Prime Pro or Standard Edition.
Before using the Quartus Prime software, you must activate your license, identify
specific users and computers, and obtain and install a license file. If you already have
a licensed version of the subscription edition, you can use that license file with this kit.
If not, follow these steps:
1. Log on at the myAltera Account Sign In web page, and click Sign In.
2. On the myAltera Home web page, click the Self-Service Licensing Center link.
3. Locate the serial number printed on the side of the development kit box below the
bottom bar code. The number consists of alphanumeric characters and does not
contain hyphens.
4. On the Self-Service Licensing Center web page, click the Find it with your License
Activation Code link.
5. In the Find/Activate Products dialog box, enter your development kit serial
number and click Search.
6. When your product appears, turn on the check box next to the product name.
7. Click Activate Selected Products, and click Close.
8. When licensing is complete, Altera emails a license.dat file to you. Store the
file on your computer and use the License Setup page of the Options dialog box
in the Quartus Prime software to enable the software.
Related Information
•Altera Software Installation and Licensing
•myAltera Account Sign In web page
2.3. Installing the Altera SoC Embedded Development Suite (EDS)
The Altera SoC EDS is a comprehensive tool suite for embedded software development
on Altera SoC devices. It contains development tools, utility programs, run-time
software, and application examples to expedite firmware and application software of
SoC embedded systems.
As a part of the Altera SoC EDS, the ARM DS-5 Altera Edition Toolkit provides a
comprehensive set of embedded development tools for Altera SoCs.
For more information, refer to the ARM Development Studio 5 (DS-5) Altera Edition
Toolkit.
For the steps to install the SoC EDS Tool Suite, refer to the Altera SoC Embedded
Design Suite User Guide.
Related Information
•ARM Development Studio 5 (DS-5) Altera Edition Toolkit
•Altera SoC Embedded Design Suite User Guide
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2.4. Development Kit Installer
The development kit installer is an installable archive of supporting documentation. It
does not include the software or documentation for the Quartus Prime design
software, nor does it include the SoC EDS software development tools.
1. Download the Arria 10 FPGA Development Kit installer from the Arria 10 FPGA
Development Kit page of the Altera website. Alternatively, you can request a
development kit DVD from the Altera Kit Installations DVD Request Form page of
the Altera website.
2. Run the Arria 10 FPGA Development Kit installer.
3. Follow the on-screen instructions to complete the installation process. Be sure that
the installation directory you choose is in the same relative location to the Quartus
Prime software installation.
The installation program creates the development kit directory structure shown in
the following figure.
Figure 3. Installed Development Kit Directory Structure
<install dir>
documents
board_design_files
The default Windows installation directory is C:\altera\<version>\.
examples
factory_recovery
demos
kits
<device name>
Table 2. Installed Directory Contents
Directory Name Description of Contents
board_design_files Contains schematic, layout, assembly, and bill of material board design files.
Use these files as a starting point for a new prototype board design.
demos Contains demonstration applications when available.
documents Contains the documentation.
examples Contains the sample design files for this kit.
factory_recovery Contains the original data programmed onto the board before shipment. Use
this data to restore the board with its original factory contents.
2.5. Installing the USB-Blaster Driver
The development board includes integrated USB-Blaster circuitry for FPGA
programming. However, for the host computer and board to communicate, you must
install the on-board USB-Blaster II driver on the host computer.
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Installation instructions for the on-board USB-Blaster II driver for your operating
system are available on the Altera website. On the Altera Programming Cable Driver
Information page of the Altera website, locate the table entry for your configuration
and click the link to access the instructions.
The on-board USB Blaster II circuit defaults to 24M and can be unstable depending on
the bus loading or HSMC cards installed. It is recommended to change the speed down
to 16M for better stability.
From a Nios® II Command Shell, type the following
jtagconfig
Note: returns the device lists of all the USB cables
jtagconfig --getparam <cable> Jtagclock
Note: returns current setting
jtagconfig --setparam <cable> JtagClock 16M
Note: sets to 16M (recommended)
Attention: <cable> is the index of the USB cables and it starts with 1.
Attention: This setting is non-volatile and may need to be done if you power down and unplug
your board and then power it back up and plug it in again.
USB-Blaster II Supported Rates:
• 24 MHz
• 16 MHz
• 6 MHz
• 24/n MHz (between 10 KHz and 6 MHz, where n represents an integer value.)
Related Information
Altera Programming Cable Driver Information
2.6. SD Card Image with Example Software
The Arria 10 GSRD (Golden System Reference Design) page on Rocketboards.org has
instructions to create an SD card image.
Related Information
GSRD User Manual
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3. Development Board Setup
This section describes how to apply power to the board and provides default switch
and jumper settings.
3.1. Applying Power to the Board
This development kit ships with its board switches preconfigured to support the design
examples in the kit.
If you suspect that your board might not be currently configured with the default
settings, follow the instructions in the Default Switch and Jumper Settings section of
this chapter.
1. Power up the development board by using the included power supply.
Caution: Use only the supplied power supply. Power regulation circuitry on the
board can be damaged by power supplies with greater voltage, and a
lower-rated power supply may not be able to provide enough power for
the board.
2. When configuration is complete, the configuration done green LED (D18)
illuminates, signaling that the Arria 10 SoC device is configured successfully.
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specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
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3.2. Default Switch and Jumper Settings
This topic shows you how to restore the default factory settings and explains their
functions.
Caution: Do not install or remove jumpers (shunts) while the development board is powered
on.
Figure 4. Default Switch and Jumper Settings
Note: The Switch position is represented by the black box.
To restore the switches to their factory default settings, perform these steps:
1. Set the DIP switch bank (SW1) to match "SW1 DIP Switch Settings" table and the
"Default Switch and Jumper Settings" figure.
Note: In the following table, ON indicates the switch is to the upper position
according to the board orientation as shown in the "Default Switch and
Jumper Settings" figure.
Table 3. SW1 Factory Default Settings
Switch Bit Name Bit Function Default Position
1 I2C flag Switch 1.1 has the following options:
• ON (0) = System MAX V is the I2C master
• OFF (1) = HPS is the I2C master
OFF
2 DC_POWER_CTRL Switch 1.2 has the following options:
• ON (0) = Power off PCIE slot when it is present
• OFF (1) = Power up PCIE directly
OFF
3 factory_load Switch 1.3 has the following options:
• ON (0) = Load user design from flash at power up
• OFF (1) = Load factory design from flash at power up
OFF
4 security_mode Resvered OFF
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Table 4. SW4 Switch Settings
Switch Bit Name Bit Function Default Position
1 Reserved Reserved OFF
2 MSEL0 Switch 4.2 has the following options:
• ON (Up) = MSEL0 is 1
• OFF (Down) = MSEL0 is 0
OFF
3 MSEL1 Switch 4.3 has the following options:
• ON (Up) = MSEL1 is 1
• OFF (Down) = MSEL1 is 0
OFF
4 MSEL2 Switch 4.4 has the following options:
• ON (Up) = MSEL2 is 1
• OFF (Down) = MSEL2 is 0
OFF
Table 5. MSEL Settings for each Configuration Scheme of Arria 10 SoC Devices
Configuration Vccpgm (V) Power-On Reset (POR delay) Valid MSEL [2:0]
JTAG-based configuration - - Use any valid MSEL pin
settings below
AS-Active Serial (x1 and x4) 1.8 Fast 010
Standard 011
PS-Passive Serial 1.2/1.5/1.8 Fast 000
Standard 001
2. Set the DIP switch bank (SW3) to match the following tables:
Table 6. SW3 Factory Default Settings
Switch Board Label Function Default Position
1 Arria 10 ON- Arria 10 JTAG Bypass
OFF- Arria 10 JTAG Enable
OFF
2 IO MAX V ON- MAX V JTAG Bypass
OFF- MAX V JTAG Enable
OFF
3 FMCA ON- FMCA JTAG Bypass
OFF- FMCA JTAG Enable
ON
4 FMCB ON- FMCB JTAG Bypass
OFF- FMCB JTAG Enable
ON
5 PCIe ON- PCIe JTAG Bypass
OFF- PCIe JTAG Enable
ON
6 MSTR0 On-Board USB Blaster II JTAG Master OFF
7 MSTR1 On-Board USB Blaster II JTAG Master OFF
8 MSTR2 On-Board USB Blaster II JTAG Master OFF
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3. Set the following jumper blocks to match the table below:
Table 7. Default Jumper Settings
Board
Reference
Board Label Description Default Position
J16, J17 OSC2_CLK_SEL • 00 (SHORT, SHORT): Selects the on-board 25MHz
clock
• 01 (SHORT, OPEN): Selects SMA clock which
connected to J15
• 10 (OPEN, SHORT): Selects the on-board 33MHz
clock
• 11 (OPEN, OPEN): none
SHORT, SHORT
J30 HPS Core Voltage • SHORT: HPS core 0.95 V
• OPEN: HPS core 0.9 V
SHORT
J32 Voltage of FMCBVADJ • No SHORT: 1.1 V
• SHORT 1 and 2: 1.2 V
• SHORT 3 and 4: 1.25 V
• SHORT 5 and 6: 1.35 V
• SHORT 7 and 8: 1.5 V
• SHORT 9 and 10: 1.8 V
SHORT 9 and 10
J42 Voltage of FMCAVADJ • No SHORT: 1.1 V
• SHORT 1 and 2: 1.1 V
• SHORT 3 and 4: 1.2 V
• SHORT 5 and 6: 1.35 V
• SHORT 7 and 8: 1.5 V
• SHORT 9 and 10: 1.8 V
SHORT 9 and 10
Table 8. Default Jumper BSEL Settings for Micro-SD Daughtercard
Board Reference Description Default BSEL Value = 0x4 Default Position
J3 BSEL0 0 SHORT left 2 pins
J4 BSEL1 0 SHORT upper 2 pins(1)
J5 BSEL2 1 SHORT upper 2 pins(1)
(1) The directions of these pins are in reference to the board arrangement as in the "Default
Switch and Jumper Settings" figure.
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Related Information
Board Settings DIP Switch on page 64
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4. Board Test System
This kit includes an application called the Board Test System (BTS). The BTS is an
easy-to-use interface to alter functional settings of the FPGA portion of the SoC. You
can use the BTS to test board components, modify functional parameters, observe
performance, and measure power usage.
Figure 5. Board Test System GUI
You can use the BTS to test board components, modify functional parameters, observe
performance, and measure power usage. While using the BTS, you reconfigure the
FPGA several times with test designs specific to the functionality you are testing.
Several designs are provided to test the major board features. Each design provides
data for one or more tabs in the application. The Configure menu identifies the
appropriate design to download to the FPGA for each tab.
After successful FPGA configuration, the appropriate tab appears that allows you to
exercise the related board features. Highlights appear in the board picture around the
corresponding components.
683227 | 2023.07.12
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