
Quick Start Guide | Intel Arria 10 GX Signal Integrity Development Kit
Using the Transceiver Signal Integrity
Demonstration
Figure 1. Directory Structure
Step 3. Use the Board Update Portal to update your board
and load the Transceiver Signal Integrity Demonstration
The Board Update Portal allows you to download new FPGA
congurationstothe“user”portionoftheboard’sash
memory. If you cannot connect to the Board Update Portal,
refer to the kit’s user guide for other options to update the
ashmemory.
Toupdatetheuserportionofashmemoryonyourboard,
follow these steps:
1. Type the IP address shown on the board’s LCD into your
PC’s web browser to display the Board Update Portal
web page.
2. IntheHardwareFileNameeld,specifythe.ashle
(<installation directory>\kits\arria10GX_10ax115sf45_
si\examples\board_test_system\qts_sma_amphenol\
bts_sma_amphenol.ash) that you downloaded from
the Intel website. Because the design does not have a
softwarecomponent,leavetheSoftwareFileNameeld
blank.
3. Click Upload.
4. ReconguretheFPGAwiththenewlesbychanging
SW3 position 2 back to the close position,then
repowering your board or pushing MAX_RESETn (S11) to
reconguretheFPGA.
The demonstration design now runs in the FPGA.
You can also use the Board Update Portal to upload your
custom designs. The kit’s user guide describes how to
prepare your designs for use with the Board Update Portal.
Files are installed in the following directory structure:
Step 2. Install the development kit software
Install the latest development kit software tools from
www.intel.com/content/www/us/en/products/program-
mable/fpga.html and follow the on-screen instructions to
complete the installation.
The Transceiver Signal Integrity Demonstration consists of
a Java-based GUI and an FPGA design. After updating your
board as described in Step 3, your board’s FPGA contains
the Transceiver Signal Integrity Demonstration design,
which communicates with the GUI through the On-Board
Intel FPGA Download Cable II circuitry.
To run the demonstration, follow these steps:
1. Connect the Intel FPGA Download Cable II type A to B
cable from your PC to the board.
2. If the Intel FPGA Download Cable II driver is not installed
on your PC, install the driver using the instructions in the
user guide.
3. Connect SMA cables from one or more channels on the
board to an oscilloscope capable of displaying the data
rates you wish to observe.
4. Make sure SW3 position 2 is set to close position (User
Hardware #1) and power up the board
5.LaunchtheBoardTestSystem.exele,locatedat
<installation directory>\kits\arria10GX_10ax115sf45_
si\examples\board_test_system. For optimal viewing,
your screen resolution must be 1024x768 or greater.
6. Select SMA port and desired Data Type, and then click
“Start” to run the test on the activated XCVR #2
tab (If XCVR #2 is not activated automatically, please
manuallycongureXCVR#2designfromthe
conguremenu)
7. Observe the resulting eye diagram on the oscilloscope
and monitor the link statistics shown on the
screen.
For information on bit error rate (BER) calculation,
equalization settings, and other details regarding this
demonstration, refer to the user guide. Visit the Transceiver
Signal Integrity Development Kit page (www.intel.com/
content/www/us/en/programmable/products/boards_
and_kits/dev-kits/altera/kit-a10-gx-si.html) for the latest
documentation and designs.