Intel Arria 10 gx User manual

Intel® Arria® 10 GX Signal

Integrity Development Kit

Introduction

What’s in the Box

You can download the kit installer directly from

www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/

kit-a10-gx-si.html

A Complete Development Platform for Prototyping

The Intel® Arria® 10 GX Signal Integrity

Development Kit helps you thoroughly

evaluate the signal integrity of Intel

Arria 10 GX transceivers. With this kit,

you can:

• Evaluate Intel Arria 10 GX FPGA

transceiver performance

• Generate and check pseudo-

random binary sequence (PRBS)

patterns via an easy-to-use GUI

• Dynamicallychangedierential

output voltage (VOD),

pre-emphasis, and equalization

settings to optimize transceiver

performance for your channel

• Perform jitter analysis

• Verify physical medium attachment

(PMA) compliance to PCI Express*

(PCIe*), Gbps Ethernet (GbE), XAUI,

CEI-6G, Serial RapidIO*, high-

denitionserialdigitalinterface

(HD-SDI), and other major

standards

• Transceiver Signal Integrity Development Board,

- Intel Arria 10 GX FPGA (10AX115S2F45I1SG)

- Six full-duplex transceiver channels with 2.4 mm SMA connectors

- Four full-duplex transceiver channels to Amphenol Xcede+*

backplane connector

- Four full-duplex transceiver channels to CFP2 optical interface

- Four full duplex transceiver channel to QSFP+ optical interface

- Single transceiver channel to SFP+ optical interface

- Ten full-duplex transceiver channels to Samtec Bullseye high-density

connector

- LCD

- Ethernet PHY

• AC adapter power supply

• USB ll type A to B cable

• Ethernet cable

• Documentation

Quick start guide

Quick Start Guide | Intel Arria 10 GX Signal Integrity Development Kit

Using the Board Update Portal

The Board Update Portal design example in this kit

facilitateseasydevelopmentkitsoftwareandboardash

memory updates, allowing you to:

• Access useful information on www.intel.com/content/

www/us/en/products/programmable/fpga.html,

including updated software and design examples

• Loaddesignsintotheashmemoryonyourboard

The following steps ensures that you have the latest

software on your computer and board. The Board Update

Portal design example—which consists of a Nios® II

embedded processor, an Ethernet media access control

(MAC), and a web page—is stored in the “factory” portion

ofyourboard’sashmemory.Thesourceforthisdesignis

installed with the development kit software. When your

board is connected to the network, the Nios II processor

obtains an Internet protocol (IP) address and allows you to

interface with your board over the network through the

web page.

Before you proceed, ensure that you have the following:

• A computer connected to a working Ethernet port on a

DHCP-enabled network

• A separate working Ethernet port connected to the same

network for your board

• The Ethernet, power cables, and development board

included in your kit

Step 1. Connect to the Board Update Portal

1. With the board powered down, set SW3 position 2 to

open (factory position).

2. Attach the Ethernet cable from the board to your

network hub.

3. Power up the board. The LCD displays “Connecting” as it

connects to your network server (may take a couple of

minutes). It then obtains an IP address, which is

displayed on the board’s LCD.

4. Launch a web browser on a computer that is connected

to the same network, and type the IP address displayed

on the LCD in the address bar. The Board Update Portal

web page appears on your screen.

5. Click on the “Signal Integrity Development Kit” link and

download the latest version of the development kit

software. The version is displayed in the “Downloads”

section of the website.

6. Download any designs that interest you to your

computer. Check this website often for new designs and

for updates to existing designs and documentation.

7. If necessary, download the latest Intel software tools

— Intel Quartus® Prime software, Nios processor, and

intellectual property (IP) functions. This development

kit comes with an Intel Quartus Prime software license.

If you cannot connect to the Board Update Portal, go to

www.intel.com/content/www/us/en/programmable/

products/boards_and_kits/dev-kits/altera/kit-a10-gx-si.

html to ensure that you have the latest development kit

software.

Quick Start Guide | Intel Arria 10 GX Signal Integrity Development Kit

Using the Transceiver Signal Integrity

Demonstration

Figure 1. Directory Structure

Step 3. Use the Board Update Portal to update your board

and load the Transceiver Signal Integrity Demonstration

The Board Update Portal allows you to download new FPGA

congurationstothe“user”portionoftheboard’sash

memory. If you cannot connect to the Board Update Portal,

refer to the kit’s user guide for other options to update the

ashmemory.

Toupdatetheuserportionofashmemoryonyourboard,

follow these steps:

1. Type the IP address shown on the board’s LCD into your

PC’s web browser to display the Board Update Portal

web page.

2. IntheHardwareFileNameeld,specifythe.ashle

(<installation directory>\kits\arria10GX_10ax115sf45_

si\examples\board_test_system\qts_sma_amphenol\

bts_sma_amphenol.ash) that you downloaded from

the Intel website. Because the design does not have a

softwarecomponent,leavetheSoftwareFileNameeld

blank.

3. Click Upload.

4. ReconguretheFPGAwiththenewlesbychanging

SW3 position 2 back to the close position,then

repowering your board or pushing MAX_RESETn (S11) to

reconguretheFPGA.

The demonstration design now runs in the FPGA.

You can also use the Board Update Portal to upload your

custom designs. The kit’s user guide describes how to

prepare your designs for use with the Board Update Portal.

Files are installed in the following directory structure:

Step 2. Install the development kit software

Install the latest development kit software tools from

www.intel.com/content/www/us/en/products/program-

mable/fpga.html and follow the on-screen instructions to

complete the installation.

The Transceiver Signal Integrity Demonstration consists of

a Java-based GUI and an FPGA design. After updating your

board as described in Step 3, your board’s FPGA contains

the Transceiver Signal Integrity Demonstration design,

which communicates with the GUI through the On-Board

Intel FPGA Download Cable II circuitry.

To run the demonstration, follow these steps:

1. Connect the Intel FPGA Download Cable II type A to B

cable from your PC to the board.

2. If the Intel FPGA Download Cable II driver is not installed

on your PC, install the driver using the instructions in the

user guide.

3. Connect SMA cables from one or more channels on the

board to an oscilloscope capable of displaying the data

rates you wish to observe.

4. Make sure SW3 position 2 is set to close position (User

Hardware #1) and power up the board

5.LaunchtheBoardTestSystem.exele,locatedat

<installation directory>\kits\arria10GX_10ax115sf45_

si\examples\board_test_system. For optimal viewing,

your screen resolution must be 1024x768 or greater.

6. Select SMA port and desired Data Type, and then click

“Start” to run the test on the activated XCVR #2

tab (If XCVR #2 is not activated automatically, please

manuallycongureXCVR#2designfromthe 

conguremenu)

7. Observe the resulting eye diagram on the oscilloscope

and monitor the link statistics shown on the

screen.

For information on bit error rate (BER) calculation,

equalization settings, and other details regarding this

demonstration, refer to the user guide. Visit the Transceiver

Signal Integrity Development Kit page (www.intel.com/

content/www/us/en/programmable/products/boards_

and_kits/dev-kits/altera/kit-a10-gx-si.html) for the latest

documentation and designs.

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