Intel Quark D2000 Guide

Document Number: 333580-002EN
Intel® Quark™ Microcontroller D2000
Platform Design Guide
November 2016

Intel® Quark™ Microcontroller D2000
Platform Design Guide November 2016
2 Document Number: 333580-002EN
You may not use or facilitate the use of this document in connection with any infringement or other legal analysis concerning Intel products
described herein. You agree to grant Intel a non-exclusive, royalty-free license to any patent claim thereafter drafted which includes subject
matter disclosed herein.
No license (express or implied, by estoppel or otherwise) to any intellectual property rights is granted by this document.
All information provided here is subject to change without notice. Contact your Intel representative to obtain the latest Intel product
specifications and roadmaps.
The products described may contain design defects or errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Copies of documents which have an order number and are referenced in this document may be obtained by calling 1-800-548-4725 or by
visiting: http://www.intel.com/design/literature.htm
Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation.
Learn more at http://www.intel.com/ or from the OEM or retailer.
No computer system can be absolutely secure.
Intel, Quark and the Intel logo are trademarks of Intel Corporation in the U.S. and/or other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2016, Intel Corporation. All rights reserved.

Intel® Quark™ Microcontroller D2000
November 2016 Platform Design Guide
Document Number: 333580-002EN 3
Contents
1.0 Introduction.................................................................................................................................................7
1.1 Overview................................................................................................................................................................7
1.2 Audience and Purpose ....................................................................................................................................7
1.3 Terminology.........................................................................................................................................................8
1.4 Reference Documents .....................................................................................................................................8
2.0 System Assumptions .................................................................................................................................9
2.1 General Assumptions.......................................................................................................................................9
2.1.1 PCB Technology and Stackup................................................................................................ 11
2.1.2 PCB Technology Considerations .......................................................................................... 11
2.2 Backward and Forward Coupling Coefficient Calculation ............................................................ 14
2.3 Feature Set ........................................................................................................................................................ 15
2.4 CRB Pin Mapping ............................................................................................................................................ 17
3.0 Subsystem Details....................................................................................................................................18
3.1 Design Recommendations.......................................................................................................................... 18
3.2 General Design Guideline Assumptions ............................................................................................... 19
4.0 I²C Interface ...............................................................................................................................................20
4.1 I²C Interface Signals ...................................................................................................................................... 20
4.2Interface Routing Guidelines ..................................................................................................................... 21
4.2.1 General Design Considerations ............................................................................................. 22
5.0 Pulse Width Modulation (PWM) ............................................................................................................23
5.1 PWM Signaling................................................................................................................................................. 24
5.2 Functional Operation.................................................................................................................................... 24
6.0 UART ...........................................................................................................................................................26
6.1 Signal Descriptions ........................................................................................................................................ 27
6.2 Features .............................................................................................................................................................. 28
7.0 SPI................................................................................................................................................................30
7.1 Features .............................................................................................................................................................. 31
8.0 Clocking......................................................................................................................................................33
8.1 Features .............................................................................................................................................................. 34
9.0 General Purpose I/O (GPIO) ...................................................................................................................35
9.1 Signal Descriptions ........................................................................................................................................ 35
9.2 Features .............................................................................................................................................................. 36
10.0 JTAG............................................................................................................................................................38
11.0 Analog-to-Digital Converter (ADC).......................................................................................................39

Intel® Quark™ Microcontroller D2000
Platform Design Guide November 2016
4 Document Number: 333580-002EN
11.1 Features .............................................................................................................................................................. 39
12.0 Power Delivery..........................................................................................................................................41
12.1 DVDD Linear Regulator ................................................................................................................................ 41
12.1.1 Operation of an Active Pull –Down Circuit ...................................................................... 41
12.1.2 Implementation of an Active Pull –Down Circuit.......................................................... 41
Figures
Figure 1. Block Diagram .....................................................................................................................................................9
Figure 2. PCB Floor Plan ................................................................................................................................................. 10
Figure 3. System Diagram .............................................................................................................................................. 11
Figure 4. Single-Ended Microstrip Diagram ........................................................................................................... 12
Figure 5. Differential Microstrip Diagram ................................................................................................................ 13
Figure 6. Backward Coupling Coefficient ................................................................................................................ 14
Figure 7. Forward Coupling Coefficient ................................................................................................................... 14
Figure 8. Single-Ended Kb Diagram........................................................................................................................... 15
Figure 9. Differential Kb Diagram ............................................................................................................................... 15
Figure 10. CRB Pin Mapping Diagram.......................................................................................................................... 17
Figure 11. I²C Interface....................................................................................................................................................... 20
Figure 12. I²C Point-to-Point Topology...................................................................................................................... 21
Figure 13. PWM ..................................................................................................................................................................... 23
Figure 14. Duty Cycle of 20%.......................................................................................................................................... 24
Figure 15. Duty Cycle of 50%.......................................................................................................................................... 24
Figure 16. Duty Cycle of 80%.......................................................................................................................................... 24
Figure 17. UART .................................................................................................................................................................... 26
Figure 18. UART 2-Via Point-to-Point Topology.................................................................................................... 27
Figure 19. SPIO...................................................................................................................................................................... 30
Figure 20. SPI Point-to-Point Single-Ended Topology........................................................................................ 31
Figure 21. RTC........................................................................................................................................................................ 33
Figure 22. RTC Topology................................................................................................................................................... 34
Figure 23. GPIO ..................................................................................................................................................................... 35
Figure 24. GPIO Pin Routing Topology ....................................................................................................................... 36
Figure 25. JTAG Connectivity.......................................................................................................................................... 38
Figure 26. Analog Shielding Requirements .............................................................................................................. 39
Figure 27. Active Pull –Down circuit implementation ......................................................................................... 41
Tables
Table 1. Terminology.........................................................................................................................................................8
Table 2. Reference Documents .....................................................................................................................................8

Intel® Quark™ Microcontroller D2000
November 2016 Platform Design Guide
Document Number: 333580-002EN 5
Table 3. Stackup Details................................................................................................................................................ 13
Table 4. Good Layout Practices ................................................................................................................................. 19
Table 5. I²C Point-to-Point Platform Routing Guidelines ............................................................................... 21
Table 6. PWM Timing...................................................................................................................................................... 25
Table 7. Timer Period ..................................................................................................................................................... 25
Table 8. UART Signals .................................................................................................................................................... 27
Table 9. UART Point-to-Point Topology Platform Routing Guidelines.................................................... 28
Table 10. UART Point-to-Point Topology Platform Routing Guidelines.................................................... 28
Table 11. SPI Platform Routing Guidelines ............................................................................................................. 31
Table 12. RTC Signals........................................................................................................................................................ 34
Table 13. GPIO Pin Routing Guidelines..................................................................................................................... 36
Table 14. Generic Routing Requirements................................................................................................................. 38
Table 15. Active Pull –Down circuit BOM ................................................................................................................ 42

Intel® Quark™ Microcontroller D2000
Platform Design Guide November 2016
6 Document Number: 333580-002EN
Revision History
Date
Revision
Description
November 2016
002
Memory specification updated. Power Delivery chapter added.
December 2015
001
Initial release.
§

Introduction
Intel® Quark™ Microcontroller D2000
November 2016 Platform Design Guide
Document Number: 333580-002EN 7
1.0 Introduction
1.1 Overview
This design guide provides motherboard implementation recommendations for the
Intel® Quark™ Microcontroller D2000 platform, based on the Intel® Quark™
Microcontroller D2000 processor. This document includes design guidelines for Intel®
Quark™ Microcontroller D2000 platforms and the hardware integration aspects that
must be considered when designing a platform.
This design guide has been developed to ensure maximum flexibility for board
designers while reducing the risk of board-related issues. Design recommendations are
based on Intel's simulations and lab experience and are strongly recommended, if not
necessary, to meet the timing and signal quality specifications. Design
recommendations are based on the reference platforms designed by Intel. They should
be used as an example but may not be applicable to particular designs.
Note: The guidelines recommended in this document are based on experience, simulation,
and preliminary validation work done at Intel while developing the Intel® Quark™
Microcontroller D2000 processor-based platform. This work is ongoing, and these
recommendations are subject to change.
Caution: If the guidelines listed in this document are not followed, it is very important that
designers perform thorough signal integrity and timing simulations. Even when
following these guidelines, Intel recommends the critical signals to be simulated to
ensure proper signal integrity and flight time. Any deviation from the guidelines should
be simulated.
Metric units are used in some sections in addition to the standard use of U.S. customary
system of units (USCS). If there is a discrepancy between the metric and USCS units,
assume the USCS unit is most accurate. The conversion factor used is 1 inch (1000
mils) = 25.4 mm.
1.2 Audience and Purpose
The Intel® Quark™ Microcontroller D2000 is a highly integrated, ultra-low-power part
designed to enable innovative wearable solutions with long battery life for
fitness/health/wellness monitors, smart watches, and so on.
This document is intended to aid platform hardware designers in system
implementation and reference design reuse by:
Documenting the hardware implementation of a specific form factor wearable
based on the Intel® Quark™ Microcontroller D2000 platform

Introduction
Intel® Quark™ Microcontroller D2000
Platform Design Guide November 2016
8 Document Number: 333580-002EN
Providing details such as block diagrams, which illustrate connectivity, system level
considerations, options, and design guidelines
Describing the theory of operation or principles considered in deriving a design
guideline
1.3 Terminology
Table 1. Terminology
Term
Description
ADC
Analog-to-Digital Converter
CRB
Customer Reference Board
GPIO
General Purpose Input/Output
I²C
Inter-Integrated Circuit
I2S
Inter-IC Sound
JTAG
Joint Test Action Group
OSC
Oscillator
PWM
Pulse Width Modulation
RTC
Real-Time Clock
SIO
Serial I/O
SoC
System on Chip
SPI
Serial Peripheral Interface
UART
Universal Asynchronous Receiver Transmitter
XTAL
Crystal
1.4 Reference Documents
Table 2. Reference Documents
Document
Document No.
Intel® Quark™ Microcontroller D2000 Datasheet
333577
§

System Assumptions
Intel® Quark™ Microcontroller D2000
November 2016 Platform Design Guide
Document Number: 333580-002EN 9
2.0 System Assumptions
2.1 General Assumptions
This section covers general Intel® Quark™ Microcontroller D2000 and Intel® Quark™
Microcontroller D2000 Customer Reference Board (CRB) system topology and interface
connectivity assumptions. The Intel® Quark™ Microcontroller D2000 CRB is used as a
baseline reference example for guidelines.
Figure 1. Block Diagram

System Assumptions
Intel® Quark™ Microcontroller D2000
Platform Design Guide November 2016
10 Document Number: 333580-002EN
Figure 2. PCB Floor Plan

System Assumptions
Intel® Quark™ Microcontroller D2000
November 2016 Platform Design Guide
Document Number: 333580-002EN 11
Figure 3. System Diagram
2.1.1 PCB Technology and Stackup
The system uses the PCB technology of a standard interconnect, Type 3, 4-layer board,
no blind or buried vias. It is important to note that variations in the stackup of a
motherboard, such as changes in the dielectric height, trace widths, and spacing, can
impact the impedance, loss, and jitter characteristics of all the interfaces. Such changes
may be intentional, or may be the result of variations in the manufacturing process. In
either case, they must be properly considered when designing interconnects. This
design guide applies the CRB PCB stackup and trace width/spacing that is shown in
Figure 4.
Note: All the routing guidelines in this document are simulated based on the CRB stackup.
2.1.2 PCB Technology Considerations
The typical values, including the design and material tolerances, are centered on a
nominal single line impedance specification of 50𝛺± 15% for microstrip. Many
interfaces specify a different nominal single-ended impedance. For more details on the

System Assumptions
Intel® Quark™ Microcontroller D2000
Platform Design Guide November 2016
12 Document Number: 333580-002EN
nominal trace width to meet those impedance targets, refer to the individual interface
section.
The following general stackup recommendations should be followed:
Microstrip layers are assumed to be built from 1/2oz. foil, plated up nominally
another 1 oz.; however, the trace thickness range defined allows for significant
process variance around this nominal.
Based on the Intel® Quark™ Microcontroller D2000 layout layers, 3/4 dual stripline
is assumed to be built from 1 oz. copper.
All high-speed signals should reference solid planes over the length of their routing
and should not cross plane splits. Ground referencing is preferred.
Reference plane stitching vias must be used in conjunction with high-speed signal
layer transitions that include a reference plane change. Refer to each signal group
section for more specification.
The parameter values for internal and external traces are the final thickness and
width after the motherboard materials are laminated, conductors plated, and
etched. Intel uses these exact values to generate the associated electrical models
for simulation.
Figure 4. Single-Ended Microstrip Diagram

System Assumptions
Intel® Quark™ Microcontroller D2000
November 2016 Platform Design Guide
Document Number: 333580-002EN 13
Figure 5. Differential Microstrip Diagram
Table 3. Stackup Details
OPCM Stack-Up Information
Layer
Cu Weight
Proposed
Thickness
(mils)
Structure
Ref
Single End
Differential
50 Ohm ± 10%
90 Ohm ± 10%
Target
LW
Finished
LW
Target
LW/SP
Finished
LW/SP
Soldermask
0.50
L1
Top
Hoz+Plating
1.80
L2
3.94
4.2/8
Prepreg
2.70
1080
L2
GND
1oz
1.20
Core
50
50mil
core
L3
GND
1oz
1.20
Prepreg
2.70
1080
L4
Bottom
Hoz+Plating
1.80
L3
3.94
4.2/8
Soldermask
0.50
Finished
Thickness
(mils)
62.40

System Assumptions
Intel® Quark™ Microcontroller D2000
Platform Design Guide November 2016
14 Document Number: 333580-002EN
2.2 Backward and Forward Coupling Coefficient Calculation
Some designs require a stackup build that is outside of the ranges provided. In this
case, compare the routing electrical characteristics versus the Intel recommendation.
Comparing the single-ended and differential impedances is important. However,
crosstalk level, which is governed by trace spacing, is not implied by the impedance
target. Calculating and comparing the backward coupling coefficient is recommended
to choose proper trace spacing in cases where the selected stackup varies from the
Intel recommendation. The coupling coefficient represents the source voltage
percentage that is coupled to victim lines. As shown in Figure 6, Kb is defined as the
backward coupling coefficient. For backward (near- end) crosstalk, inductive and
capacitive coupling are of the same polarity and the noise magnitude is not a function
of trace length. The backward coupling coefficient (Kb) values can be used to determine
trace spacing. For forward (far-end) crosstalk, Kf inductive and capacitive coupling are
of opposite polarity, and the crosstalk magnitude (Vfe) is proportional to both trace
length and edge rate. Kf is typically a very small value in most practical designs.
Therefore, Intel has not included the Kf values in the design guide. However, if the value
is desired, the equation for calculating Kf is provided in Figure 7.
Figure 6. Backward Coupling Coefficient
Figure 7. Forward Coupling Coefficient

System Assumptions
Intel® Quark™ Microcontroller D2000
November 2016 Platform Design Guide
Document Number: 333580-002EN 15
Figure 8. Single-Ended Kb Diagram
Figure 9. Differential Kb Diagram
Breakout topologies are mainly decided by package ballout patterns and pitches.
Similar geometries will be used for various stackups. Refer to the interface sections for
the breakout maximum length allowed and signals not listed in Table 3.
2.3 Feature Set
A wearable can contain any feature set and capabilities supported on Intel® Quark™
Microcontroller D2000. The following is an example feature set of a typical wearable
and used in the Intel® Quark™ Microcontroller D2000 form factor. Refer to the SoC
Datasheet for the latest features supported on the platform.
Intel® Quark™ Microcontroller D2000 features:
Intel® Quark™ Microcontroller D2000 SoC 32 MHz
32 KB flash memory (internal)
8 KB OTP flash (internal)
4 KB Data flash (internal)
8 KB SRAM (internal)
1x I²C (Master/Slave)
1x SPI master supports up to 4 devices
1x SPI slave
2x UART, supports 9-bit addressing mode
19 ADC/Comparator inputs

System Assumptions
Intel® Quark™ Microcontroller D2000
Platform Design Guide November 2016
16 Document Number: 333580-002EN
2x PWM signals
25 GPIOs
Real-time clock
Watchdog timer
Intel® Quark™ Microcontroller D2000 main expansion options:
“Arduino Uno” compatible SIL sockets (3.3V I/O only)
Intel® Quark™ Microcontroller D2000 on-board components:
Accelerometer/Magnetometer sensor
UART/JTAG to USB convert for USB debug port
Other Intel® Quark™ Microcontroller D2000 connectors:
1x USB 2.0 Device Port –micro Type B
On-board coin cell battery holder
5V input screw terminal/header (external power or Li-ion)
EEMBC power input header
Power sources for this platform:
External 5V DC input
Li-ion battery (external)
USB power (5V) via debug port
Coin cell battery (on-board)

System Assumptions
Intel® Quark™ Microcontroller D2000
November 2016 Platform Design Guide
Document Number: 333580-002EN 17
2.4 CRB Pin Mapping
Figure 10 shows the CRB interfaces and mapping.
Figure 10. CRB Pin Mapping Diagram
§

Subsystem Details
Intel® Quark™ Microcontroller D2000
Platform Design Guide November 2016
18 Document Number: 333580-002EN
3.0 Subsystem Details
This chapter provides design guidelines for the SoC associated interfaces. All of the
routing guidelines (W/S, isolation, length requirement) are based on CRB 4-layer PCB
technology. If a different PCB stackup is implemented, the electrical guidelines
(impedance, Kb, Insertion Loss) provided in this document must be followed to ensure
that the layout can meet simulation recommendations.
3.1 Design Recommendations
The Intel® Quark™ Microcontroller D2000 SoC is an ultra-low-power Intel® architecture
SoC that integrates an Intel® Quark™ Microcontroller D2000 processor core, memory
subsystem with on-die volatile and non-volatile storage and I/O interfaces into a single
system-on-chip solution.
This section presents design recommendations for the subsystems that make up the
Intel® Quark™ Microcontroller D2000 platform. The sections include overview
information, component selection studies, suggested routing guidelines, and additional
filter and signal information for the Intel® Quark™ Microcontroller D2000 platform.
The design recommendations are developed to ensure maximum flexibility for board
designers while reducing the risk of board-related issues.
Note: These design recommendations should be carefully followed and any deviations
should be verified through simulations. The component selection recommendations
describe the components that are being considered for the Intel® Quark™
Microcontroller D2000. If and when updated boards become available, this will be
noted in these sections.
The following subsystems are covered in this section:
On-die SRAM
Display interface
SPI
Storage
SPI
I²C
SPI
Integrated Sensor
UART
GPIO

Subsystem Details
Intel® Quark™ Microcontroller D2000
November 2016 Platform Design Guide
Document Number: 333580-002EN 19
3.2 General Design Guideline Assumptions
The following assumptions pertain to all the subsystems discussed in this chapter.
Package length compensation is needed. The length values are tested and
measured as package-pin-to-package-pin.
The breakout and breakin minimum spacing ratio is 1:1 for all interfaces.
The trace width/intra-spacing for differential pairs and trace width for single-
ended signals depend on the impedance.
For analog signals, it is important to keep the analog ground return path clean of
digital noise to maintain a high signal-to-noise ratio.
For technical specifications (such as speeds, supported resolutions, and data rates),
refer to the Intel® Quark™ Microcontroller D2000 Datasheet.
Note: 1. Follow the general guidelines in this section, if a specific interface design guide is
not available.
2. All the routing guidelines in this document are simulated based on the CRB
stackup.
Table 4. Good Layout Practices
Stitching Vias
Provide stitching vias for layer transitions
Break-In/Break-Out Regions
1. If desired trace width cannot be maintained in the break regions, maintain a minimum trace
width of 3.5 mil.
2. If desired trace spacing cannot be maintained in the break regions, maximize the trace
spacing.
Over and Around the Voids
1. Avoid routing over the voids and reference plane splits. Consult the SIE if split crossing
cannot be avoided
2. When going around the voids, maintain a minimum spacing of 1xh between signal trace and
void. Desirable spacing is 3xh where "h" is the distance to the nearest reference plane.
Lateral Distance to Reference Plane Edge
1. Keep a signal trace 4xh away from the edge of the reference plane.
§

I²C Interface
Intel® Quark™ Microcontroller D2000
Platform Design Guide November 2016
20 Document Number: 333580-002EN
4.0 I²C Interface
I²C is a two-wire serial bus for inter-IC communication. One wire is for data, the other
for clock. There is one I²C controller. The controller owns its own two-wire bus.
4.1 I²C Interface Signals
Signals for the I²C interface are illustrated in the table 6 below.
Figure 11. I²C Interface
I²C features:
One I²C interface
Support for both master and slave operation
Operational speeds:
Standard mode (0 to 100Kbps)
Fast mode (≤ 400Kbps)
Fast mode plus (≤ 1Mbps)
7-bit or 10-bit addressing
Support for clock stretching by slave devices
Multi-master arbitration
Spike suppression