Intel Agilex 7 FPGA I Series User manual

Intel Agilex® 7 FPGA I-Series
Transceiver-SoC Development Kit
User Guide
Online Version
Send Feedback
ID: 721605
Version: 2023.04.10

Contents
1. Overview........................................................................................................................ 4
1.1. Block Diagram.......................................................................................................6
1.2. Feature Summary..................................................................................................6
1.3. Box Contents........................................................................................................ 7
1.4. Recommended Operating Conditions........................................................................ 7
2. Getting Started............................................................................................................... 8
2.1. Intel Quartus® Prime Software and Driver Installation................................................ 8
2.2. Design Examples................................................................................................... 8
3. Power Up the Development Kit..................................................................................... 10
3.1. Default Settings...................................................................................................10
3.2. Power Up............................................................................................................11
3.3. Perform Board Restore..........................................................................................12
3.3.1. Restore Board System Intel MAX 10 with Default Factory Image.....................12
3.3.2. Restore Board QSPI Flash with Default Factory Image................................... 12
4. Board Test System........................................................................................................ 13
4.1. Set Up BTS GUI Running Environment.................................................................... 14
4.1.1. Download OpenJDK.................................................................................. 14
4.1.2. Download OpenJFX.................................................................................. 15
4.1.3. Install OpenJDK and OpenJFX.................................................................... 15
4.1.4. Install Intel Quartus Prime Software........................................................... 15
4.1.5. Run BTS GUI........................................................................................... 16
4.2. Test the Functionality of the Development Kit.......................................................... 17
4.2.1. The Bottom Info Bar.................................................................................17
4.2.2. The Configure Menu................................................................................. 17
4.2.3. The Sys Info Tab...................................................................................... 18
4.2.4. The GPIO Tab.......................................................................................... 19
4.2.5. The XCVR Tab..........................................................................................21
4.2.6. The Memory Tab...................................................................................... 30
4.3. Control On-Board Clock through Clock Controller GUI............................................... 33
4.4. Monitor On-Board Power Regulator through Power Monitor GUI.................................. 37
4.5. BTS Test Areas.................................................................................................... 38
4.6. Identify Test Pass or Fail-based on BTS GUI Test Status.............................................38
5. Development Kit Hardware and Configuration.............................................................. 39
5.1. Configure FPGA and Access HPS Debug Access Port by JTAG...................................... 39
5.2. Configure the FPGA Device Using the AS Mode (Default Mode)................................... 39
5.3. Configure the FPGA Device Using the Avalon-ST Mode.............................................. 39
5.4. Daughter Cards................................................................................................... 40
5.4.1. HPS Out of Box Experience (OOBE) Daughter Card....................................... 40
6. Custom Projects for the Development Kit..................................................................... 41
6.1. Add SmartVID Settings in the Intel Quartus Prime QSF File....................................... 41
6.2. Golden Top......................................................................................................... 42
7. Document Revision History for the Intel Agilex 7 FPGA I-Series Transceiver-SoC
Development Kit User Guide.................................................................................... 43
Contents
Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide Send Feedback
2

A. Development Kit Components....................................................................................... 45
A.1. System Management............................................................................................45
A.2. Power................................................................................................................ 47
A.3. Clocks................................................................................................................ 50
A.4. General Input/Output...........................................................................................52
A.5. Memory Interfaces...............................................................................................56
A.6. Communication Interfaces.................................................................................... 56
A.7. Daughter Cards................................................................................................... 60
A.8. Connectors and Cables......................................................................................... 61
B. Additional Information................................................................................................. 62
B.1. Safety and Regulatory Information.........................................................................62
B.1.1. Safety Warnings...................................................................................... 63
B.1.2. Safety Cautions....................................................................................... 64
B.2. Compliance Information........................................................................................67
Contents
Send Feedback Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
3

1. Overview
Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit is a complete design
environment that includes both hardware and software you need to develop Intel
Agilex 7 FPGA I-Series designs. The board provides a wide range of peripherals and
memory interfaces to facilitate the development of Intel Agilex 7 I-Series Transceiver-
SoC designs.
Table 1. Ordering Information
Development Kit Version Ordering Code Device Part Number Serial Number Identifier
Intel Agilex 7 FPGA I-Series
Transceiver-SoC
Development Kit (Production
1 4x F-Tile)
DK-SI-AGI027FA (Power
Solution 2)
AGIB027R31B1E1V 2000001
Intel Agilex 7 FPGA I-Series
Transceiver-SoC
Development Kit (Production
2)
DK-SI-AGI027FC (Power
Solution 2)
AGIB027R31B1E1VB 3000001
Intel Agilex 7 FPGA I-Series
Transceiver-SoC
Development Kit (ES1 4x F-
Tile)
DK-SI-AGI027FB (Power
Solution 1)
AGIB027R31B1E1VAA 0001001
Intel Agilex 7 FPGA I-Series
Transceiver-SoC
Development Kit (ES)
DK-SI-AGI027FES (Power
Solution 1)
AGIB027R31B1E2VR0 0000001
For the board and FPGA capabilities, refer to the Intel Agilex 7 FPGA and SoC FPGA I-
Series page on the Intel® website.
For more information about the Intel Agilex 7 Device Errata Sheet and User Guidelines
(ES-1069) and Intel Agilex 7 Known Issue List, contact Intel Premier Support and
quote ID #15011992053.
721605 | 2023.04.10
Send Feedback
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

Figure 1. Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit Board Image -
DK-SI-AGI027FB and DK-SI-AGI027FES (Intel Enpirion®)
Figure 2. Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit Board Image -
DK-SI-AGI027FA and DK-SI-AGI027FC (Not Intel Enpirion®)
Related Information
Intel Agilex 7 FPGA and SoC FPGA I-Series
1. Overview
721605 | 2023.04.10
Send Feedback Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
5

1.1. Block Diagram
Figure 3. Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit Block Diagram
1.2. Feature Summary
• Intel Agilex 7 FPGA I-Series, 2.7M LE, 3184B package
• F-Tile 1 (13C)
— 4 FHT transceiver channels fan out to Quad Small Form Factor Double Density
800 (QSFPDD800)
— 8 FGT transceiver channels to Quad Small Form Factor Double Density
connector
— 2 FGT transceiver channels to HD-BNC for SDI
— 4 FGT transceiver as DP2.0(1)
— 1FGT transceiver for USB3.2(1)
• F-Tile 2 (13A)
— 4 FHT transceiver channels (116G) to MXPM
— 8 FGT transceiver channels (56G) to MXPM
— 8 FGT transceiver channels to Quad Small Form Factor Double Density
connector
— 4 FGT transceiver channels to MCIO (PCIe*)
• F-Tile 3 (12C)
— 16 FGT channels to FMC+
• F-Tile 4 (12A)
— 16 FGT channels to FMC+
(1) Preliminary
1. Overview
721605 | 2023.04.10
Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide Send Feedback
6

• SR DDR4 2666 (x72 w/ ECC), 16GB
• 8GB SR DDR4-2666 (x72 w/ ECC) component down (HPS)
• IO48 interface for HPS Out of Box Experience (OOBE) daughter cards
1.3. Box Contents
• Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit
• Single-rank DDR4 DIMM module
• QSPI flash daughter card
• HPS IO48 OOBE daughter card
• NAND daughter card
• USB 2.0 Type B cable
• Ethernet cable
• 240W power adapter and NA/EU/JP/UK cords
• ATX power convert cable - 24 pin to 6 pin
1.4. Recommended Operating Conditions
Table 2. Recommended Operating Conditions
Operating Condition Range of Values
Ambient operating temperature range 0 °C to 30 °C
ICC load current 195 A
ICC load transient percentage 200 A/µs
FPGA maximum power supported by active heatsink/fan 160 W(2)
When handling the board, it is important to observe static discharge precautions.
Caution: Without proper anti-static handling, the board can be damaged. Therefore, use anti-
static handling precautions when touching the development kit.
Note: This development kit should not be operated in a vibration environment.
(2) 160W for core and 60W for FGT Transceiver
1. Overview
721605 | 2023.04.10
Send Feedback Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
7

2. Getting Started
2.1. Intel Quartus® Prime Software and Driver Installation
Intel Quartus® Prime design software is a multiplatform design environment that
easily adapts to your specific needs in all phases of FPGA, CPLD and SoC designs. The
Intel Quartus Prime software delivers the highest performance and productivity for
Intel FPGAs, CPLDs, and SoCs. Intel Quartus Prime Pro Edition software is optimized
to support the advanced features in next-generation FPGAs and SoCs with the Intel
Agilex 7, Intel Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 GX device families.
Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit includes on-board Intel
FPGA Download Cable circuits for FPGA and system Intel MAX® 10 programming.
However, for the host computer and board to communicate, you must install the Intel
FPGA Download Cable driver on the host computer. Installation instructions for the
Intel FPGA Download Cable driver for your operating system are available on the Intel
website.
On the Intel website, navigate to the Cable and Adapter Drivers Information link to
locate the table entry for your configuration and click the link to access the
instructions.
The Intel SoC EDS is a comprehensive software tool suite for embedded software
development on Intel SoC devices. It contains development tools, utility programs,
run-time software, and application examples to expedite firmware and application
software of SoC embedded systems.
As a part of the Intel SoC EDS, the Arm* Development Studio 5 (DS-5) Intel SoC
FPGA Edition Toolkit provides a comprehensive set of embedded development tools for
Intel's SoC FPGAs.
For more information and steps to install the Intel SoC EDS Tool Suite, refer to the
links below.
Related Information
•Quick-Start for Intel Quartus Prime Pro Edition Software
•Intel Quartus Prime Pro Edition User Guide: Getting Started
•Arm DS-5 Intel SoC FPGA Edition Toolkit
•Intel SoC FPGA Embedded Development Suite User Guide
2.2. Design Examples
Unzip the install package which includes board design files, documents and examples
directories. The table below lists the file directory names and a description of their
contents.
721605 | 2023.04.10
Send Feedback
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

Table 3. Installed Development Kit Directory Structure
Directory Name Description of Directory Contents
board_design_files Contains schematics, layout, assembly and bill of material
board design files. Use these files as a starting point for a
new prototype board design
documents Contains the development kit documentation – quick start
guides and user guide
examples Contains:
• Board Test System: BTS GUI, Power GUI, and Clock GUI
• Golden Top project for pinout assignments management
• Design Examples: Memory, XCVR, GPIO, System Intel
MAX 10
factory_recovery The original data programmed into flash U85 for AVST x32
configuration and System Intel MAX 10 before shipment.
Use this data to restore the board with its original factory
content.
2. Getting Started
721605 | 2023.04.10
Send Feedback Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
9

3. Power Up the Development Kit
The instructions in this chapter explain how to setup the Intel Agilex 7 FPGA I-Series
Transceiver-SoC Development Kit for specific use cases.
3.1. Default Settings
The Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit ships with its board
switches preconfigured to support the design examples in the kit. If you suspect your
board might not be correctly configured with the default settings, follow the
instructions in the factory default switch settings table to return to its factory settings
before proceeding ahead.
Note: X refers to Don't Care in the table below.
Note: Don't set the switches when the power is on. Only set the switches after the power is
off.
Table 4. Factory Default Switch Settings
Switch Default Position Default Function
S19 [1:4] OFF/OFF/ON/ON System Intel MAX 10 and FPGA
selected in JTAG chain.
S20 [1:4] ON/ON/ON/ON Mode 1: On-board Intel download
circuit act as the only JTAG master.
Chained HPS with SDM nodes
internally.
S9 [1:4] ON/OFF/OFF/X Configuration mode setting bits:
AS - Fast mode
S10 [1:4] ON/ON/ON/ON SYS_SW[0:3]
• SYS_SW[0]—Factory Loadn
• ‘0’—Load image from Page 0 of the
QSPI
• SYS_SW[1]—MUX_SEL1
• SYS_SW[2]—MUX_SEL7
• SYS_SW[3]—MUX_SEL9
continued...
721605 | 2023.04.10
Send Feedback
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

Switch Default Position Default Function
S15 [1:4] ON/ON/ON/OFF SYS_SW[4:7]
• SYS_SW[4]—MUX_SEL_ZL
• SYS_SW[5]—FMC-A PCIe RP/EP
Select
— “0”: RP (Default)
— “1”: EP
• SYS_SW[6]—FMC-B PCIe RP/EP
Select
— “0”: RP (Default)
— “1”: EP
• SYS_SW[7]—MCIO PCIe RP/EP
Select
— “0”: RP
— “1”: EP (Default)
S1 [1:4] OFF/OFF/OFF/OFF User Switch [0:3]
S6 [1:4] OFF/OFF/OFF/OFF User Switch [4:7]
S22 [1:4] ON/ON/ON/ON MUX_DIP_SW[0:3]
• MUX_DIP_SW0—MUX_SEL2
• MUX_DIP_SW1—MUX_SEL3
• MUX_DIP_SW2—MUX_SEL4
• MUX_DIP_SW3—MUX_SEL5
Set to "ON" by default to select on-
board clock as input.
S23 [1:4] ON/ ON / ON / ON MUX_DIP_SW[4:7]
• MUX_DIP_SW4—MUX_SEL10
• MUX_DIP_SW5—MUX_SEL11
• MUX_DIP_SW6—MUX_SEL12
• MUX_DIP_SW7—MUX_SEL14
Set “0”/closed by default for on-board
clock as input.
S4 [1:4] ON/ ON / ON / ON MUX_DIP_SW[8:11]
• MUX_DIP_SW8—MUX_SEL13
• MUX_DIP_SW9—MUX_SEL6
• MUX_DIP_SW10—MUX_SEL0
• MUX_DIP_SW11—MUX_SEL8
Set “0”/closed by default for on-board
clock as input.
3.2. Power Up
To power up the development kit, follow these steps:
1. Use the provided 240 W power adapter to supply power through J30.
2. After power adapter is plugged into J30 and switch S18 is set to the ON position,
D22 LED illuminates, indicating that the board power up successfully. If the LED
(D22) is not turned ON, it indicates that one or more power supply is incorrect.
3. Power Up the Development Kit
721605 | 2023.04.10
Send Feedback Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
11

3.3. Perform Board Restore
This development kit ships with GHRD design examples stored in the QSPI flash device
and system Intel MAX 10 pre-programmed. You must perform board restore by using
the restore menu in BTS GUI or following the instructions below through the Intel
Quartus Prime Programmer GUI.
3.3.1. Restore Board System Intel MAX 10 with Default Factory Image
1. Open Intel Quartus Prime Programmer GUI, and detect the JTAG chain after
System Intel MAX 10 is restored.
2. Attach System Intel MAX 10 image on System Intel MAX 10 part.
3. Select programming options and click program button.
Note: Once you plug Intel FPGA Download Cable between J11 and PC, the Intel
on-board download cable circuit is disabled automatically.
3.3.2. Restore Board QSPI Flash with Default Factory Image
Note: The QSPI flash is pre-programmed with GHRD image. Completing the steps overwrites
the AvSTx32 image. Refer to https://rocketboards.org/ to recover and update GHRD
image on QSPI flash.
1. Plug QSPI flash card into J3 slot and ensure MSEL[2:0] are OFF (AvST x32 mode)
before power up the board.
2. Open Intel Quartus Prime Programmer GUI, detect JTAG chain after System Intel
MAX 10 is restored.
3. Attached AvST x32 image (BTS/image/ES/QSPI folder) on QSPI flash which is
under System Intel MAX 10 part.
4. Select programming options and click program button.
3. Power Up the Development Kit
721605 | 2023.04.10
Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide Send Feedback
12

4. Board Test System
The Intel Agilex 7 FPGA I-Series Transceiver-SoC Development Kit includes design
examples and the board test system (BTS) GUI to test the functionality of this board.
The BTS provides an easy-to-use interface to alter functional settings and observe
results. You can use the BTS to test board components, modify functional parameters,
observe performance, and measure power usage.
While using the BTS, you reconfigure the FPGA several times with test designs specific
to the functionality that you are testing. The BTS is also useful as a reference for
designing systems. The BTS communicates over the JTAG bus to a test design running
in the Intel Agilex 7 FPGA I-Series.
The following figure shows the graphical user interface (GUI) of a board that is in
factory configuration.
Figure 4. BTS GUI (Intel Enpirion®) DK-SI-AGI027FB and DK-SI-AGI027FES
721605 | 2023.04.10
Send Feedback
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the
application or use of any information, product, or service described herein except as expressly agreed to in
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
ISO
9001:2015
Registered

Figure 5. BTS GUI (Not Intel Enpirion®) DK-SI-AGI027FA and DK-SI-AGI027FC
4.1. Set Up BTS GUI Running Environment
To run BTS GUI, including Power Monitor and Clock Controller GUI, you need to
download and install Java runtime including OpenJDK and OpenJFX on your systems
and set up the running environment. This is a one-time procedure, so if you have
already completed it before, you do not need to do it again unless the Java version
upgrade is needed.
4.1.1. Download OpenJDK
To download the Temurin OpenJDK, follow these steps:
1. Download the Temurin OpenJDK using this link: https://adoptium.net/
releases.html.
2. Select Architecture x64, Package Type JRE, and Version 11.
3. On Windows system, choose the JRE zip format file.
4. On Linux system, choose the JRE tar.gz format file.
4. Board Test System
721605 | 2023.04.10
Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide Send Feedback
14

4.1.2. Download OpenJFX
To download the OpenJFX, follow these steps:
1. Download the OpenJFX using this link: https://gluonhq.com/products/javafx/.
2. Select JavaFX version 17.0.2 [LTS].
3. For the Windows system, download the JavaFX Windows x64 SDK.
4. For Linux system, download the JavaFX Linux x64 SDK.
4.1.3. Install OpenJDK and OpenJFX
You have two downloaded zip files, follow these steps to install them.
1. On Windows system, Intel recommends you to unzip the files and put them in
the following directory:
— C:\Program Files\Java\jre
— C:\Program Files\Java\jfx
Note: The unzipped folder name of JRE is jdk-11.0.xx+x-jre (for example,
jdk-11.0.14+9-jre), you need to rename it to jre. The unzipped folder
name of JFX is javafx-sdk-17.0.2, you need to rename it to jfx.
2. On Linux system, Intel recommends you to unzip the files and rename the folders
using the following commands:
# unzip openjfx-17.0.2_linux-x64_bin-sdk.zip -d /opt/Java/
# tar zxvf OpenJDK11U-jre_x64_linux_hotspot_11.0.14_9.tar.gz -C /opt/Java/
# cd /opt/Java
# mv javafx-sdk-17.0.2 jfx
# mv jdk-11.0.14+9-jre jre
You have the following two directories on your Linux system:
— /opt/Java/jre
— /opt/Java/jfx
4.1.4. Install Intel Quartus Prime Software
You must install the Intel Quartus Prime software to support the silicon on the
development kit. The recommended version is located in the README.txt file in the
examples\board_test_system directory. If you choose to install individual files,
you must install Intel Agilex 7 Device Support.
The BTS communicates over JTAG to a test design running in the FPGA. The BTS and
Power Monitor share the JTAG with other applications such as the Nios® II JTAG Debug
Module and the Signal Tap Logic Analyzer. Intel recommends closing other applications
before using BTS, as the GUI is designed based on the Intel Quartus Prime software.
The BTS relies on the Intel Quartus Prime software's specific library. Before running
the BTS, open the Intel Quartus Prime software to automatically set the environment
variable QUARTUS_ROOTDIR. You can also change it through Window's Environment
Variables in System Properties. The BTS uses this environment variable to locate the
Intel Quartus Prime library.
4. Board Test System
721605 | 2023.04.10
Send Feedback Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
15

4.1.5. Run BTS GUI
Follow these steps to power up the development kit and run the BTS GUI:
1. Connect the USB cable to your PC and the board.
2. Check the development board switches and jumpers are set according to your
preferences. Refer to Power Up Development Kit. In most cases, BTS requires
system Intel MAX 10 and Intel Agilex 7 FPGA on the JTAG chain while Clock
Controller and Power Monitor require only System Intel MAX 10.
3. Check the external modules status: MXPM cable/QSFP/QSFPDD/FMC/DIMM
4. Turn on the board power switch.
Note: To ensure operating stability, keep the USB cable connected and the board powered on
when running the demonstration application. You must attach the USB cable and
power on the board for BTS to run correctly.
Navigate to the <packagedir>\examples\board_test_system directory to run
BTS. The BTS release folder always includes the following files.
Figure 6. BTS Folder
You can run BTS GUI easily with the following scripts.
1. On Windows system, double click the .bat files to run BTS, Clock Controller, or
Power Monitor GUI.
Figure 7. Windows Console
2. On Linux system, you need to run the shell script with root privilege.
4. Board Test System
721605 | 2023.04.10
Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide Send Feedback
16

Figure 8. Linux Console
Note: The .bat or shell script checks the Java environment settings, copies
necessary files, and gives some prompts if the environment is not set up
correctly.
The GUI displays the application tab corresponding to the design running in the
FPGA. If the design loaded in the FPGA is not supported, it prompts a message to
configure your board with a valid BTS design. Refer to The Configure Menu.
4.2. Test the Functionality of the Development Kit
This section describes each control in the BTS.
4.2.1. The Bottom Info Bar
The bottom information bar shows the status of the system connection, the Intel
Quartus Prime version and the JTAG clock.
•System Connected/Disconnected: Shows if the board is connected to the
system. The green sign turns gray if the board becomes disconnected.
•Intel Quartus Prime Version: Displays the current Intel Quartus Prime version
installed and active on your system. The text turns red if your version is older
than the required version. Change the QUARTUS_ROOTDIR environment variable if
you have installed the right version but the active version does not meet the
requirement.
•JTAG: Displays the JTAG clock frequency.
4.2.2. The Configure Menu
Use the Configure Menu to select the design you want to use. Each design example
tests different functionality that corresponds to one or more application tabs.
4. Board Test System
721605 | 2023.04.10
Send Feedback Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
17

Figure 9. The Configure Menu
To configure the FPGA with a test system design, follow these steps:
1. On the Configure menu, click the Configure command that corresponds to the
functionality you want to test.
2. In the dialog box that appears, click Configure to download the corresponding
design's SRAM Object File (.sof) to the FPGA. The download process usually takes
less than a minute.
3. When configuration finishes, the design begins running in the FPGA. The
corresponding GUI application tabs that interface with the design are now
enabled. If you use the Intel Quartus Prime Programmer for configuration, instead
of the BTS GUI, you might need to restart the GUI.
4.2.3. The Sys Info Tab
The Sys Info tab shows information about the board's current configuration. The tab
displays the board information, JTAG Chain devices and other details stored on the
board.
4. Board Test System
721605 | 2023.04.10
Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide Send Feedback
18

Figure 10. The Sys Info Tab
The following sections describe the controls on the System Info tab.
Board Information
The board information control displays static information about your board.
•Board Name: Indicates the official name of the board given by the BTS.
•Board Revision: Indicates the revision of the board.
•MAX Version: Indicates the version of the system Intel MAX 10.
JTAG Chain
The JTAG chain control shows all the devices currently in the JTAG chain.
Note: You should place the system Intel MAX 10 and FPGA in the JTAG chain when running
the BTS GUI.
4.2.4. The GPIO Tab
The GPIO tab allows you to interact with all the general-purpose user I/O components
on your board. You can turn LEDs on or off and see the status of push buttons and dip
switches.
4. Board Test System
721605 | 2023.04.10
Send Feedback Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide
19

Figure 11. The GPIO Tab
The following sections describe the controls on the GPIO tab.
User LEDs
The User LEDs control displays the current state of the user LEDs. Toggle the LED
buttons to turn the board LEDs on and off. Click the All button to reverse the state of
all the LEDs.
User Dip Switches
The User Dip Switches control display the status of the USER_SW[0:3](S1) and
USER_SW[4:7](S6).
Push Buttons
The Push Button control shows the status of PB0 and PB1.
Qsys Memory Map
The Qsys Memory Map control shows the memory map of bts_config.sof design
running on your board.
4. Board Test System
721605 | 2023.04.10
Intel Agilex® 7 FPGA I-Series Transceiver-SoC Development Kit User Guide Send Feedback
20