Intel MFSYS25V2 User manual

Intel®Compute Module MFS5520VI
Technical Product Specification
Intel order number: E64311-007
Revision 1.5
December, 2010
Enterprise Platforms and Services Division

Revision History Intel® Compute Module MFS5520VI TPS
Revision 1.5
Intel order number: E64311-007
ii
Revision History
Date Revision
Number
Modifications
February, 2009 1.0 Initial release.
June, 2009 1.1 Updated the document.
March, 2010 1.2 Updated the document.
April, 2010 1.3 Updated the document.
May, 2010 1.4 Removed CCC and CNCA.
December, 2010 1.5 Updated Video mode info and BMC memory size.
Disclaimers
Information in this document is provided in connection with Intel®products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's
Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any
express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property
right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make
changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.
The Intel®Compute Module MFS5520VI may contain design defects or errors known as errata which may cause the
product to deviate from published specifications. Current characterized errata are available on request.
Intel Corporation server baseboards support peripheral components and contain a number of high-density VLSI and
power delivery components that need adequate airflow to cool. Intel’s own chassis are designed and tested to meet
the intended thermal requirements of these components when the fully integrated system is used together. It is the
responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor
datasheets and operating parameters to determine the amount of air flow required for their specific application and
environmental conditions. Intel Corporation can not be held responsible if components fail or the compute module
does not operate correctly when used outside any of their published operating or non-operating limits.
Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2010.

Intel® Compute Module MFS5520VI TPS Table of Contents
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Table of Contents
1. Introduction ..........................................................................................................................1
1.1 Chapter Outline........................................................................................................ 1
1.2 Intel®Compute Module Use Disclaimer................................................................... 1
2. Product Overview.................................................................................................................2
2.1 Intel®Compute Module MFS5520VI Feature Set .................................................... 2
2.2 Compute Module Layout.......................................................................................... 3
2.2.1 Connector and Component Locations ..................................................................... 3
2.2.2 External I/O Connector Locations............................................................................ 3
2.2.3 Compute Module Mechanical Drawings .................................................................. 5
3. Functional Architecture.......................................................................................................6
3.1 Intel®Xeon®processor ............................................................................................ 7
3.1.1 Processor Support ................................................................................................... 7
3.1.2 Mixed Processor Configuration................................................................................ 7
3.1.3 Turbo Mode ............................................................................................................. 9
3.1.4 Hyper-Threading...................................................................................................... 9
3.1.5 Intel®QuickPath Interconnect .................................................................................. 9
3.1.6 Unified Retention System Support......................................................................... 10
3.2 Memory Subsystem ............................................................................................... 11
3.2.1 Intel®QuickPath Memory Controller ...................................................................... 11
3.2.2 Publishing Compute Module Memory .................................................................... 11
3.2.3 Memory Map and Population Rules....................................................................... 12
3.2.4 Memory RAS ......................................................................................................... 13
3.2.5 Memory Upgrade Rules......................................................................................... 15
3.3 Intel®5520 Chipset IOH......................................................................................... 17
3.4 Intel®82801JR I/O Controller Hub (ICH10R)......................................................... 17
3.4.1 PCI Subsystem ...................................................................................................... 18
3.4.2 USB 2.0 Support.................................................................................................... 18
3.5 Integrated Baseboard Management Controller...................................................... 19
3.5.1 Floppy Disk Controller ........................................................................................... 21
3.5.2 Keyboard and Mouse Support ............................................................................... 21
3.5.3 Wake-up Control.................................................................................................... 21
3.6 Video Support ........................................................................................................ 21
3.6.1 Video Modes.......................................................................................................... 21
3.7 Network Interface Controller (NIC) ........................................................................ 22
3.7.1 Direct Cache Access (DCA) ..................................................................................22
3.8 Intel®Virtualization Technology for Directed I/O (Intel® VT-d)................................ 22
4. Connector/Header Locations and Pin-outs .....................................................................23
4.1 Board Connector Information................................................................................. 23

Table of Contents Intel® Compute Module MFS5520VI TPS
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4.2 Power Connectors ................................................................................................. 23
4.3 I/O Connector Pin-out Definition ............................................................................ 24
4.3.1 VGA Connector...................................................................................................... 24
4.3.2 I/O Mezzanine Card Connector ............................................................................. 24
4.3.3 Midplane Signal Connector.................................................................................... 28
4.3.4 Serial Port Connector ............................................................................................ 29
4.3.5 USB 2.0 Connectors .............................................................................................. 29
5. Jumper Block Settings ......................................................................................................31
5.1 Recovery Jumper Blocks ....................................................................................... 31
5.1.1 CMOS Clear and Password Clear Usage Procedure ............................................ 32
5.1.2 Integrated BMC Force Update Procedure ............................................................. 32
5.1.3 Integrated BMC Initialization.................................................................................. 33
6. Product Regulatory Requirements...................................................................................34
6.1 Product Regulatory Requirements......................................................................... 34
6.2 Product Regulatory Compliance and Safety Markings .......................................... 34
6.3 Product Environmental/Ecology Requirements ..................................................... 34
Appendix A: Integration and Usage Tips................................................................................35
Appendix B: Integrated BMC Sensor Tables..........................................................................36
Appendix C: POST Error Messages and Handling ................................................................42
Appendix D: Supported Intel®Modular Server System.........................................................46
Glossary.....................................................................................................................................47
Reference Documents..............................................................................................................50

Intel® Compute Module MFS5520VI TPS List of Figures
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Intel order number: E64311-007
List of Figures
Figure 1. Component and Connector Location Diagram ..............................................................3
Figure 2. Intel®Compute Module MFS5520VI Front Panel Layout............................................... 4
Figure 3. Intel®Compute Module MFS5520VI – Hole and Component Positions ........................ 5
Figure 4. Intel®Compute Module MFS5520VI Functional Block Diagram .................................... 6
Figure 5. Unified Retention System and Unified Backplate Assembly........................................ 10
Figure 6. DIMM Nomenclature.................................................................................................... 12
Figure 7. DIMM Slot Order.......................................................................................................... 12
Figure 8. Integrated BMC Hardware ........................................................................................... 20
Figure 9. Recovery Jumper Blocks ............................................................................................. 31
Figure 10. Intel®Modular Server System MFSYS25 .................................................................. 46

List of Tables Intel® Compute Module MFS5520VI TPS
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List of Tables
Table 1. Intel compute module MFS5520VI Feature Set.............................................................. 2
Table 2. Mixed Processor Configurations ..................................................................................... 8
Table 3. Mirroring DIMM Population Rules Variance across Nodes........................................... 15
Table 4. Intel®Compute Module MFS5520VI PCI Bus Segment Characteristics....................... 18
Table 5. Video Modes ................................................................................................................. 21
Table 6. Board Connector Matrix ................................................................................................ 23
Table 7. Power Connector Pin-out (J1A1) .................................................................................. 23
Table 8. VGA Connector Pin-out (J6A1)..................................................................................... 24
Table 9. 120-pin I/O Mezzanine Card Connector Pin-out ........................................................... 25
Table 10. 120-pin I/O Mezzanine Card Connector Signal Definitions......................................... 26
Table 11. 40-pin I/O Mezzanine Card Connector Pin-out ........................................................... 28
Table 12. 96-pin Midplane Signal Connector Pin-out ................................................................. 28
Table 13. Internal 9-pin Serial Header Pin-out (J9J1)................................................................. 29
Table 14. External USB Connector Pin-out ................................................................................30
Table 15. Pin-out of Internal USB Connector for low-profile Solid State Drive (J9B7)................ 30
Table 16. Recovery Jumpers ......................................................................................................32
Table 17. MFS5520VI Sensors................................................................................................... 37
Table 18. POST Error Messages and Handling.......................................................................... 42

Intel® Compute Module MFS5520VI TPS List of Tables
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Intel® Compute Module MFS5520VI TPS Introduction
Revision 1.5 1
Intel order number: E64311-007
1. Introduction
This Technical Product Specification (TPS) provides board-specific information detailing the
features, functionality, and high-level architecture of the Intel®Compute Module MFS5520VI.
1.1 Chapter Outline
This document is divided into the following chapters:
•Chapter 1 – Introduction
•Chapter 2 – Product Overview
•Chapter 3 – Functional Architecture
•Chapter 4 – Connector/Header Locations and Pin-outs
•Chapter 5 – Jumper Block Settings
•Chapter 6 – Product Regulatory Requirements
•Appendix A – Integration and Usage Tips
•Appendix B – BMC Sensor Tables
•Appendix C – Post Error Messages and Handling
•Appendix D – Supported Intel®Modular Server System
•Glossary
•Reference Documents
1.2 Intel®Compute Module Use Disclaimer
Intel®Modular Server components require adequate airflow to cool. Intel ensures through its
own chassis development and testing that when these components are used together, the fully
integrated system will meet the intended thermal requirements. It is the responsibility of the
system integrator who chooses not to use Intel-developed server building blocks to consult
vendor datasheets and operating parameters to determine the amount of airflow required for
their specific application and environmental conditions. Intel Corporation cannot be held
responsible if components fail or the system does not operate correctly when used outside any
of their published operating or non-operating limits.

Product Overview Intel® Compute Module MFS5520VI TPS
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2. Product Overview
The Intel®Compute Module MFS5520VI is a monolithic printed circuit board with features that
were designed to support the high-density compute module market.
2.1 Intel®Compute Module MFS5520VI Feature Set
Table 1. Intel compute module MFS5520VI Feature Set
Feature Description
Processors Support for one or two Intel®Xeon®Processor 5500 series or two Intel®Xeon®
Processor 5600 series in FC-LGA 1366 Socket B package with up to 95 W Thermal
Design Power (TDP).
4.8 GT/s, 5.86 GT/s, and 6.4 GT/s Intel®QuickPath Interconnect (Intel®QPI)
Enterprise Voltage Regulator-Down (EVRD) 11.1
Memory Support for 1066/1333 MT/s ECC registered (RDIMM) or unbuffered (UDIMM)
DDR3 memory.
12 DIMMs total across 6 memory channels (3 channels per processor).
Note: Mixed memory is not tested or supported. Non-ECC memory is not tested and is
not supported in a server environment.
Chipset Intel®5520 Chipset IOH
Intel®82801JR I/O Controller Hub (ICH10R)
On-board
Connectors/Headers
External connections:
Four USB 2.0 ports
DB-15 Video connector
Internal connectors/headers:
One low-profile USB 2x5 pin header to support low-profile USB solid state drives
Intel®I/O Mezzanine connectors supporting Dual Gigabit NIC Intel®I/O Expansion
Module (Optional)
On-board Video On-board ServerEngines* LLC Pilot II Controller
Integrated 2D Video Controller
64 MB DDR2 Memory
On-board Hard Drive
Controller
LSI* 1064e SAS controller
LAN Two integrated 1000 Ethernet ports and two optional 1000 Ethernet ports, provided by
the Dual Gigabit NIC mezzanine module.

Intel® Compute Module MFS5520VI TPS Product Overview
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2.2 Compute Module Layout
2.2.1 Connector and Component Locations
The following figure shows the board layout of the Intel®Compute Module MFS5520VI. Each
connector and major component is identified by a number or letter. A description of each
identified item is provided below the figure.
AF003077
J
Q
F
B
G
H
PON
L
M
A
C
E
D
I
K
M
A Intel®5520 Chipset I/O Hub J CPU 2 Socket
B CPU2 DIMM Slots K Power/Fault LEDs
C Mezzanine Card Connector 1 L Power Switch
D CPU 1 with Heatsink M Activity and ID LEDs
E Mezzanine Card Connector 2 N Video Connector
F Midplane Power Connector O USB Ports 2 and 3
G Midplane Signal Connector P USB1 Ports 0 and 1
H Midplane Guide Pin Receptacle Q CMOS Battery
I CPU 1 DIMM Slots
Figure 1. Component and Connector Location Diagram
2.2.2 External I/O Connector Locations
The following drawing shows the layout of the external I/O components for the Intel®Compute
Module MFS5520VI.

Product Overview Intel® Compute Module MFS5520VI TPS
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AF003120
AC
BHI
DE F G
A USB ports 0 and 1 F Hard Drive Activity LED
B USB ports 2 and 3 G ID LED
C Video H Power button
D I/O Mezzanine NIC ports 1 and
2 LEDs
I Power and Fault LEDs
E NIC ports 1 and 2 LEDs
Figure 2. Intel®Compute Module MFS5520VI Front Panel Layout

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2.2.3 Compute Module Mechanical Drawings
AF003121
357.34
.000
120.65
.000
256.54
262.89
6.35
72.65
169.85
185.93
203.78
213.94
224.10
234.26
244.42
254.58
148.40
102.02
138.84 248.92
10.16
396.24 300.35
41.40
141.77
115.85
98.85
166.99
173.99
223.39
209.52
192.99
185.99
239.84
249.42
207.65
253.74
14.58
58.10
104.50
101.10
3.27
152.27
142.11
131.95
121.79
111.63
101.47
Figure 3. Intel®Compute Module MFS5520VI – Hole and Component Positions

Functional Architecture Intel® Compute Module MFS5520VI TPS
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3. Functional Architecture
The architecture and design of the Intel®Compute Module MFS5520VI is based on the Intel®
5520 Chipset I/O Hub (IOH) and the Intel®82801JR ICH10 RAID. The chipset is designed for
systems based on the Intel®Xeon®Processor in FC-LGA 1366 socket B package with Intel®
QuickPath Interconnect (Intel®QPI). The chipset contains two main components:
Intel®5520 Chipset I/O Hub (IOH) that provides a connection point between various I/O
components.
Intel®82801JR, which is the I/O controller hub (ICH10R) for the I/O subsystem.
This chapter provides a high-level description of the functionality associated with each chipset
component and the architectural blocks that make up the server board.
Primary
Mid-Plane Connector
22
FLASHFLASH
TPM
Opt - int in TB
DRAMDRAM
BMCBMC
2
4
SSI Compliant
Mezzanine
Flex IO
Connector
Figure 4. Intel®Compute Module MFS5520VI Functional Block Diagram

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3.1 Intel®Xeon®processor
3.1.1 Processor Support
The Compute Module supports the following processors:
One or two Intel®Xeon®Processor 5500 series with 4.8 GT/s, 5.86 GT/s or 6.4 GT/s
Intel®QPI link interface and Thermal Design Power (TDP) up to 95 W.
One or two Intel®Xeon®Processor 5600 series with a 6.4 GT/s Intel®QPI link interface
and Thermal Design Power (TDP) up to 95 W.
Previous generations of the Intel®Xeon®processors are not supported on the compute module.
3.1.1.1 Processor Population Rules
Note: Although the Compute Module does support dual-processor configurations consisting of
different processors that meet the defined criteria below, Intel does not perform validation
testing of this configuation. For optimal performance in dual-processor configurations, Intel
recommends that identical processors be installed.
When using a single processor configuration, the processor must be installed into the processor
socket labeled CPU1. A terminator is not required in the second processor socket when using a
single processor configuration.
When two processors are installed, the following population rules apply:
Both processors must be of the same processor family.
Both processors must have the same front-side bus speed.
Both processors must have the same cache size.
Processors with different speeds can be mixed in a system, given the prior rules are met.
If this condition is detected, all processor speeds are set to the lowest common
denominator (highest common speed) and an error is reported.
Processor stepping within a common processor family can be mixed as long as it is
listed in the processor specification updates published by Intel Corporation.
3.1.2 Mixed Processor Configuration
The following table describes mixed processor conditions and recommended actions for the
Intel®Compute Module MFS5520VI. Errors fall into one of the following categories:
Fatal: If the compute module can boot, it pauses at a blank screen with the text
“Unrecoverable fatal error found. System will not boot until the error is resolved”
and “Press <F2> to enter setup”, regardless of whether the “Post Error Pause” setup
option is enabled or disabled. When the operator presses the F2 key on the keyboard,
the error message is displayed on the Error Manager screen, and an error is logged with
the error code. The compute module cannot boot unless the error is resolved. The user
needs to replace the faulty part and restart the system.
Major: If the “Post Error Pause” setup option is enabled, the compute module goes
directly to the Error Manager to display the error and log the error code. Otherwise, the
compute module continues to boot and no prompt is given for the error, although the
error code is logged to the Error Manager.

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Minor: The message is displayed on the screen or on the Error Manager screen. The
system continues booting in a degraded state. The user may want to replace the
erroneous unit. The POST Error Pause option setting in the BIOS setup does not have
any effect on this error.
Table 2. Mixed Processor Configurations
Error Severity System Action
Processor family not
Identical
Fatal The BIOS detects the error condition and responds as follows:
Logs the error.
Alerts the Integrated BMC about the configuration error.
Does not disable the processor.
Displays “0194: Processor 0x family mismatch detected”
message in the Error Manager.
Takes Fatal Error action (see above) and will not boot until the
fault condition is remedied.
Processor cache not
identical
Fatal The BIOS detects the error condition and responds as follows:
Logs the error.
Alerts the Integrated BMC about the configuration error.
Does not disable the processor.
Displays “0192: Processor 0x cache size mismatch detected”
message in the Error Manager.
Takes Fatal Error action (see above) and will not boot until the
fault condition is remedied.
Processor frequency (speed)
not identical
Fatal The BIOS detects the error condition and responds as follows:
Adjusts all processor frequencies to lowest common
denominator.
No error is generated – this is not an error condition.
Continues to boot the system successfully.
If the frequencies for all processors cannot be adjusted to be the
same, then the BIOS:
Logs the error.
Displays “0197: Processor 0x family is not supported” message in
the Error Manager.
Takes Fatal Error action (see above) and will not boot until the
fault condition is remedied.
Processor Intel®QuickPath
Interconnect speeds not
identical
Major The BIOS detects the error condition and responds as follows:
Adjusts all processor interconnect frequencies to lowest common
denominator.
Logs the error.
Alerts the Integrated BMC about the configuration error.
Does not disable the processor.
Displays “0195: Processor 0x Intel(R) QPI speed mismatch”
message in the Error Manager.
If POST Error Pause is disabled in the Setup, continues to boot in
a degraded state.
If POST Error Pause is enabled in the Setup, pauses the system,
but can continue to boot if operator directs.

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Error Severity System Action
Processor microcode
missing
Minor The BIOS detects the error condition and responds as follows:
Logs the error.
Does not disable the processor.
Displays “8180: Processor 0x microcode update not found”
message in the Error Manager or on the screen.
The system continues to boot in a degraded state, regardless of
the setting of POST Error Pause in the Setup.
3.1.3 Turbo Mode
The Turbo Mode feature allows processors to program thresholds for power/current which can
increase platform performance by 10%.
If the processor supports this feature, the BIOS setup provides an option to enable or disable
this feature. The default is enabled.
3.1.4 Hyper-Threading
Most Intel®Xeon®processors support Intel®Hyper-Threading Technology. The BIOS detects
processors that support this feature and enables the feature during POST.
If the processor supports this feature, the BIOS Setup provides an option to enable or disable
this feature. The default is enabled.
3.1.5 Intel®QuickPath Interconnect
Intel®QPI is a cache-coherent, link-based interconnect specification for processor, chipset, and
I/O bridge components. Intel®QPI provides support for high-performance I/O transfer between
I/O nodes. It allows connection to standard I/O buses such as PCI Express*, PCI-X, PCI
(including peer-to-peer communication support), AGP, and so on, through appropriate bridges.
Each Intel®QPI link consists of 20 pairs of uni-directional differential lanes for the transmitter
and receiver, plus a differential forwarded clock. A full-width Intel®QPI link pair consists of 84
signals (20 differential pairs in each direction plus a forwarded differential clock in each
direction). Each Intel®Xeon®Processor 5500 series and Intel®Xeon®Processor 5600 series
processors support two Intel®QPI links, one going to the other processor and the other to the
Intel®5520 IOH.
In the current implementation, Intel®QPI ports are capable of operating at transfer rates of up to
6.4 GT/s. Intel®QPI ports operate at multiple lane widths (full - 20 lanes, half - 10 lanes, quarter
- 5 lanes) independently in each direction between a pair of devices communicating through
Intel®QPI. The Compute Module supports full width communication only.

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3.1.6 Unified Retention System Support
The Compute Module complies with Intel’s Unified Retention System (URS) and the Unified
Backplate Assembly. The Compute Module ships with a made-up assembly of Independent
Loading Mechanism (ILM) and Unified Backplate at each processor socket.
The URS retention transfers load to the Compute Module through the unified backplate
assembly. The URS spring, captive in the heatsink, provides the necessary compressive load
for the thermal interface material. All components of the URS heatsink solution are captive to
the heatsink and only require a Philips* screwdriver to attach to the unified backplate assembly.
See the following figure for the stacking order of the URS components.
.
AF002699
Heatsink
Screw
Compression Spring
Retention Cup
Thermal Interface Material (TIM)
Retaining Ring
Server Board
Heatsink
Attach Studs
ILM Attach Studs Unified Backplate
ILM and Socket
Figure 5. Unified Retention System and Unified Backplate Assembly

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3.2 Memory Subsystem
3.2.1 Intel®QuickPath Memory Controller
The Intel®Xeon®Processor 5500 series and Intel®Xeon®Processor 5600 series have an
integrated memory controller, the Intel®QuickPath Memory Controller, in its package. The
memory controller supports DDR3 1333/1066/800 ECC registered DIMMs (RDIMMs) and ECC
unbuffered DIMMs (UDIMMs).
3.2.1.1 Intel®Compute Module MFS5520VI Supported Memory
The Intel®Compute Module MFS5520VI has 12 DIMM sockets and supports the following
memory features:
Six DDR3 memory channels (three per processor socket) with two DIMMs per channel,
thereby supporting up to 12 DIMMs with dual-processor sockets
DDR3 1333 MHz and DDR3 1066 MHz memory modules
Single–Rank (SR) and Dual–Rank (DR) ECC Registered (RDIMMs) or ECC Unbuffered
(UDIMMs) DDR3 memory modules
Quad–Rank (QR) ECC Registered (RDIMMs) DDR3 memory modules
Maximum memory capacity of 192 GB with two processors installed
Use of identical DIMMs in the compute module is recommended
The following configurations are not validated or supported with the Intel®Compute Module
MFS5520VI:
Mixing of RDIMMs and UDIMMs is not supported
Mixing memory type, size, speed and/or rank on this server board is not validated and is
not supported
Mixing memory vendors is not validated and is not supported on this server board
Non-ECC memory is not validated and is not supported in a server environment
For a complete list of supported memory for the Intel®Compute Module MFS5520VI, refer to the
Tested Memory List published in the Intel®Server Configurator Tool.
3.2.2 Publishing Compute Module Memory
The BIOS displays the “Total Memory” of the compute module during POST if Display
Logo is disabled in the BIOS setup. This is the total size of memory discovered by the
BIOS during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in
the system.
The BIOS displays the “Effective Memory” of the compute module in the BIOS setup.
The term Effective Memory refers to the total size of all DDR3 DIMMs that are active (not
disabled) and not used as redundant units.
The BIOS provides the total memory of the compute module in the main page of the
BIOS setup. This total is the same as the amount described by the first bullet above.
If Display Logo is disabled, the BIOS displays the total system memory on the diagnostic
screen at the end of POST. This total is the same as the amount described by the first
bullet above.

Functional Architecture Intel® Compute Module MFS5520VI TPS
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3.2.3 Memory Map and Population Rules
The nomenclature for DIMM sockets implemented on the Intel®Compute Module MFS5520VI is
detailed in the following figures.
Processor Socket 1 Processor Socket 2
Channel A Channel B Channel C Channel D Channel E Channel F
A1 A2 B1 B2 C1 C2 D1 D2 E1 E2 F1 F2
Figure 6. DIMM Nomenclature
AF003098
DIMM B2
DIMM A1
DIMM A2
DIMM B1
DIMM C2
DIMM C1
DIMM F1
DIMM F2
DIMM E1
DIMM D2
DIMM D1
DIMM E2
Figure 7. DIMM Slot Order
3.2.3.1 Memory Subsystem Nomenclature
DIMMs are organized into physical slots on DDR3 memory channels that belong to
processor sockets.
The memory channels from processor socket 1 are identified as Channel A, B, and C.
The memory channels from processor socket 2 are identified as Channel D, E, and F.

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The compute module Quick Reference Label DIMM slot identifiers provide information
about the channel, and therefore the processor to which they belong. For example,
DIMM_A1 is the first slot on Channel A on processor 1; DIMM_D1 is the first DIMM
socket on Channel D on processor 2.
The memory slots associated with a given processor are unavailable if the given
processor socket is not populated.
A processor may be installed without populating the associated memory slots provided a
second processor is installed with associated memory. In this case, the memory is
shared by the processors. However, the platform suffers performance degradation and
latency due to the remote memory.
Processor sockets are self-contained and autonomous. However, all memory subsystem
support (that is, Memory RAS, Error Management, and so on) in the BIOS setup are
applied commonly across processor sockets.
3.2.4 Memory RAS
3.2.4.1 RAS Features
The Compute Module supports the following memory RAS features:
Channel Independent Mode
Channel Mirroring Mode
The memory RAS offered by the Intel®Xeon®Processor 5500 series and Intel®Xeon®
Processor 5600 series processors is done at channel level, that is, during mirroring, channel B
mirrors channel A. All DIMM matching requirements are on a slot to slot basis on adjacent
channels. For example, to enable mirroring, corresponding slots on channel A and channel B
must have DIMMs of identical parameters.
If one socket fails the population requirements for RAS, the BIOS sets all six channels to the
Channel Independent mode.
The memory slots of DDR3 channels from the Intel®Xeon®Processor 5500 series and Intel®
Xeon®Processor 5600 series processors should be populated on a farthest first fashion. This
holds true even in the Channel Independent mode. This means that A2 cannot be
populated/used if A1 is empty.
3.2.4.2 Channel Independent Mode
In the Channel Independent mode, multiple channels can be populated in any order (for
example, channels B and C can be populated while channel A is empty). Therefore, all DIMMs
are enabled and utilized in the Channel Independent mode.
3.2.4.3 Channel Mirroring Mode
The Intel®Xeon®Processor 5500 series and Intel®Xeon®Processor 5600 series support
channel mirroring to configure available channels of DDR3 DIMMs in the mirrored configuration.
The mirrored configuration is a redundant image of the memory, and can continue to operate
despite the presence of sporadic uncorrectable errors.
Channel mirroring is a RAS feature in which two identical images of memory data are
maintained, thus providing maximum redundancy. On the Intel®Xeon®Processor 5500 series
and Intel®Xeon®Processor 5600 series processors based Intel®server boards, mirroring is