IRT DDA-3301 User manual

3301-dda.ib.doc page 1 of 20 06/01/2004
IRT Eurocard
Types DDA-3301
G.703 Data Distribution Amplifiers
&
ZDA-3301RH
Handshake changeover assembly
I R T Electronics Pty Ltd A.B.N. 35 000 832 575
26 Hotham Parade, ARTARMON N.S.W. 2064 AUSTRALIA
National: Phone: [phone] Fax: [phone]
International: [phone] [phone]
Email: [e-mail]
Web: www.irtelectronics.com
Designed and manufactured in Australia
IRT can be found on the Internet at:
http://www.irtelectronics.com

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IRT Eurocard
Type DDA-3301
G.703 Data Distribution Amplifiers
&
ZDA-3301RH
Handshake changeover assembly
Instruction Book
Table of Contents
Section Page
General description 3
Functional diagrams 5
Technical specifications 6
Electrical characteristics of G.703 signals 9
Characteristics of signal types 10
Coding characteristics 10
G.703 data signal format 10
Description of operation 12
Handshake operation 14
Pre-installation 16
Operational safety 16
Internal adjustments 17
Installation 17
Installation in frame 17
Front & rear panel diagrams 18
Warranty & service 19
Equipment return 19
Drawing index 20
This instruction book applies to units later than S/N 0309251.

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IRT Eurocard
Types DDA-3301
G.703 Data Distribution Amplifiers
&
ZDA-3301RH
Handshake changeover assembly
General description
The DDA-3000 series of data distribution amplifiers are intended for use with data signals conforming to the ITU
Rec. G.703. Due to the fixed rates of the G.703 specification it is necessary to specify the G.703 data rate when
ordering so that the appropriate timing components, coding and levels are set in accordance with the standard.
For ease of reference the different amplifiers are called by the same designation with a suffix to indicate the rate.
This does not indicate that a product at one data rate can be readily changed to a different rate, but rather that that
they perform similar functions.
Some of the Data Distribution Amplifiers (DDA’s) in the series are primarily designed to work as stand alone
DDA’s whilst others are intended primarily for use in redundant path switching applications.
The DDA-3301 is currently available in 8, 34 and 45 Mb/s G.703 rates and is primarily intended for use in pairs
with a double width rear assembly (ZDA-3301RH) for automatic path protection applications.
Three outputs are provided at the rear of the module with an additional output for monitoring purposes on the front
panel. The primary output is controlled by relays to provide a bypass signal from the input in the event of a power
failure.
Indicators are provided on the front panel for: Data loss
AIS detect (Alarm Indication Signal)
Module in service
Module in standby.
External alarm signals are also available on the rear of the module.
Changeover inhibit and changeover request switches are provided on the front panel for use where modules are
linked in pairs for redundancy. For this configuration a special handshake connector is provided on the rear panel to
link the logic sections of two modules.
When used as a line equaliser or distribution amplifier the DDA may be housed in any of IRT’s standard Eurocard
frames. When used in pairs for handshake operation only 3 RU chassis types may be used so that the two modules
are as close together as possible. The double width rear assemblies are designed specifically for this purpose and
provide the best return loss characteristics. Cables should not be used to link two modules.
Details of frame types are available separately.
Applications:
• Stand alone cable equaliser or distribution amplifier
• Paired for redundant path protection switching
Standard features:
• Adaptive cable input equalisation
• Data regeneration & re-clocking
• Monitor facility
• Power fail bypass facility
• External alarms and bypass
• Redundancy handshake facility
• IRT Eurocard construction compatible with other IRT Eurocard modules and frames
• Dual power supply operation

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Equipment provided:
Standard: DDA-3301/XX Data distribution amplifier module.
(Where XX is the G.703 data rate)
ZDA-3301 Rear assembly for stand alone DDA-3301.
Accessories available:
ZDA-3301RH Double rear assembly for handshake: Connects two adjacent DDA-3301’s for automatic
changeover of all three outputs in the event of a fault
being detected. Note that the ZDA-3301RH
supersedes the earlier ZDA-3101RH.

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Functional diagrams
J 3
Handshake diagram 2 x DDA-3301
J 2
J 4
INPUT
RELAY
K 1.3 RELAY
K 1.2 OUTPUTS
DDA SIGNAL
PROCESSING
RELAYS
K 3, RL 1 & RL 2
INPUT
RELAY
K 1.3 RELAY
K 1.2
DDA SIGNAL
PROCESSING
RELAYS
K 3, RL 1 & RL 2
INPUT
J 1
RELAY
K 1.3
RELAY
K 1.2
OUTPUTS
RELAY
RL 1 J 3
RECLOCKING
AIS DETECTION
DATA FAIL
DETECTION
MAIN/SBY LOGIC
FOR K 3
CLOCK
&
DATA
RECOVERY
EQUALISER
Relay K 1 = Power fail bypass.
Relay K 3 = Magnetic latching Main/Sby.
CLOCK
+ MARKS
- MARKS
MON
.
Block diagram DDA-3301- Signal path
RELAY
K 3 J 2
RELAY
RL 2 J 4

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Technical specifications
DDA-3301/8:
Conforms to CCITT G.703 8448 Kb/s – see Electrical characteristics of G.703 signals.
Input:
Type Transformer coupled.
Impedance 75 Ωterminated.
Cable equalisation Automatic.
0 - 6 dB at 4,224 KHz. Components set for Beldin YR23769 cable.
Outputs:
Type Transformer coupled.
Number 3 switched, regenerated, reclocked outputs located on rear connection
assembly and one located on front panel.
Impedance 75 Ωsource terminated.
DDA-3301/34:
Conforms to CCITT G.703 34368 Kb/s – see Electrical characteristics of G.703 signals.
Input:
Type Transformer coupled.
Impedance 75 Ωterminated.
Cable equalisation Automatic.
0 - 12 dB at 17,184 KHz. Components set for Beldin YR23769 cable.
Outputs:
Type Transformer coupled.
Number 3 switched, regenerated, reclocked outputs located on rear connection
assembly and one located on front panel.
Impedance 75 Ωsource terminated.
DDA-3301/45:
Generally in accord with CCITT G.703 44736 Kb/s – see Electrical characteristics of G.703 signals.
Input:
Type Transformer coupled.
Impedance 75 Ωterminated.
Equalisation Automatic for up to 400 m of Belden 8281 equivalent.
Outputs:
Type Transformer coupled.
Number 3 switched, regenerated, reclocked unshaped outputs located on rear
connection assembly and one located on front panel.
Impedance 75 Ωsource terminated.
Electrical Characteristics:
Cable Type Coaxial
Impedance 75 Ω
Signal level 1.0 V
Pulse Shape Unshaped, scaled from fig. 17/G.703
Nominal pulse width 14.55 ns
Code conversion B3ZS
Jitter at input port § 3 of recommendation G.823
Jitter at output port § 2 of recommendation G.823
Return loss at input ports:
860 KHz to 1720 KHz 12 dB
1720 KHz to 34368 KHz 18 dB
34368 KHz to 51550 KHz 14 dB

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Common data:
(Applies to all versions)
Controls & alarms:
Input:
External changeover request A ground applied to this input will emulate the operation of the front panel switch
“Change Request”
Outputs:
Bypass Contact closure to ground if power has failed
General alarm Contact closure to ground if
a. Data Loss is detected OR
b. AIS is detected AND the AIS disable link (LK 1) is not installed
AIS detection is defined as at least 2048 consecutive data “1”s
Data Loss is defined as less than 120 data “1”s in 512 G.703 data rate clock
periods
Connectors: Data: BNC
Alarm: Krone LSA plus
Indicators: DC power
Data loss
AIS detect
Module in service
Module in standby
Power requirements 28 Vac CT (14-0-14) or ±16 Vdc
Power consumption 170 mA. (5.5 VA)
Temperature range 0 - 50° C ambient
Mechanical Suitable for mounting in IRT 19" rack chassis types with input output and power
connections on the rear panel
Finish: Front panel: Grey background, black lettering & red IRT logo
Rear assembly: Detachable silk-screened PCB with direct mount connectors to Eurocard and
external signals
Dimensions 6 HP x 3 U x 220 mm IRT Eurocard
Standard accessories Rear connector assembly

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ZDA-3301RH Technical specifications
Controls & alarms:
Input:
External changeover request A ground applied to this input will emulate the operation of the front panel
switch “Change Request”.
Outputs:
Bypass Contact closure to ground if power has failed.
General Alarm Contact closure to ground if
a. Data Loss is detected OR
b. AIS is detected AND the AIS disable link (LK 1) is not installed.
AIS detection is defined as at least 2048 consecutive data “1”s.
Data Loss is defined as less than 120 data “1”s in 512 G.703 data rate clock
periods.
In Service (Main) Path Indication: Transistor switch to ground if card is Main (if DA version is equipped).
Connectors: Data: BNC.
Alarm: Krone LSA plus.
In Service (Main) Path: Krone LSA plus.
Changeover logic:
A changeover to the companion module will occur under any of the following conditions:
Loss of input signal
AIS detection alarm (provided AIS is not disabled by link LK 1)
Loss of power
In all of the above cases switching will only occur if
companion module is able to provide an output free of the same defects and
changeover inhibit switch is not activated on either module.
Priority logic:
The priority switching in normal mode follows non-reverting logic, which dictates:
In the event of failure of main then standby DDA will assume control and become Main causing the failed
path DDA to become Standby.
This implies that when the failed path is restored that it will remain as Standby and not become Main unless either a
failure of Main occurs or a manual changeover is requested.
Power on reset.
When power is applied to the pair, the power on reset signal will set the module which was last enabled as Main as
Main and the other module will be forced to act as Reserve.
When power is applied to a pair for the first time it may be necessary to force the desired module to become main by
pressing the Change Request button on the front panel of the desired module. The Main module will be indicated by
the In Service LED lighting on the front panel.

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Electrical characteristics of G.703 signals:
Electrical characteristics CCITT G.703 2048 Kb/s:
Pair each direction One coaxial pair.
Test load impedance 75 Ωresistive.
Signal level 2.37 V.
Nominal pulse width 244 ns.
Code conversion HDB3.
Pulse shape Fig. 15/G.703.
Jitter at input port § 3 of recommendation G.823.
Jitter at output port § 2 of recommendation G.823.
Return loss at input ports:
51 KHz to 102 KHz 12 dB.
102 KHz to 2048 KHz 18 dB.
2048 KHz to 3072 KHz 14 dB.
Electrical characteristics CCITT G.703 8448 Kb/s:
Pair each direction One coaxial pair
Test load impedance 75 Ωresistive
Signal level 2.37 V
Nominal pulse width 59 ns
Code conversion HDB3
Pulse shape Fig. 16/G.703
Jitter at input port § 3 of recommendation G.823
Jitter at output port § 2 of recommendation G.823
Return loss at input ports:
211 KHz to 422 KHz 12 dB
422 KHz to 8448 KHz 18 dB
8448 KHz to 12672 KHz 14 dB
Electrical characteristics CCITT G.703 34368 Kb/s:
Cable Type Coaxial
Impedance 75 Ω
Signal level 1.0 V
Nominal pulse width 14.55 ns
Code conversion HDB3
Pulse shape Fig. 17/G.703
Jitter at input port § 3 of recommendation G.823
Jitter at output port § 2 of recommendation G.823
Return loss at input ports:
860 KHz to 1720 KHz 12 dB
1720 KHz to 34368 KHz 18 dB
34368 KHz to 51550 KHz 14 dB
Electrical characteristics CCITT G.703 Shaped 44736 Kb/s:
Cable Type Coaxial
Impedance 75 Ω
Signal level
Power at 22368 KHz +1.8 dBm to +5.7 dBm.
Power at 44736 KHz >20 dBm below power at 22368 KHz.
Code conversion B3ZS
Pulse shape Fig. 14/G.703
Electrical characteristics CCITT G.703 Unshaped 44736 Kb/s:
Cable Type Coaxial
Impedance 75 Ω
Signal level 1.0 V
Pulse Shape Unshaped, scaled from fig. 17/G.703
Nominal pulse width 14.55 ns
Code conversion B3ZS
Jitter at input port § 3 of recommendation G.823
Jitter at output port § 2 of recommendation G.823
Return loss at input ports:
860 KHz to 1720 KHz 12 dB
1720 KHz to 34368 KHz 18 dB
34368 KHz to 51550 KHz 14 dB

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Characteristics of signal types
Coding characteristics - G.703:
The HDB3 (High Density Bi-polar of order 3) code as defined in G.703 for 34,368 Kb/s is as follows:
Binary 1 bits are represented by alternate positive and negative pulses and binary 0 bits by spaces. Exceptions
are made when strings of successive 0 bits occur in the binary signal.
Each block of 4 successive zeros is replaced by 000V or B00V where B is an inserted pulse of the correct
polarity and V is an inserted pulse violating the polarity rule. The choice of 000V or B00V is made so that
the number of B pulses between consecutive V pulses is odd so that successive V pulses are of alternate
polarity and so no DC component is introduced.
The B3ZS (Bipolar with Three Zero Substitution) (Also designated HDB2 - High Density Bi-polar of order 2) code
as defined in G.703 for 44,736 Kb/s is as follows:
Binary 1 bits are represented by alternate positive and negative pulses and binary 0 bits by spaces. Exceptions
are made when strings of successive 0 bits occur in the binary signal.
Each block of 3 successive zeros is replaced by 00V or B0V. The choice of 00V or B0V is made so that the
number of B pulses between consecutive V pulses is odd, so that successive V pulses are of alternate polarity
and so no DC component is introduced.
G.703 data signal format.
The following waveforms are intended to give some idea of the type of signal at various points in the DDA when in
operation. They are not intended as accurate portrayals of either voltage levels or timing.
It can be seen that the original signal has both positive and negative going pulses. This format is used so that the
signal does not rely on DC levels. To preserve the AC nature of the signal a coding system is used to ensure that a
succession of either ‘1’s or ‘0’s in the original data does not produce a DC output. The coding system varies
according to the type of G.703 signal (See specifications for each module and Coding characteristics above.)
It can be seen that the cable effected signal bears little resemblance to the original signal and due to the high
frequency attenuation looks more like a noisy analogue signal than a digital signal. The input equaliser circuit in the
DDA enhances the high frequency response and detects the rate of change of the signal to produce a squared up
signal with fast rise and fall times suitable for processing and re-clocking.
The signal is separated into +ve and -ve mark signals as shown. The relative timing of these signals must be closely
maintained or the final re-clocked output signal will not be accurate.
The re-clocking circuit acts on each of the +ve and -ve mark signals by detecting the data rate with a phase locked
loop which has a sufficiently long flywheel time to maintain the clock frequency in the presence of the maximum
length ‘0’ data signal.
The re-clocked +ve and -ve mark signals are fed to separate output drivers for each output where they are
recombined in the output transformers resulting in an output signal as shown which is the same as the original
signal.