IRT DDA-3280 User manual

3280-dda.ib.doc page 1 of 16 23/07/2002
IRT Eurocard
Types DDA-3280
2 Mb/s G.703 Data Distribution Amplifier
&
ZDA-3280RH
Handshake changeover assembly
I R T Electronics Pty Ltd A.B.N. 35 000 832 575
26 Hotham Parade, ARTARMON N.S.W. 2064 AUSTRALIA
National: Phone: [phone] Fax: [phone]
International: [phone] [phone]
Email: [e-mail]
Web: www.irtelectronics.com
Designed and manufactured in Australia
IRT can be found on the Internet at:
http://www.irtelectronics.com
IRT Communications
www.irtcommunications.com

3280-dda.ib.doc page 2 of 16 23/07/2002
IRT Eurocard
Type DDA-3280
2 Mb/s G.703 Data Distribution Amplifier
&
ZDA-3280RH
Handshake changeover assembly
Instruction Book
Table of Contents
Section Page
General Description 3
Functional Diagrams 4
Technical Specifications 5
DDA-3280 5
Electrical Characteristics CCIT G.703 2048 kb/s 5
ZDA-3280RH 6
Characteristics of signal 7
Coding Characteristics 7
G.703 Data Signal Format 7
Description of Operation 8
Handshake Operation 10
Pre-installation 12
Operational safety 12
Internal Adjustments 13
Installation 13
Installation in frame 13
Front & rear panel diagrams 14
Warranty & Service 15
Equipment return 15
Drawing index 16
This instruction book applies to units later than S/N 0201001.
IRT Communications
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3280-dda.ib.doc page 3 of 16 23/07/2002
IRT Eurocard
Types DDA-3280
2 Mb/s G.703 Data Distribution Amplifier
&
ZDA-3280RH
Handshake changeover assemblie
General Description
The DDA-3280 data distribution amplifier is intended for use with data signals conforming to the ITU Rec. G.703 at
the 2.048 Mb/s rate.
The DDA-3280 is primarily intended for use in pairs with a double width rear assembly (ZDA-3280RH) for
automatic path protection applications.
Three outputs are provided at the rear of the module with an additional output for monitoring purposes on the front
panel. The primary output is controlled by relays to provide a bypass signal from the input in the event of a power
failure.
Indicators are provided on the front panel for: Data loss
AIS detect (Alarm Indication Signal)
Module in service
Module in standby.
External alarm signals are also available on the rear of the module.
Changeover inhibit and changeover request switches are provided on the front panel for use where modules are
linked in pairs for redundancy. For this configuration the ZDA-3280RH dual rear assembly must be used.
When used as a line equaliser or distribution amplifier the DDA may be housed in any of IRT’s standard Eurocard
frames. When used in pairs for handshake operation only 3 RU chassis types may be used so that the two modules
are side by side. The double width rear assembly is designed specifically for this purpose and provides the best
return loss characteristics.
Details of frame types are available separately.
Applications:
• Stand alone cable equaliser or distribution amplifier
• Paired for redundant path protection switching
Standard features:
• Input cable loss to –6dB @ 1024 kHz
• Data regeneration & re-clocking
• Monitor facility
• Power fail bypass facility
• External alarms and bypass
• Redundancy handshake facility
• IRT Eurocard construction compatible with other IRT Eurocard modules and frames
• Dual power supply operation
Equipment provided:
Standard: DDA-3280 Data distribution amplifier module.
ZDA-3280 Rear assembly for stand alone DDA-3280.
Accessories available:
ZDA-3280RH Double rear assembly Connects two adjacent DDA-3280’s for automatic changeover of
for handshake: all three outputs in the event of a fault being detected.
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3280-dda.ib.doc page 4 of 16 23/07/2002
Functional Diagrams
J 3
Handshake diagram 2 x DDA-3280 with ZDA-3280RH
J 2
J 4
INPUT
1J1
RELAY
K 1.3 RELAY
K 1.2 OUTPUTS
DDA SIGNAL
PROCESSING
RELAYS
K 3, 1RL1 & 1RL2
INPUT
2J1 RELAY
K 1.3 RELAY
K 1.2
DDA SIGNAL
PROCESSING
RELAYS
K 3, 2RL1 & 2RL2
INPUT
J 1
RELAY
K 1.3
RELAY
K 1.2
OUTPUTS
J 4
RECLOCKING
AIS DETECTION
DATA FAIL
DETECTION
MAIN/SBY LOGIC
FOR K 3
Relay K 1 = Power fail bypass.
Relay K 3 = Magnetic latching Main/Stby.
- MARK
CLOCK
&
DATA
RECOVERY
CLOCK
+ MARK
MON
.
Block diagram DDA-3280- Signal path
RELAY
K 3 J 2
J 5
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3280-dda.ib.doc page 5 of 16 23/07/2002
Technical Specifications
DDA-3280:
2048 kb/s signal data:
Conforms to electrical characteristics CCITT G.703 2048 kHz synchronisation interface – see below.
Input:
Type Transformer coupled.
Impedance 75 Ωterminated.
Cable Loss 6 dB @ 1024 kHz (650m of Belden 8281).
Outputs:
Type Transformer coupled.
Number 3 switched, regenerated, reclocked outputs located on rear connection assembly
and one located on front panel.
Impedance 75 Ωsource terminated.
Controls & alarms: DC power
Data loss
Module in service
Module in standby
Bypass
General alarm
Changeover request.
Outputs:
Bypass Contact closure to ground if power has failed
General alarm Contact closure to ground if
a. Data Loss is detected OR
b. AIS is detected AND the AIS disable link (LK 1) is not installed
AIS detection is defined as at least 2048 consecutive data “1”s
Data Loss is defined as less than 120 data “1”s in 512 G.703 data rate clock
periods
Connectors: Data: BNC
Alarm: Krone LSA plus
Indicators: DC power
Data loss
AIS detect
Module in service
Module in standby
Other:
Power requirements 28 Vac CT (14-0-14) or ±16 Vdc
Power consumption 170 mA. (5.5 VA)
Temperature range 0 - 50° C ambient
Mechanical Suitable for mounting in IRT 19" rack chassis types with input output and power
connections on the rear panel
Finish: Front panel: Grey enamel, silk-screened black lettering & red IRT logo
Rear assembly: Detachable silk-screened PCB with direct mount connectors to Eurocard and
external signals
Dimensions 6 HP x 3 U x 220 mm IRT Eurocard
Standard accessories Rear connector assembly
Optional accessories Instruction manual.
Due to our policy of continuing development, these specifications are subject to change without notice.
Electrical characteristics CCITT G.703 2048 kb/s:
Pair each direction One coaxial pair.
Test load impedance 75 Ωresistive.
Signal level 2.37 Vp.
Nominal pulse width 244 ns.
Code conversion HDB3.
Pulse shape Fig. 15/G.703.
Jitter at input port § 3 of recommendation G.823.
Jitter at output port § 2 of recommendation G.823.
Return loss at input ports:
51 kHz to 102 kHz 12 dB.
102 kHz to 2048 kHz 18 dB.
2048 kHz to 3072 kHz 14 dB.
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3280-dda.ib.doc page 6 of 16 23/07/2002
ZDA-3280RH Technical Specifications
Controls & alarms:
Input:
External changeover request A ground applied to this input will emulate the operation of the front panel
switch “Change Request”.
Outputs:
Bypass Contact closure to ground if power has failed.
General Alarm Contact closure to ground if
a. Data Loss is detected OR
b. AIS is detected AND the AIS disable link (LK 1) is not installed.
AIS detection is defined as at least 2048 consecutive data “1”s.
Data Loss is defined as less than 120 data “1”s in 512 G.703 data rate clock
periods.
Connectors: Data: BNC.
Alarm: Krone LSA plus.
Changeover logic:
A changeover to the companion module will occur under any of the following conditions:
Loss of input signal
AIS detection alarm (provided AIS is not disabled by link LK 1)
Loss of power
In all of the above cases switching will only occur if
companion module is able to provide an output free of the same defects and
changeover inhibit switch is not activated on either module.
Priority logic:
The priority switching in normal mode follows non-reverting logic, which dictates:
In the event of failure of main then standby DDA will assume control and become Main causing the failed
path DDA to become Standby.
This implies that when the failed path is restored that it will remain as Standby and not become Main unless either a
failure of Main occurs or a manual changeover is requested.
Power on reset.
When power is applied to the pair, the power on reset signal will set the module which was last enabled as Main as
Main and the other module will be forced to act as Reserve.
When power is applied to a pair for the first time it may be necessary to force the desired module to become main by
pressing the Change Request button on the front panel of the desired module. The Main module will be indicated by
the In Service LED lighting on the front panel.
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3280-dda.ib.doc page 7 of 16 23/07/2002
Characteristics of signal
Coding characteristics - G.703:
The HDB3 (High Density Bi-polar of order 3) code as defined in G.703 for 2048 kb/s is as follows:
Binary 1 bits are represented by alternate positive and negative pulses and binary 0 bits by spaces. Exceptions
are made when strings of successive 0 bits occur in the binary signal.
Each block of 4 successive zeros is replaced by 000V or B00V where B is an inserted pulse of the correct
polarity and V is an inserted pulse violating the polarity rule. The choice of 000V or B00V is made so that
the number of B pulses between consecutive V pulses is odd so that successive V pulses are of alternate
polarity and so no DC component is introduced.
G.703 Data Signal Format.
The following waveforms are intended to give some idea of the type of signal at various points in the DDA when in
operation. They are not intended as accurate portrayals of either voltage levels or timing.
It can be seen that the original signal has both positive and negative going pulses. This format is used so that the
signal does not rely on DC levels. To preserve the AC nature of the signal a coding system is used to ensure that a
succession of either ‘1’s or ‘0’s in the original data does not produce a DC output. The coding system varies
according to the type of G.703 signal, HDB3 or B3ZS. 2048 kb/s signals are coded as HDB3 (See specification
characteristics above).
It can be seen that the cable effected signal bears little resemblance to the original signal and due to the high
frequency attenuation looks more like a noisy analogue signal than a digital signal.
The signal is separated into +ve and -ve mark signals as shown. The relative timing of these signals must be closely
maintained or the final re-clocked output signal will not be accurate.
The re-clocking circuit acts on each of the +ve and -ve mark signals by detecting the data rate with a ringing circuit,
which has a sufficiently ring time to maintain the clock frequency in the presence of the maximum length ‘0’ data
signal.
The re-clocked +ve and -ve mark signals are fed to separate output drivers for each output where they are
recombined in the output transformers resulting in an output signal as shown which is the same as the original
signal.
Original signal
Cable effected signal
Positive mark signal
Negative mark signal
Output signal
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3280-dda.ib.doc page 8 of 16 23/07/2002
Description of Operation
See block diagrams commencing on page 4 and schematic diagrams at rear of this manual.
Input:
The G.703 input signal is connected to the input circuit of the amplifier.
If no power is present, and the amplifier was active before the power was removed, then the signal will be directed
to the output connector via K 1 and K 3. When power is applied the K 1 relays operate and switch the signal via the
amplifier to the K 3 relay and thence the output connectors.
In this power fail mode, the connection from input to output is passive and so only one output can be connected.
The K 3 relay is of the bi-stable magnetic latching type and so will only change state when an imbalance of drive
occurs between the set and reset coils. The K 3 relay is operated under the control of the logic processor main select
via transistor driver Q 8 to the set coil and released by any external signal present via pin 15a of the rear connector
to the reset coil.
When power is applied to the DDA, the logic circuit will cause the K 3 relay to be set. If two DDA’s are connected
in handshake configuration, one of the two will take control first and become the main amplifier causing the other to
become the standby.
Either module can be made main by pressing the change request button on the front panel of the required module
provided that no alarms are present. An external changeover request may also be made via pin 3 of SK 2
alarm/control connector on the rear panel provided that the changeover inhibit switch on the front panel is not in the
inhibit position.
When the K 3 relay is in the reset position the input path from the input connector and the K 1 relay is terminated in
75 Ωto preserve the loading on the input.
Active path:
Input switching & equaliser:
The signal from the K 1a relay connects to the input transformer,T2, and data/clock recovery IC, U1, which
generates +ve and –ve mark signals and the received clock.
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3280-dda.ib.doc page 9 of 16 23/07/2002
Logic processing, reclocking and AIS detection:
The main logic processing, reclocking, error detection and operational interfacing are all performed by logic circuits
within U 4, which is a custom-programmed large scale logic array. The internal logic and functions of this IC are too
complex to describe in detail and the following is intended as a guide to function only.
Data loss detection:
Valid data is deemed to be present at the module input when 120 or more data pulses have been received in 512
nominal clock periods at the G.703 data bit rate specified for the DDA. In order for the data pulse to be counted,
more than 60% of the minimum anticipated data pulse must be present.
If less than 120 data pulses are counted over a period of 512 clock pulses then the data signal is deemed to be invalid
and the data loss flag is set.
If the area of a given pulse is less than 60% of the minimum anticipated (or acceptable) data pulse, after line
equalisation and shaping, then that pulse is not considered as a valid input to the count.
In any of these cases the Data Loss LED on the front panel of the module will light and the general alarm relay
output will be activated connecting the general alarm output contact to ground.
AIS detection:
The data processor will detect an incoming AIS (Alarm Indication Signal) (a series of >2048 1’s) and will set the
AIS flag and the general alarm relay output will be activated connecting the general alarm output contact to ground.
Note however that when data errors or no data is detected that the DDA-3280 does not generate an outgoing AIS
data stream to the data outputs.
The AIS alarm system may be disabled by a link on the main board LK 1. This prevents the AIS detection from
operating the automatic changeover function when used in handshake configuration and prevents AIS from setting
the general alarm output. The AIS detection circuit will, however, still provide AIS indication, on the front panel
LED, if AIS is detected.
The AIS disable link does not effect the general alarm being activated by data or signal loss as described above.
Power on reset:
When power is applied to the unit, U 6 generates a power on reset signal. This signal causes the processing circuit to
examine its current status and connections and restore operation to its state prior to power failure.
If the DDA is connected for stand-alone operation all alarms will be reset and normal operation will resume. If an
AIS signal is present on the data input or data is outside the prescribed limits outlined above then the general alarm
will be activated after the normal detection period has elapsed from the P.O.R. signal being initiated.
For operation in handshake mode see Handshake operation description.
ARA in & urgent alarm out.
These facilities are not enabled at this time.
Data signal output drivers.
The reclocked +ve and -ve mark signals are bussed to output drivers U 7 to 10.
Each output driver consists of three inverters operating in parallel in order to obtain a high current output capability
for driving the output transformer without stressing any individual amplifier.
Diodes are connected across the transformer primary to ground and the inverter output to +5V to prevent any back
EMF from causing damage to the drivers. The resistors between the output drivers and the output transformer set the
correct output operating pulse amplitude to ±2.37 V measured at the output connectors.
Note that the Mon. Output on the front panel of the module is obtained in the same manner as the outputs on the rear
of the module.
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3280-dda.ib.doc page 10 of 16 23/07/2002
Handshake Operation:
Purpose:
Handshake interconnection is required when two circuits are to be operated in 1:1 protection switching mode to
provide a continuous signal output in the event of failure of the primary signal path.
Priority logic:
For this mode to be employed it is necessary to provide two programme feeds which are designated as the Main and
Standby paths.
The priority switching in normal mode follows non-reverting logic, which dictates:
In the event of failure of main then standby DDA will assume control and become Main causing the failed
path DDA to become Standby.
This implies that when the failed path is restored that it will remain as Standby and not become Main unless either a
failure of Main occurs or a manual changeover is requested.
Changeover logic:
A changeover to the companion module will occur under any of the following conditions:
Loss of input signal
AIS detection alarm (provided AIS is not disabled by link LK 1)
Loss of power
In all of the above cases switching will only occur if:
the companion module is able to provide an output free of the same defects AND
the changeover inhibit switch is not activated on either module.
Connections:
Handshake interconnection should only be made using the handshake double rear assembly ZDA-3280RH.
This rear assembly makes all the necessary connections for both logic and data signals when two DDA’s are inserted
side by side in a 3 RU frame.
Individual alarm outputs are provided for each module.
Detailed operational description:
Connections for handshake (paired) operation of two DDA-3280’s are shown in the following diagram.
Inputs & outputs:
The two modules are supplied with signals from separate paths to their input connectors on the rear of the module.
For the purposes of description these are designated as the main and reserve inputs although they may be of equal
standing.
Logic connections:
All required logic connections are made by tracks on the double width PCB. Automatic operation is immediately
initiated when two modules are plugged into this type of rear assembly.
No external connections are required, but external alarm connections are available from each module for use if
desired. Additionally, each module has a connection for an external Make Main control for remote DA selection.
ZDA-3280RH handshake connections
(Three switched outputs)
Presen
t
8K2
SIGNAL
&
LOGIC
PROCESSING
4K7
+5
+12
Present
Loop
Status
Main select
4K7 4K7
4K7 8K2
+12
4K7
10R
K 3/2
K 3/1
10R
K 1a
EQUIP.
8K2
SIGNAL
&
LOGIC
PROCESSING
4K7
+12
Status Main select
4K7
4K7
4K7
+5
Loop
4K7
10R
K 3/2
K 3/1
+12
10R
K 1a
EQUIP.
RL 1 RL 1
J4
8K2
Main Input Reserve Input
Outputs
K 1b
75R
K 3 K 1b
J2
75R
K 3
J3
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3280-dda.ib.doc page 11 of 16 23/07/2002
Operation:
Handshake mode detection:
Two data lines are present on the module rear connector to indicate to each module that it is to operate in handshake
mode.
The Loop signal on pin 16a is connected to ground when another module is connected and the Present signal on pin
16b detects the presence of power on the alternate module.
If the Loop signal is not connected to ground then all handshake operations are inhibited.
If the loop signal is at ground indicating the presence of an alternate module and if power is present on both modules
then normal handshake operation is permitted. If the Present signal indicates that power is lost on the alternate
module then the module with power will take control and become Main.
Power on reset.
When power is applied to the pair the power on reset signal will attempt to reset both modules. However, as only
one module can be Main, the logic processor checks for handshake operation and if detected then the module which
was last enabled as Main will take control as Main and the other module will be forced to act as Reserve.
This memory capability is due to the latching nature of the K 3 relay, which will cause the Main and Reserve paths
to be maintained even in the absence of power.
The only exception to this rule is when power is applied to a pair for the first time that they are coupled in
handshake mode. In this special case both modules will initially have their K 3 relays in the active path condition
and so both will attempt to become Main. As the P.O.R. signal for each module will be slightly different for any two
modules, one will reach its operating mode first and will force the other module to immediately change to become
Reserve.
As the selection of which module becomes Main is cannot be determined before installation it may be necessary to
force the desired module to become main by pressing the Change Request button on the front panel of the desired
module. The Main module will be indicated by the In Service LED, on the front panel, lighting.
Automatic changeover:
An automatic changeover is initiated whenever the power fails on Main and not on Reserve or when a general alarm
is initiated on Main (indicating either loss of input signal or AIS indication if the AIS is enabled) and the Change
Inhibit switch is not active on either module.
In either case, the Main Status line will go from LO to HI. The companion module, on detecting this change, will
switch its Main Select line to HI. The K 3/1 relay driver then activates the relay (hence becoming Main) and sends
the Status line to the first module LO confirming the change and preventing that module from attempting to become
Main again.
Manual changeover:
A manual changeover is initiated by pressing the Change Request button on the front of the module that is required
to become Main.
The mechanism of the change is similar to the automatic changeover described above except that it is initiated by
the module requesting that it become Main. This forces the Status line to the other module to LO and it immediately
responds to become Reserve.
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3280-dda.ib.doc page 12 of 16 23/07/2002
Pre-installation:
Handling:
This equipment may contain or be connected to static sensitive devices and proper static free handling precautions
should be observed.
Where individual circuit cards are stored, they should be placed in antistatic bags. Proper antistatic procedures
should be followed when inserting or removing cards from these bags.
Power:
AC mains supply: Ensure that operating voltage of unit and local supply voltage match and that correct
rating fuse is installed for local supply.
DC supply: Ensure that the correct polarity is observed and that DC supply voltage is maintained
within the operating range specified.
Earthing:
The earth path is dependent on the type of frame selected. In every case particular care should be taken to ensure
that the frame is connected to earth for safety reasons. See frame manual for details.
Signal earth: For safety reasons a connection is made between signal earth and chassis earth. No attempt should be
made to break this connection.
Operational Safety:
WARNING
Operation of electronic equipment involves the use of voltages and currents that may
be dangerous to human life. Note that under certain conditions dangerous potentials
may exist in some circuits when power controls are in the OFF position.
Maintenance personnel should observe all safety regulations.
Do not make any adjustments inside equipment with power ON unless proper
precautions are observed. All internal adjustments should only be made by suitably
qualified personnel. All operational adjustments are available externally without the
need for removing covers or use of extender cards.
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3280-dda.ib.doc page 13 of 16 23/07/2002
Internal Adjustments
The only internal adjustment that may be made by the user is link LK 1, which may be set to disable AIS detection if
required.
This module uses a programmable logic device as the main processing circuit. This device must be correctly
programmed is only obtainable through IRT. No attempt should be made to substitute other devices or to
programme a similar device as this could cause extensive damage to the module.
Installation
Installation in frame or chassis:
See details in separate manual for selected frame type.
G.703 data connections - stand alone operation:
Connect the input and as many output connections as required.
Only good quality 75 Ohm connectors and cable should be used. The use of 50 Ohm BNC connectors may cause
serious reflection problems with G.703 signals, causing data errors.
In general cable runs should be kept as short as possible and should not exceed 600 metres for reliable error free
operation.
G.703 data connections - handshake operation:
See separate section on handshake operation.
Alarm and external changeover connections:
A Krone type connector is provided on the rear panel of the module providing the following:
Pin 1 K 1 relay status - connection to ground indicates module is in bypass mode.
2 K 2 relay status - connection to ground indicates module is Main in handshake mode.
3 External changeover request - connection to ground will make this module Main in
handshake mode.
4 Ground.
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3280-dda.ib.doc page 14 of 16 23/07/2002
Front & rear panel diagrams
The following front panel and rear assembly drawings are not to scale and are intended to show relative positions of
connectors, indicators and controls only.
MON.
ALLOW
INHIBIT
REQUEST
AIS
STANDBY
CHANGE
DATA
LOSS
IN
SERVICE
DDA-3280
N140
ZDA-3280RH
1
2
3
4
2SK 2
1J 2
MODULE 1
1J 3
MODULE 2
1J 4
1
2
3
4
2J 1 1J 1
INPUT
MODULE 2 INPUT MODULE 1
1SK 2
2RL1
2RL2
1RL1
1RL2
3280
1
2
3
4
SK 2 INPUT
O/P
J5
O/P
O/P
J4
J2
J1
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3280-dda.ib.doc page 15 of 16 23/07/2002
Warranty & service
Equipment is covered by a limited warranty period of three years from date of first delivery unless contrary
conditions apply under a particular contract of supply. For situations when “No Fault Found” for repairs, a
minimum charge of $A100.00 will apply, whether the equipment is within the warranty period or not.
Equipment warranty is limited to faults attributable to defects in original design or manufacture. Warranty on
components shall be extended by IRT only to the extent obtainable from the component supplier.
Equipment return:
Before arranging service ensure that the fault is in the unit to be serviced and not in associated equipment. If
possible, confirm this by substitution.
Before returning equipment contact should be made with IRT or your local agent to determine whether the
equipment can be serviced in the field or should be returned for repair.
The equipment should be properly packed for return observing antistatic procedures.
The following information should accompany the unit to be returned:
1. A fault report should be included indicating the nature of the fault
2. The operating conditions under which the fault initially occurred.
3. Any additional information which may be of assistance in fault location and remedy.
4. A contact name and telephone and fax numbers.
5. Details of payment method for items not covered by warranty.
6. Full return address.
7. For situations when “No Fault Found” for repairs, a minimum charge of $A100.00 will apply, whether
the equipment is within the warranty period or not.
Please note that all freight charges are the responsibility of the customer.
The equipment should be returned to the agent who originally supplied the equipment or, where this is not
possible, to IRT direct as follows.
Equipment Service
IRT Electronics Pty Ltd
26 Hotham Parade
ARTARMON
N.S.W.2064
AUSTRALIA
Phone: [phone] Fax: [phone]
Email: [e-mail]
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3280-dda.ib.doc page 16 of 16 23/07/2002
Drawing index
Drawing # Sheet # Description
804066 1 DDA-3280 2 Mb DA schematic part 1.
804066 2 DDA-3280 2 Mb DA schematic part 2.
804066 3 DDA-3280 2 Mb DA signal path block diagram.
804066 4 DDA-3280 2 Mb DA external logic block diagram.
804184 1 ZDA-3280RH Handshake rear assembly schematic.
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Title
SCALE
SIZE
Sheet
DRAWN CHECKED ENG. APP. Revision:
DO NOT COPY NOR
DISCLOSE TO ANY
THIRD PARTY
WITHOUT WRITTEN
CONSENT
of1
IRT Electronics Pty. Ltd.
Drawing No.
COPYRIGHT
ARTARMON NSW AUSTRALIA 2064
A3
N.T.S. 5
DDA-3280
804066
Date: 6-Feb-2002
27a 27b 5b
11a 11b 9a 9b
+5 +5 +5 +5
+5 +5
16b 17a
+5
+12
15a 14b 14a 15b
R S
+12
+12
18b 19b
+5 +5
19a 20a 20b
+5
ARA IN
INPUT EQUAL
&
CLOCK RECOVERY
/pmark OUTPUT
DRIVERS
U4
7064
KRONE
DC-DC CONV
21a/b 23a/b 22a/b 25a/b 24a/b 26a/b
11 43 12 16 17 19 18 14 21 32 25 24 27 26 4
5 29 28 20 40 41 34 33 38 39
rec_clock /mmark
/kpercent
xtal_in
ara_in
xtnl_co_req
gen_alarm
markpm
urgent_alarm
/ckd_pmark /ckd_mmark
+5
U6
MAX704
2 3
7
44 /por
10 22 30 42
+5
315 23 35
+5
+12
1
2
3U11
7812T
+12 +12 +12
18a
+5+5+5 +5
5a 16a
+12
+5
31 ais_disable
/loop present status main_select
make_main
/del_make_main
+12 +12
SK2
1 2 3 4
/11/13
+5
1
16 15
2
/main_tally6
+5
31a+12V
+12V
11
913
N/C
1
14
0123456789
+5V
DLY
10
31b
4.296MHz
K1.1 K2.1
12
U5A HC14S
34
U5B HC14S
Q8 NPN
21
D2 LS4148
J1 K1.2K1.3
21 R56 560 21 R57 560 21 R58 560 21 R59 560
21
R60 4K7
K2/1
GEN ALARM 21 R62
4K7
21
F1
4R7
21 F2
4R7
21 F3
4R7
21 F4
4R7
56
U5C HC14S
PB1
/make_main_req
SW1
/inhib_co
LD1
/dataloss_led
LD2
/ais_led
LD3
/in_service_led
LD4
/standby_led
21
R61 4K7
21 R65
10K
2 1
X1
21
R69
10M
2 1
R70 1K
2 1
R81
10K
21
R80 4K7
21
R68 10K
21
R67 4K7
21
R79
4K7
21
R78
4K7
21
D7 1N4148
2 1
D6 1N4148
21
D5 1N4148
21
R76 4K7
21 R75
8K2
21 R71
4K7
D8-11
1N4004
D12-15 1N4004
2 1
D17
2 1
D18
COAX1COAX2
COAX3
MON
21 R74
4K7
21
R73 8K2
21 R72
4K7
K1.3 K1.2 K1.1
POWER 2 1
D4
1N4148
J2
98
U5D HC14S
LK1
1 2
C52 22p
1 2
C53
22p
12
C64
2.2u
12
C61
10u
12
C63
100n
12
C62
100n
2 1
D16
3xLS4148
12
C77
100n
12
C78 10u
12
C79 10u
12
C76
470u
21 R93
33
1 2
C72 1500
1 2
C71 1500
12
C73
100n
12
C74
100n
12
C57
100n
12
C58
100n
Q7
2N2369A
12
C70
100n
12
C69
100n
12
C68 10u
12
C67
100n
12
C66
10u
12
C54
10u
21
R77
10
21 R94
10R
21
R95 4k7
2 1
R96
75
21 R63
270
1 2
L40 RFC
K3/2A
21 R66
1K
12
C75 100n
12
C56 4u7
12
3
DD9 BAV99
2 1
R82
100K
12
C55 1p
K3/2
21 R101
10R
21 D19
LS4148
K3/2B
1 2
L42 IND
1 2
L41 IND
1 2
C65 100n
12
C1
N/C
1 2
C2 1u
J4
J5
12
C86
100n
12
C87
100n
12
C89
100n
AMPLIFIER
2MB DISTRIBUTION
1 2 3
JP2
IRT Communications
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IRT Electronics Pty. Ltd.
Drawing No.
COPYRIGHT
ARTARMON NSW AUSTRALIA 2064
A3
N.T.S. 5
DDA-3280
804066
Date: 6-Feb-2002
OUTPUT DRIVE OUTPUT DRIVE OUTPUT DRIVE OUTPUT DRIVE
+5+5
GND = PIN 7 U1,U5,U7,U8,U9,U10
+5 +5+5
AMPLIFIER
+5+5+5
/ckd_pmark /ckd_mmark
/ckd_pmark
/ckd_mmark/ckd_mmark/ckd_mmark
+5 +5 +5 +5
1 2 3 4 5 6 7 8 910
11 12 13 14 15 16 17 18
+5V
1 3
6 5 4
/pmark /mmark rec clock
U4/11 U4/12 DLY
U1
XR5683
C1
+5V = PIN 14 U5,U7,U8,U9,U10
2MB DISTRIBUTION
/ckd_pmark /ckd_pmark
COAX311a
9a
3 4
+5V
K1.3/7
K1.2-7
12
C85 10u
12
C59 10u
12
C84 10u
12
C60
5x100n
12
C83
12
C82
12
C81
12
C80
2 1
3
DD3 BAV70
2 1
3
DD5 BAV70
2 1
3
DD7 BAV70
21
R1 300R
3 1
2
RV1
100k
12
C3 100n
12
C4 33p
12
C6 100n
12
C7 10u
12
C8 100n
12
C11 10u
12
C12 100n
T2
T4-6T
L1
48u CT
21
R2
18R
2 1
3
DD1
BAV70
12
C13
N/C
3 4
U7B
5 6
U7C
9 8
U7D
11 10
U7E
13 12
U7F
T3 PI718
21 R84
18R
21
R83
18R
21
R97
240R
21
3
DD2
BAW56
1 2
U7A
74HC04
1 2
U8A
74HC04
3 4
U8B
5 6
U8C
9 8
U8D
11 10
U8E
13 12
U8F
21
R86
18R
21
R98
240R
T4
PI718
21
R85 18R
21
3
DD4
BAW56
1 2
U9A
74HC04
3 4
U9B
5 6
U9C
9 8
U9D
11 10
U9E
13 12
U9F
21
R99
240R
21 R88
18R
21 R87
18R
21
3
DD6
BAW56
3 4
U10B
5 6
U10C
9 8
U10D
11 10
U10E
13 12
U10F
1 2
U10A
74HC04
T5
PI718 T6
PI718
21
R100 240R
21
3
DD8
BAW56
21 R89
18R
21
R90
18R
21
R3
1K8 21 R4
3K3
2 1
D1
BAS32 1 2
C9
100n
2 1
C5 70p
12
C11
10u
2
IRT Communications
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Title
SCALE
SIZE
Sheet
DRAWN CHECKED ENG. APP. Revision:
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THIRD PARTY
WITHOUT WRITTEN
CONSENT
of3
IRT Electronics Pty. Ltd.
Drawing No.
COPYRIGHT
ARTARMON NSW AUSTRALIA 2064
A3
N.T.S. 5
DDA-3280
804066
Date: 6-Feb-2002
CLOCK AND DATA
RECOVERY
CLOCK +MARK -MARK
AIS DETECTION
DATA FAIL
DETECTION
MAIN/SBY LOGIC
FOR K3
AMPLIFIER
2MB DATA DISTRIBUTION
BLOCK DIAGRAM DDA-3280 SIGNAL PATH
21
75R
J1 INPUT
J4 OUTPUT J5 OUTPUT
J2 OUTPUT
MON.
RELAY K3
RELAY K1a
RELAY K1b
IRT Communications
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Title
SCALE
SIZE
Sheet
DRAWN CHECKED ENG. APP. Revision:
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THIRD PARTY
WITHOUT WRITTEN
CONSENT
of4
IRT Electronics Pty. Ltd.
Drawing No.
COPYRIGHT
ARTARMON NSW AUSTRALIA 2064
A3
N.T.S. 5
DDA-3280
804066
Date: 6-Feb-2002
SIGNAL
&
LOGIC
PROCESSING
+5V +5V +5V +5V +5V
+5V
+12V K2
Gen.alarm
Make main Inhibit
Data loss LED AIS LED In service LED Standby LED
+12V
K1
+5V
__
__
__
__
+5V +5V
SK2 KRONE
Gen. alarm Ext C/O Req. Gnd
BLOCK DIAGRAM DDA-3280 EXTERNAL LOGIC
Power Fail
21
75R
J4 OUTPUT J5 OUTPUT J2 LOOP OUTPUT
INPUT RELAY
K3
RELAY K1a
MON.
21 4K7
21
4K7
21
4K7
21
4K7
K2
K1c
21 1K
12
2121
21 10K
RELAY K1b
AMPLIFIER
2MB DATA DISTRIBUTION
IRT Communications
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