Lattice Semiconductor CrossLink LIF-MD6000 User manual

CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
FPGA-EB-02010 Version 1.4
April 2018

CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02010-1.4
Contents
Acronyms in This Document .................................................................................................................................................3
1. Introduction ..................................................................................................................................................................4
2. Headers and Test Connections .....................................................................................................................................6
3. Programming Circuit .....................................................................................................................................................7
3.1. Bridging Circuit ....................................................................................................................................................7
3.2. I2C Expander ........................................................................................................................................................8
4. Power Supply ................................................................................................................................................................9
5. Status Indicators .........................................................................................................................................................11
6. SMA IO Link Board ......................................................................................................................................................12
7. Breakout IO Link Board ...............................................................................................................................................14
8. Ordering Information..................................................................................................................................................17
References ..........................................................................................................................................................................18
Technical Support Assistance...............................................................................................................................................18
Appendix A. LIF-MD6000-ML-EVN-BRD Schematics ...........................................................................................................19
Appendix B. LIF-MD6000-ML-EVN-BRD Bill of Materials ....................................................................................................27
Appendix C. SMA-IOL-EVN-BRD Schematics .......................................................................................................................33
Appendix D. SMA-IOL-EVN-BRD Bill of Materials................................................................................................................34
Appendix E. B-IOL-EVN-BRD Schematics.............................................................................................................................35
Appendix F. B-IOL-EVN-BRD Bill of Materials .....................................................................................................................36
Revision History...................................................................................................................................................................37
Figures
Figure 1.1. Top View of Master Link Board and its Key Components ...................................................................................4
Figure 1.2. Bottom View of Master Link Board.....................................................................................................................5
Figure 3.1. Programming Block.............................................................................................................................................7
Figure 3.2. Bridging Block .....................................................................................................................................................8
Figure 3.3. I2C Expander Block ..............................................................................................................................................8
Figure 4.1. Power Supply Block.............................................................................................................................................9
Figure 6.1. Top View of SMA IO Link Board ........................................................................................................................13
Figure 6.2. Bottom View of SMA IO Link Board ..................................................................................................................13
Figure 7.1. Top View of Breakout IO Link Board .................................................................................................................16
Figure 7.2. Bottom View of Breakout IO Link Board ...........................................................................................................16
Tables
Table 2.1. Headers and Test Connectors ..............................................................................................................................6
Table 4.1. Power LEDs...........................................................................................................................................................9
Table 4.2. Device Power Rail Summary and Test Points .....................................................................................................10
Table 5.1. Status LED I/O Map ............................................................................................................................................11
Table 6.1. Headers and Test Connectors ............................................................................................................................12
Table 6.2. U1 Connector Description..................................................................................................................................12
Table 7.1. Headers and Test Connectors ............................................................................................................................14
Table 7.2. U1 Connector Description..................................................................................................................................14
Table 7.3. J2 Header Description ........................................................................................................................................15
Table 8.1. Ordering Information .........................................................................................................................................17

CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.4 3
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
CMOS
Complementary Metal-Oxide Semiconductor
CSI-2
Camera Serial Interface
DSI
Display Serial Interface
FTDI
Future Technology Devices International
I2C
Inter-Integrated Circuit
IO
Input/Output
LVDS
Low-Voltage Differential Signaling
MIPI
Mobile Industry Processor Interface
SPI
Serial Peripheral Interface

CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02010-1.4
1. Introduction
This document describes the Lattice Semiconductor CrossLink™LIF-MD6000 Master Link board that supports a variety
of demos, encompassing different signaling logic standards bridging with MIPI®CSI-2/DSI interface. The board‘s key
component is the CrossLink Family device that features built in MIPI D-PHY hard blocks to support different bridging
solutions.
For the latest information about this board, including optional Tx/Rx Link boards, demo files, further documentation
and more, see the Lattice website at: www.latticesemi.com/masterlink
For details about the CrossLink device, refer to FPGA-DS-02007, CrossLink Family Data Sheet.
The content of this user guide includes descriptions of on-board jumper settings, programming circuit, a complete set
of schematics, and bill of materials for LIF-MD6000 Master Link board.
Refer to Appendix A, B, C, D, E, F for the schematics and BOM of the CrossLink LIF-MD6000 Master Link board and the
schematics and BOMs of the Breakout IO Link and SMA IO Link boards that are included in the demo kit.
Circuits on the development kit board:
Programming Circuit
Mini USB Type-B connector to FTDI
FTDI to CrossLink using SPI
FTDI to XO3LF device using JTAG
CrossLink
MIPI CSI-2/DSI hard block
Bridging of multiple signaling standards
SPI flash configuration
General Purpose Input/Output
LED display
LCMXO3LF-1300E
I2C muxing
Figure 1.1 shows the top view of the LIF-MD6000 Master Link board and its key components. Figure 1.2 on the next
page shows the bottom view of the board.
Tx Connector 1 & 2 (U9, U7)
Power Switch (SW1)
External Power Input
External Power Jack (J3)
LCMXO3L-1300E (U19)
USB 2.0 Mini-B (J2)
JTAG Header (J1)
FTDI Chip (U1)
SPI Flash Device (U14)
Rx Connectors (U11, U12)
Power LEDs
LIF-MD6000-CSFBGA81
Debug Header (J18)
Debug and
Configuration LEDs
Reset and wake-up buttons
Switch (SW2)
Clock Source Selection (J26, J27)
Bank 1, 2 Voltage Selection
Headers (J24, J25)
External Clock SMA Inputs
XO3 Reset (SW3)
Figure 1.1. Top View of Master Link Board and its Key Components

CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.4 5
Figure 1.2. Bottom View of Master Link Board

CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02010-1.4
2. Headers and Test Connections
Figure 1.1 shows the top view of the Master Link board. The headers and test connections on the board provide access
to LIF-MD6000 Master Link demo board circuits. Table 2.1 lists the headers and test connectors.
Table 2.1. Headers and Test Connectors
Part
Description
Setting
J1
External JTAG interface - For LCMX03 only
—
J8
External 12 V terminal block
Open
J9
External 5 V terminal block
Open
SW1
External adaptor power ON/OFF
—
J22
External reference clock input for MIPI D-PHY reference clock
—
J21
External or internal reference clock selection
1–2 (External), 2–3 (Internal)
J5
Debug I/O
—
J20
LIF-MD6000 chip select
OPEN-OFF, SHORT-ON
J19
SPI Flash chip select
OPEN-OFF, SHORT-ON
J4
External clock input for MIPI D-PHY reference clock
—
J6
External or internal clock selection
1–2 (External), 2–3 (Internal)
J18
External SP/I2C access
—
SW2
Configuration reset for LIF-MD6000
—
J29
Reset signal voltage selector
1-2 (VCCIO2), 2-3 (VCCIO0)
J28
Reveal analyzer signal connector
—
J26
Internal/External clock and I2C SDA Mux
1-2 (CLK_INT), 2-3 (CLK_EXT), 2-4 (SDA)
J27
Internal/External reference clock and I2C SCL Mux
1-2 (CLK_INT_REF), 2-3 (CLK_EXT_REF), 2-4 (SCL)
J24
VCCIO1 Bank voltage selector
1-2 (2.5 V), 2-3 (3.3 V), 2-4 (1.2 V)
J25
VCCIO2 Bank voltage selector
1-2 (2.5 V), 2-3 (3.3 V), 2-4 (1.2 V)
J3
External power jack
—
U7, U9
Tx Connectors for external interface
—
U11, U12
Rx Connectors for external interface
—
SW4*
External reset for LIF-MD6000 device
—
SW3
External reset for LCMXO3L device
—
SW5
PMU WAKEUP Switch
—
J23
Debug Header for LCMXO3L device
—
*Note: Some CrossLink demos utilize this reset signal to ball G9 of Bank 2 while it is configured as a 1.2 V Bank. However, LVCMOS12
inputs are no longer supported across all 3 Banks. Lattice Diamond®Software 3.9 and later will not allow this signal to be placed on a
1.2 V Bank. If it is necessary to recompile one of these demo projects, the necessary modifications should be made to the project
and the board to move this reset signal to a non-1.2 V Bank on CrossLink.

CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.4 7
3. Programming Circuit
The Mini-B USB connector is used for programming the board by using Lattice Diamond Programmer software.
Figure 3.1 shows the programming block of LIF-MD6000 Master Link board.
The Mini-B USB connector interfaces to the FTDI FT2232H IC. The FTDI IC works with Diamond programmer software to
provide interfaces for:
JTAG –to program MachXO2-1300E
SPI –to program both CrossLink, and SPI Flash Memory
USB Mini-B
(J2) FTDI Chip (U1)
SPI Flash (U14)
LIF-MD6000
CSFBGA81 (U8)
LCMXO3LF-1300E
MG121 (U19)
JTAG
SPI
Figure 3.1. Programming Block
3.1. Bridging Circuit
Figure 3.2 shows the block diagram of bridging of different standard interfaces. The CrossLink device is used as a
bridging device that supports a variety of I/O standards. This demo board supports development of the following
interface bridges:
1:1 MIPI DSI Display Interface Bridge
1:2 MIPI DSI Display Interface Bridge
2:1 MIPI CSI-2 Image Sensor Aggregator Bridge
CMOS to MIPI CSI-2 Image Sensor Interface Bridge
MIPI CSI-2 to CMOS Image Sensor Interface Bridge
MIPI DSI to CMOS Display Interface Bridge
OpenLDI LVDS to MIPI DSI Display Interface Bridge
CMOS to MIPI DSI Display Interface Bridge

CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-EB-02010-1.4
LIF-MD6000
CSFBGA81 (U8)
Rx Connector 1
Rx Connector 2
D-PHY I/F
D-PHY Rx/
LVDS/CMOS
D-PHY Rx/
LVDS/CMOS
Tx Connector 2
Tx Connector 1
D-PHY I/F
Figure 3.2. Bridging Block
3.2. I2C Expander
Figure 3.3 shows the block diagram of the I2C expander. The LCMXO3LF-1200E device is used as an I2C expander and it
supports a single master and multiple slave devices connected to the board. The master I2C interface is connected to
the Tx header and the slave device I2C interface is connected to the Rx connectors supporting any slave device access
from the master based on the slave address.
LCMXO3LF-1200E-
MG121 (U19)
Rx Connector 1
Rx Connector 2
LIF-MD6000
CSFBGA81 (U8)
Tx
H
e
a
d
e
r
I2C
2 X I2C
2 X I2C
Figure 3.3. I2C Expander Block

CrossLink LIF-MD6000 Master Link Board
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© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.4 9
4. Power Supply
The power supply to the development kit is provided by the Mini-B USB connector or from an external adaptor.
Figure 4.1 shows the power supply block of the CrossLink LIF-MD6000 Master Link board. The Mini-B USB connector is
used only for programming and the onboard power regulator for the successful programming. The external adaptor
provides 12 V power source through voltage regulators on the board to CrossLink and LCMXO3LF-1300E, as well as to
the external boards connected to Tx and Rx Headers. Each I/O and core voltage rail on the board is accessible by a test
point on the board. The current flowing to each rail can be measured using a 1 Ω resistor placed in the path of each
voltage rail.
J3
J2
12 V to 5 V
converter
LDO
LDO
LDO
LDO
Power adaptor
Mini-B USB
5 V
5 V
U15
U5
U6
U17
12 V
U18
1.2 V
3.3 V
2.5 V
1.8 V
Figure 4.1. Power Supply Block
Table 4.1 lists the device power rails. There are five voltage regulators on the board used to supply the 5 V, 3.3 V, 2.5V
1.8 V, and 1.2 V rails. The input to these regulators is either from the Mini-B USB connector or the external 12 V
adaptor that is connected to the board. Switch SW2 is used to connect or disconnect the external adaptor power to the
board.
Table 4.1. Power LEDs
Voltage Rail
LEDs
Color
12
D26
Green
5
D3
Green
3.3
D25
Green
2.5
D29
Green
1.8
D28
Green
1.2
D27
Green
Table 4.2 on the next page lists the board voltage rails, including the rail source voltage, test point number, and current
sense resistor number.

CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-EB-02010-1.4
Table 4.2. Device Power Rail Summary and Test Points
Voltage Rail
Source Rail
Current Sense Resistor
Test Points
12 V
12_Ext
—
12V
5 V
12 V
—
5V
+3.3 V
5 V
—
3V3
+2.5 V
5 V
—
2V5
+1.8 V
5 V
—
1V8
+1.2 V
5 V
—
1V2
VCCCORE
+1.2 V
R19
VCC_CORE
VCCIO0
+3.3 V
R20
VCCIO0
VCCIO1
+3.3 V
R21
VCCIO1
VCCIO2
+3.3 V
R28
VCCIO2
VCC_DPHY
+1.2 V
R417
VCC_DPHY
1K_VCC_CORE
1.2 V
R190
1K_VCC_CORE
1K_VCCIO0
+3.3 V
R410
1K_VCCIO0
1K_VCCIO1
+3.3 V
R184
1K_VCCIO1
1K_VCCIO2
+3.3 V
R186
1K_VCCIO2
1K_VCCIO3
+3.3 V
R188
1K_VCCIO3

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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.4 11
5. Status Indicators
The LED status indicators on the board show power, configuration, and application status. Table 5.1 lists the status LED
I/O map.
Table 5.1. Status LED I/O Map
Device
LED
Net Name
Color
CrossLink
D6
CMOS_IO_1
Blue
CrossLink
D7
CMOS_IO_2
Blue
CrossLink
D8
CMOS_IO_3
Blue
CrossLink
D9
CMOS_IO_4
Blue
CrossLink
D10
CDONE
Green
LCMX03LF-1300E
D23
DONE
Red

CrossLink LIF-MD6000 Master Link Board
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© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-EB-02010-1.4
6. SMA IO Link Board
The SMA IO Link board connects to the CrossLink LIF-MD6000 Master Link board’s Tx or Rx connectors (U7, U9, U11 or
U12) and transfers signals to the respective SMA connectors.
Table 6.1. Headers and Test Connectors
Part
Description
Mapping to U1
J1
SMA connector for DCK_TX_P
Pin 1
J2
SMA connector for DCK_TX_N
Pin 2
J3
SMA connector for DATA0_TX_P
Pin 4
J4
SMA connector for DATA0_TX_N
Pin 5
J5
SMA connector for DATA1_TX_P
Pin 7
J6
SMA connector for DATA1_TX_N
Pin 8
J7
SMA connector for DATA2_TX_P
Pin 13
J8
SMA connector for DATA2_TX_N
Pin 14
J9
SMA connector for DATA3_TX_P
Pin 16
J10
SMA connector for DATA3_TX_N
Pin 17
J11
SMA connector for DATA4_TX_P
Pin 24
J12
SMA connector for DATA4_TX_N
Pin 25
J13
SMA connector for DATA5_TX_P
Pin 27
J14
SMA connector for DATA5_TX_N
Pin 28
U1
Connector to interface to CrossLink Master Link board
N/A
Table 6.2. U1 Connector Description
Pin
Name
1
CH4_DCK_P
2
CH4_DCK_N
3
GND
4
CH4_DATA0_P
5
CH4_DATA0_N
6
GND
7
CH4_DATA1_P
8
CH4_DATA1_N
9
GND
10
SN
11
SCLK
12
GND
13
CH4_DATA2_P
14
CH4_DATA2_N
15
GND
16
CH4_DATA3_P
17
CH4_DATA3_N
18
GND
19
12V
20
12V
Pin
Name
21
TBD
22
RESETN
23
PWR_5-0V
24
GND
25
GND
26
PWR_3-3V
27
GND
28
GND
29
PWR_1-8V
30
MOSI
31
MISO
32
PWR_1-8V
33
GND
34
GND
35
PWR_3-3V
36
GND
37
GND
38
PWR_5-0V
39
SDA
40
SCL
Note: U1 connector pin names may be different than the actual signal depending on which CrossLink LIF-MD6000 Master Link board
connector this daughter board is connected to.

CrossLink LIF-MD6000 Master Link Board
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© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.4 13
Figure 6.1. Top View of SMA IO Link Board
Figure 6.2. Bottom View of SMA IO Link Board

CrossLink LIF-MD6000 Master Link Board
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© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14 FPGA-EB-02010-1.4
7. Breakout IO Link Board
The Breakout IO Link board connects to the CrossLink LIF-MD6000 Master Link board’s Tx or Rx connectors (U7, U9,
U11 or U12) and transfers signals to the 26-pin header (J2).
Table 7.1. Headers and Test Connectors
Part
Description
Setting
J2
13x2 Header
—
U1
Connector to interface to CrossLink Master Link board
—
Table 7.2. U1 Connector Description
Pin
Name
1
CH4_DCK_P
2
CH4_DCK_N
3
GND
4
CH4_DATA0_P
5
CH4_DATA0_N
6
GND
7
CH4_DATA1_P
8
CH4_DATA1_N
9
GND
10
SN
11
SCLK
12
GND
13
CH4_DATA2_P
14
CH4_DATA2_N
15
GND
16
CH4_DATA3_P
17
CH4_DATA3_N
18
GND
19
12V
20
12V
Pin
Name
21
TBD
22
RESETN
23
PWR_5-0V
24
GND
25
GND
26
PWR_3-3V
27
GND
28
GND
29
PWR_1-8V
30
MOSI
31
MISO
32
PWR_1-8V
33
GND
34
GND
35
PWR_3-3V
36
GND
37
GND
38
PWR_5-0V
39
SDA
40
SCL
Note: U1 connector pin names may be different than the actual signal depending on which CrossLink LIF-MD6000 Master Link board
connector this daughter board is connected to.

CrossLink LIF-MD6000 Master Link Board
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© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.4 15
Table 7.3. J2 Header Description
Pin
Name
Mapping to U1
1
+3.3V
N/A
2
+1.8V
N/A
3
RESETN
Pin 22
4
CH4_DCK_TX_P
Pin 1
5
SDA
Pin 39
6
CH4_DCK_TX_N
Pin 2
7
SCL
Pin 40
8
GND
N/A
9
GND
N/A
10
CH4_DATA0_TX_P
Pin 4
11
CH4_DATA3_TX_P
Pin 16
12
CH4_DATA0_TX_N
Pin 5
13
CH4_DATA3_TX_N
Pin 17
14
GND
N/A
15
GND
N/A
16
CH4_DATA1_TX_P
Pin 7
17
CH4_DATA4_TX_P
Pin 24
18
CH4_DATA1_TX_N
Pin 8
19
CH4_DATA4_TX_N
Pin 25
20
GND
N/A
21
GND
N/A
22
CH4_DATA2_TX_P
Pin 13
23
CH4_DATA5_TX_P
Pin 27
24
CH4_DATA2_TX_N
Pin 14
25
CH4_DATA5_TX_N
Pin 28
26
GND
N/A

CrossLink LIF-MD6000 Master Link Board
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© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16 FPGA-EB-02010-1.4
Figure 7.1. Top View of Breakout IO Link Board
Figure 7.2. Bottom View of Breakout IO Link Board

CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.4 17
8. Ordering Information
Table 8.1. Ordering Information
Description
Ordering Part Number
China RoHS Environment-Friendly
Use Period (EFUP)
CrossLink: LIF-MD6000 Master Link Board
(Includes 1 SMA IO Link Board and 1 Breakout
IO Link Board)
LIF-MD6000-ML-EVN
CrossLink: LIF-MD6000 IO Link Boards
(Includes 1 SMA IO Link Board and 1 Breakout
IO Link Board)
LIFMD-IOL-EVN

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© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18 FPGA-EB-02010-1.4
References
For more information, refer to FPGA-DS-02007 (previously DS1055), CrossLink Family Data Sheet
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.

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© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02010-1.4 19
Appendix A. LIF-MD6000-ML-EVN-BRD Schematics
LIF-MD6000 Master Link Board Block Diagram
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB
CONNECTOR
USB to
JTAG / SPI
FTDI
USP Programming only
BANK-1,2
DPHY BLOCK
LIFMD-6000-6MG81I
MIPI TX HEADER1
I2C
MIPI TX I/O
BANK-0
LVDS RX HEADER1
SPI
Ext Power
Adaptor (12V)
OnBoard
LDO'S & Buck
1V2,1V8,2V5,3V3,5V
JTAG_I/F/ SPI
MIPI TX HEADER2
MIPI TX I/O
LVDS RX HEADER1
I2C
LVDS RX In
LVDS RX In
SPI
BANK-3,4
BANK-2
BANK-0
LCMXO3LF-1300-MG121
JTAG
I2C*3
I/O Expander - I2C Switch
Targeted FPGA
SPI FLASH
I2C
SPI
SPI I2C*2 I2C*1
SPI
SPI
I2C
DDDaaattteee:::
SSSiiizzzeee SSSccchhheeemmmaaatttiiiccc RRReeevvv
ooofffSSShhheeeeeettt
TTTiiitttllleee
LLLaaattttttiiiccceee SSSeeemmmiiicccooonnnddduuuccctttooorrr AAAppppppllliiicccaaatttiiiooonnnsss
EEEmmmaaaiiilll::: ttteeeccchhhsssuuuppppppooorrrttt@@@LLLaaattttttiiiccceeessseeemmmiii...cccooommm
BBBoooaaarrrddd RRReeevvv
PPPrrrooojjjeeecccttt
111666---FFFEEEBBB---111666
BBB 111...000
888111
BBBLLLOOOCCCKKK DDDiiiaaagggrrraaammm
LLLIIIFFFMMMDDD---666000000000---666MMMGGG888111III SSSnnnooowww bbbrrriiidddgggiiinnnggg sssooollluuutttiiiooonnn BBB

CrossLink LIF-MD6000 Master Link Board
Evaluation Board User Guide
© 2016-2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20 FPGA-EB-02010-1.4
FTDI Interface
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PROGRAMMING INTERFACE
TDO
TDI
TMS
TCK
FT_EECS
FT_EECLK
FT_EEDATA
VCC1_8FT
VCC1_8FT
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
VBUS_5V
MCLK 4,5,6
SISPI 4,5,6
SPISO 4,5,6
7 12MHZ
CSSPIN 4,5,6
TCK 7
TDI 7
TDO 7
TMS 7
CDONE 6
CRESETB 6
DDDaaattteee:::
SSSiiizzzeee SSSccchhheeemmmaaatttiiiccc RRReeevvv
ooofffSSShhheeeeeettt
TTTiiitttllleee
LLLaaattttttiiiccceee SSSeeemmmiiicccooonnnddduuuccctttooorrr AAAppppppllliiicccaaatttiiiooonnnsss
EEEmmmaaaiiilll::: ttteeeccchhhsssuuuppppppooorrrttt@@@LLLaaattttttiiiccceeessseeemmmiii...cccooommm
BBBoooaaarrrddd RRReeevvv
PPPrrrooojjjeeecccttt
111666---FFFEEEBBB---111666
BBB 111...000
888222
FFFTTTDDDIII IIINNNTTTEEERRRFFFAAACCCEEE
LLLIIIFFFMMMDDD---666000000000---666MMMGGG888111III SSSnnnooowww bbbrrriiidddgggiiinnnggg sssooollluuutttiiiooonnn BBB
C6 0.1uF
C7
10uF
R4 0
R1712k
C12
0.1uF
R13
10K
R60
R3
4.7k
L3
600ohm 500mA
12
C15
0.1uF
R1
4.7k
C1
4u7
12
C2
0.1uF
93LC56-SO8
U2
CS 1
CLK 2
DI 3
DO 4 VSS
5ORG
6NU
7VCC
8
C13
0.1uF
R11 12k
R12
10K
R2
4.7k
R1800
C8
0.1uF
R9
2k2
C9
0.1uF
R1810
C16
0.1uF
R1670
L2
600ohm 500mA
12
C4
0.1uF
FTDI High-Speed USB
FT2232H
FT2232HL
U1
VREGIN
50
VREGOUT
49
DM
7
DP
8
REF
6
RESET#
14
EECS
63
EECLK
62
EEDATA
61
OSCI
2
OSCO
3
TEST
13
ADBUS0 16
ADBUS1 17
ADBUS2 18
ADBUS3 19
VPHY 4
VPLL 9
VCORE 12 VCORE 37 VCORE 64
VCCIO 20 VCCIO 31 VCCIO 42 VCCIO 56
AGND
10
GND
1
GND
5
GND
11
GND
15
GND
25
GND
35
GND
47
GND
51
PWREN# 60
SUSPEND# 36
ADBUS4 21
ADBUS5 22
ADBUS6 23
ADBUS7 24
ACBUS0 26
ACBUS1 27
ACBUS2 28
ACBUS3 29
ACBUS4 30
ACBUS5 32
ACBUS6 33
ACBUS7 34
BDBUS0 38
BDBUS1 39
BDBUS2 40
BDBUS3 41
BDBUS4 43
BDBUS5 44
BDBUS6 45
BDBUS7 46
BCBUS0 48
BCBUS1 52
BCBUS2 53
BCBUS3 54
BCBUS4 55
BCBUS5 57
BCBUS6 58
BCBUS7 59
J2
SKT_MINIUSB_B_RA
VCC 1
D- 2
D+ 3
ID 4
GND 5
SHIELD3
8
SHIELD2
7
SHIELD1
6
SHIELD4
9
R160
R50
C11
18pF
X1
12MHZ
1
133
G1
2G2 4
R260
R10 2k2
C10
18pF
0DNI R23
L1
600ohm 500mA
12
R180
DNI
R70
C5
0.1uF
C14
0.1uF
C3
4u7
12
R14
10K R150
J1
header_1x8
11
22
33
44
55
66
77
88