Lattice semiconductor Ice40hx-8k User manual

iCE40HX-8K Breakout Board

Evaluation Board User Guide

FPGA-EB-02031-1.2

July 2020

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iCE40HX-8K Breakout Board

Evaluation Board User Guide

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2 FPGA-EB-02031-1.2

Disclaimers

Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its

products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is

entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have

been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the

same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s

product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this

document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any

products at any time without notice.

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Evaluation Board User Guide

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FPGA-EB-02031-1.2 3

Contents

Acronyms in This Document.................................................................................................................................................4

1. Introduction..................................................................................................................................................................5

2. Features........................................................................................................................................................................5

3. iCE40 Device .................................................................................................................................................................7

4. Software Requirements................................................................................................................................................7

5. Demonstration Design..................................................................................................................................................7

6. Board Power.................................................................................................................................................................8

7. Board I/O ......................................................................................................................................................................8

8. Programming Options ..................................................................................................................................................8

9. Ordering Information .................................................................................................................................................10

TechnicalSupport Assistance ..............................................................................................................................................11

Appendix A. Schematic Diagrams.......................................................................................................................................12

RevisionHistory...................................................................................................................................................................18

Figures

Figure 2.1. Top Side of the iCE40HX-8K Evaluation Board....................................................................................................5

Figure 2.2. Block Diagram.....................................................................................................................................................6

Figure 5.1. Block Diagram of the Verilog or VHDL Code.......................................................................................................7

Figure 8.1. SPI Flash Programming .......................................................................................................................................8

Figure 8.2. CRAM Programming ...........................................................................................................................................9

Figure A.1. Block Diagram...................................................................................................................................................12

Figure A.2. USB to SPI/RS232..............................................................................................................................................13

Figure A.3. FPGA .................................................................................................................................................................14

Figure A.4. FPGA .................................................................................................................................................................15

Figure A.5. Power and LEDs................................................................................................................................................16

Figure A.6. SPI.....................................................................................................................................................................17

Tables

Table 9.1. Ordering Information.........................................................................................................................................10

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4 FPGA-EB-02031-1.2

Acronyms in This Document

A list of acronyms used in this document.

Acronym

Definition

CRAM

Configuration Random Access Memory

FPGA

Field-Programmable Gate Array

FTDI

Future Technology Devices International

I/O

Input/Output

LED

Light Emitting Diode

SPI

Serial Peripheral Interface

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Evaluation Board User Guide

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FPGA-EB-02031-1.2 5

1. Introduction

This document provides technical information and instructions for using the iCE40™HX-8K Breakout Board. This kit is

based on the Lattice iCE40-HX8K-CT256 high performance FPGA device. Two source codes, one written in Verilog and

the other in VHDL, are available to download for the iCE40HX-8K Breakout Board. Both codes are functionally the same.

The contents of this user guide include demo operation, top-level functional descriptions of the various portions of the

evaluation board, descriptions of the on-board connectors, switches, a complete set of schematics, and the bill of

materials for the iCE40HX-8K Evaluation Board.

2. Features

The iCE40HX-8K Breakout Board includes:

iCE40HX-8K Evaluation Board –The iCE40HX-8K Evaluation Board features the following onboard capabilities:

iCE40HX-8K CT256 device

Eight user-accessible LEDs

SPI Flash for programming configuration

40 pin 0.1” header for user connectivity

0.1” holes for user connectivity

FTDI 2232H for USB interface

12 MHz oscillator

Jumpers to select programming the SPI flash or iCE40HX-8K

Pre-loaded Demo –The kit comes with a default design that flashes the LEDs on and off.

USB connector Cable –A mini B USB cable for programming the SRAM fabric of the iCE40HX-8K or the onboard SPI

flash. The USB cable also powers the iCE40HX-8K evaluation board. Figure 2.1 shows the top side of the iCE40HX-

8K Evaluation Board indicating the specific features that are designed on the board.

iCE40HX- 8K

LEDs

40 pinheader 0.1" spaced holes

USB

Figure 2.1. Top Side of the iCE40HX-8K Evaluation Board

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6 FPGA-EB-02031-1.2

FPGA

Power fromUSB 5 V

BANK 3

BANK 1

BANK 0

BANK 2

iCE40HX8K-CT256

HEADER

I/O

HEADER

I/O

RS232

USB

CONNECTOR

USB to

SPI / RS232

LEDS(1-8)

SPI

Figure 2.2. Block Diagram

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FPGA-EB-02031-1.2 7

3. iCE40 Device

This board features an iCE40HX-8K device with a 1.2 V core supply. It is packaged in a 256 caBGA package. For a

complete description of this device, refer to iCE40 LP/HX Family Data Sheet (FPGA-DS-02029).

4. Software Requirements

You should install the following software before you begin developing designs for the evaluation board:

Lattice iCEcube2™Release –2012.09SP1.22498 or later

Diamond® Programmer –Version 2.2 or later

These software are available at the Lattice website Design Software and IP page. Make sure you log in to the Lattice

website. Otherwise, these software downloads are not visible.

5. Demonstration Design

The design file iCE40HX8KLED.zip contains the following files:

LED_VHDL.vhd (VHDL code)

LED_Verilog.v (Verilog code)

LED.pcf (pin constraint file)

LED_VHDL_bitmap.hex (Bit stream file for programming FPGA)

LED_Verilog_bitmap.hex (Bit stream file for programming FPGA)

Two source codes are provided, one written in VHDL and the other in Verilog. Both of these codes function identically.

This provides you with an option to use either one of the codes when programming the iCE40HX-8K Breakout Board.

When the FPGA is programmed with one of these codes, the red LEDs (D2 thru D9) flashes on for half a second and off

for half a second. Figure 5.1 shows the block diagram of the Verilog or VHDL code.

÷216 ÷96 2-bit counter Decoder

½ second pulse 2

LED2

LED3

LED9

12 MHz Clk

Figure 5.1. Block Diagram of the Verilog or VHDL Code

The source code has two counters that are used to divide the 12 MHz clock by 216 and 96, generating an approximately

half-second pulse. This pulse along with the decoder turns the LEDs (D2 thru D9) on for half a second and off for half a

second. The decoder can be modified to have any type of LED sequence by changing either the VHDL or Verilog code.

When the board is plugged into a USB port, a +5 V power is applied to the board that lights a green LED (D11). After the

FPGA is programmed, a green LED (D10) lights. This LED is connected to the CDONE line of the FPGA.

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8 FPGA-EB-02031-1.2

6. Board Power

The iCE40HX-8K evaluation board is powered with the USB cable. LED location D11 indicates that the board is powered

up. All I/O are driven at 3.3 V. There are two versions of the BOM. Early versions have D1 populated with a CDBU0520

Schottky. Later versions populate D1 with a CDSU4148. The later version diode complies with the voltage requirements

on the Vpp_2V5 pin for NVCM programming/configuration.

7. Board I/O

The I/O that feed the holes and the 0.1” connector are driven at 3.3 V levels. Location J2 is the populated 2 x 20 row

connector. Locations J1, J3, and J4 have hole locations that you can connect to for their specific I/O requirements.

8. Programming Options

Two jumpers, J6 and J7, can be set for two types of FPGA configurations:

SPI Flash Mode, for programming the serial flash memory.

SPI Peripheral Mode, for configuring the volatile CRAM in the FPGA.

In SPI Flash Mode the SPI signals from the FTDI USB interface chip programs the serial flash memory. After the memory

is programmed, the FPGA reads from the memory and configures itself. The advantage of programming the serial flash

is that the FPGA is reconfigured after power-up. Jumpers must be in locations J7:1-2, J6:2-4, and J6:1-3 as shown in

Figure 8.1.

Figure 8.1. SPI Flash Programming

iCE40HX-8K Breakout Board

Evaluation Board User Guide

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FPGA-EB-02031-1.2 9

In SPI Peripheral Mode, the SPI signals load the program file into the CRAM (configuration RAM) of the FPGA directly. In

this mode, the FPGA loses its configuration when power is removed and must be reconfigured. Jumpers must be in

locations J6:1-2 and J6:3-4. Jumper J7 is not installed as shown in Figure 8.2.

Figure 8.2. CRAM Programming

LED in location D10 is connected to the CDONE pin of the iCE40HX-8K. This can be monitored to determine that the

iCE40HX-8K is programmed correctly.

iCE40HX-8K Breakout Board

Evaluation Board User Guide

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

10 FPGA-EB-02031-1.2

9. Ordering Information

Table 9.1. Ordering Information

Description

Ordering Part Number

China RoHS Environment-Friendly

Use Period (EFUP)

iCE40HX-8K Breakout Board

iCE40HX8K-B-EVN

iCE40HX-8K Breakout Board

Evaluation Board User Guide

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-EB-02031-1.2 11

Technical Support Assistance

Submit a technical support case through www.latticesemi.com/techsupport.

iCE40HX-8K Breakout Board

Evaluation Board User Guide

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

12 FPGA-EB-02031-1.2

Appendix A. Schematic Diagrams

Figure A.1. Block Diagram

B B

A A

FPGA

Power from USB 5V

BANK 3

BANK 1

BANK 0

BANK 2

iCE40HX8K-CT256

HEADER

I/O

HEADER

I/O

RS232

USB

CONNECTOR

USB to

SPI / RS232

LEDS(1-8)

SPI

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 iCE40HX-8K Breakout Board 
 Evaluation Board User Guide 
 
© 2013-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 
FPGA-EB-02031-1.2 13 
Figure A.2. USB to SPI/RS232 
5
5
4
4
3
3
2
2
1
1
D D
CC
BB
AA
SCK
SI
SO
FT_EECS
FT_EECLK
FT_EEDATA
SS
+3.3V
VCC1_8FT
VCC1_8FT
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
iCE_SCK 6
FLASH_MOSI 6
FLASH_MISO 6
iCE_SS_B 6
DM5
DP5
RS232_Rx_TTL 3
RS232_Tx_TTL 3
RTSn 3
DTRn 3
CTSn 3
DSRn 3
DCDn 3
iCE_CLK 4
iCE_CDONE 4
iCE_CREST 4
Title
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B
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B
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A
iCE40-HX8K Breakout Board - USB to SPI/RS232
B
26Jul 11, 2013
R50R50
C13
0.1uF
C13
0.1uF
C4
0.1uF
C4
0.1uF
R40R40
C12
0.1uF
C12
0.1uF
R11 12KR11 12K
R10
10K
R10
10K
C6
0.1uF
C6
0.1uF
X1
12.0000MHZ
X1
12.0000MHZ
VDD 4
STANDBY#
1
GND
2OUTPUT 3
R8
10K
R8
10K
R150R150
R120R120
R190R190
R30R30
C11
0.1uF
C11
0.1uF
R170R170R14 2.2KR14 2.2K
R20
0
R20
0
R7 2.2KR7 2.2K
C5
0.1uF
C5
0.1uF
C3
4.7uF
C3
4.7uF
C9
0.1uF
C9
0.1uF
R20R20
C2
0.1uF
C2
0.1uF
R9
10K
R9
10K
C10
10uF
C10
10uF
R160R160
C8
0.1uF
C8
0.1uF
FTDI High-Speed USB
 FT2232H
FT2232HL
U1
FTDI High-Speed USB
 FT2232H
FT2232HL
U1
VREGIN
50
VREGOUT
49
DM
7
DP
8
REF
6
RESET#
14
EECS
63
EECLK
62
EEDATA
61
OSCI
2
OSCO
3
TEST
13
ADBUS0 16
ADBUS1 17
ADBUS2 18
ADBUS3 19
VPHY 4
VPLL 9
VCORE 12
VCORE 37
VCORE 64
VCCIO 20
VCCIO 31
VCCIO 42
VCCIO 56
AGND
10
GND
1
GND
5
GND
11
GND
15
GND
25
GND
35
GND
47
GND
51
PWREN# 60
SUSPEND# 36
ADBUS4 21
ADBUS5 22
ADBUS6 23
ADBUS7 24
ACBUS0 26
ACBUS1 27
ACBUS2 28
ACBUS3 29
ACBUS4 30
ACBUS5 32
ACBUS6 33
ACBUS7 34
BDBUS0 38
BDBUS1 39
BDBUS2 40
BDBUS3 41
BDBUS4 43
BDBUS5 44
BDBUS6 45
BDBUS7 46
BCBUS0 48
BCBUS1 52
BCBUS2 53
BCBUS3 54
BCBUS4 55
BCBUS5 57
BCBUS6 58
BCBUS7 59
R130R130
R60R60
R18
0R18
0
R10R10
C7
0.1uF
C7
0.1uF
C1
4.7uF
C1
4.7uF
93LC56-SO8
U2
93LC56-SO8
U2
CS 1
CLK 2
DI 3
DO 4
VSS
5ORG
6NU
7VCC
8
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iCE40HX-8K Breakout Board

Evaluation Board User Guide

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14 FPGA-EB-02031-1.2

Figure A.3. FPGA

D D

C C

B B

MAKE PWR TRACES

CAPABLE OF 1A MAKE PWR TRACES

CAPABLE OF 1A

PIO0_01

PIO0_03

PIO0_07

PIO0_08

PIO0_09

PIO0_13

PIO0_14

PIO0_15

PIO0_17

PIO0_18

PIO0_23

PIO0_27

PIO0_29

PIO0_30

PIO0_31

PIO0_32

PIO0_33

PIO0_34

PIO0_36

PIO0_38

PIO0_39

PIO0_41

PIO0_42

PIO0_44

PIO0_45

PIO0_46

PIO0_47

PIO0_51

PIO0_07

PIO0_01 PIO0_08

PIO0_09PIO0_03

PIO0_13PIO0_15

PIO0_18

PIO0_14

PIO0_17PIO0_20

PIO0_23

PIO0_27

PIO0_29

PIO0_30

PIO0_32PIO0_31

PIO0_36

PIO0_34

PIO0_33

PIO0_45

PIO0_38

PIO0_46

PIO0_39PIO0_51

PIO0_41PIO0_47

PIO0_42

PIO0_44

PIO1_04

PIO1_08

PIO1_12

PIO1_19

PIO1_18

PIO1_16

PIO1_14

PIO1_22

PIO1_21

PIO1_20

PIO1_30

PIO1_29

PIO1_32

PIO1_34

PIO1_40

PIO1_38

PIO1_37

PIO1_36

PIO1_44

PIO1_42

PIO1_49

PIO1_47

PIO1_51

PIO1_01

PIO1_03

GBIN2/PIO1_28

PIO1_01

PIO1_04

PIO1_03

PIO1_08

PIO1_12

PIO1_20

PIO1_37

PIO1_18

PIO1_19

GBIN2/PIO1_28

PIO1_34

PIO1_30

PIO1_47

PIO1_40

PIO1_38

PIO1_14

PIO1_21

PIO1_16

PIO1_22

PIO1_42

PIO1_29

PIO1_32

PIO1_36

PIO1_46

PIO1_51

PIO1_44

PIO1_49

PIO0_20

PIO1_46

VCCIO1

VCCIO0

+1.2V

+3.3V

VCCIO0

VCCIO1 VCC_1.2V

LED7 5

LED6 5

LED5 5

LED4 5

LED3 5

LED2 5

LED1 5

LED0 5

RS232_Tx_TTL 2

RS232_Rx_TTL 2

DSRn 2

RTSn 2

DTRn 2

DCDn 2

CTSn 2

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BANK0

iCE40HX8K-CT256

U3A

BANK0

iCE40HX8K-CT256

U3A

PLLVCC0

PLLGND_0

GBIN1/PIO0_25

C8 GBIN0/PIO0_26

VCCIO0_01

A13

VCCIO0_02

VCCIO0_03

VCCIO0_04

PIO0_00 C14

PIO0_01 B15

PIO0_02 D13

PIO0_03 B14

PIO0_04 C12

PIO0_05 E11

PIO0_06 C13

PIO0_07 A16

PIO0_08 A15

PIO0_09 B13

PIO0_10 E10

PIO0_11 C11

PIO0_12 D11

PIO0_13 B12

PIO0_14 B10

PIO0_15 B11

PIO0_16 C10

PIO0_17 A10

PIO0_18 A11

PIO0_19 D10

PIO0_20 C9

PIO0_21 E9

PIO0_22 D9

PIO0_23 A9

PIO0_24 F9

PIO0_27 B9

PIO0_28 D8

PIO0_29 B8

PIO0_30 A7

PIO0_31 C7

PIO0_32 B7

PIO0_33 B6

PIO0_34 C6

PIO0_35 D7

PIO0_36 A6

PIO0_37 D6

PIO0_38 A5

PIO0_39 B5

PIO0_40 E6

PIO0_41 B4

PIO0_42 A2

PIO0_43 D5

PIO0_44 A1

PIO0_45 C5

PIO0_46 C4

PIO0_47 B3

PIO0_48 D4

PIO0_49 E5

PIO0_50 D3

PIO0_51 C3

C24

0.1uF

C24

0.1uF

C21

0.1uF

C21

0.1uF

C18

0.1uF

C18

0.1uF

TP7

DNI

TP7

DNI

TP8

DNI

TP8

DNI

R23

100

R23

100

C19

0.1uF

C19

0.1uF

TP6

DNI

TP6

DNI

C27

0.1uF

C27

0.1uF

Header2x20

40 39

R24

10K

R24

10K

Header2x20

DNI

Header2x20

DNI

40 39

C17

0.1uF

C17

0.1uF

C20

0.1uF

C20

0.1uF

TP5

DNI

TP5

DNI

BANK1

iCE40HX8K-CT256

U3B

BANK1

iCE40HX8K-CT256

U3B

PIO1_00

R14

PIO1_01

R15

PIO1_02

P14

PIO1_03

P15

TRST_B

N14

GBIN3/PIO1_27

H11 GBIN2/PIO1_28

H16

VCCIO1_01

H10

VCCIO1_02

C15

VCCIO1_03

H15

VCCIO1_04

N15

PIO1_04 P16

PIO1_05 M13

PIO1_06 M14

PIO1_07 L12

PIO1_08 N16

PIO1_09 L13

PIO1_10 L14

PIO1_11 K12

PIO1_12 M16

PIO1_13 J10

PIO1_14 M15

PIO1_15 J11

PIO1_16 L16

PIO1_17 K13

PIO1_18 K14

PIO1_19 J15

PIO1_20 K15

PIO1_21 K16

PIO1_22 J14

PIO1_23 J12

PIO1_24 J13

PIO1_25 J16

PIO1_26 H13

PIO1_29 H14

PIO1_30 G16

PIO1_31 H12

PIO1_32 G15

PIO1_33 G10

PIO1_34 F16

PIO1_35 G11

PIO1_36 F15

PIO1_37 G14

PIO1_38 E16

PIO1_39 G13

PIO1_40 D16

PIO1_41 G12

PIO1_42 F14

PIO1_43 F12

PIO1_44 D15

PIO1_45 F11

PIO1_46 E14

PIO1_47 C16

PIO1_48 F13

PIO1_49 B16

PIO1_50 E13

PIO1_51 D14

C23

0.1uF

C23

0.1uF

C26

0.1uF

C26

0.1uF

R21

TP9

DNI

TP9

DNI

C15

0.1uF

C15

0.1uF

TP4

DNI

TP4

DNI

C22

10uF

C22

10uF

C25

0.1uF

C25

0.1uF

R22

1C16

0.1uF

C16

0.1uF

C14

0.1uF

C14

0.1uF

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 iCE40HX-8K Breakout Board 
 Evaluation Board User Guide 
 
© 2013-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 
FPGA-EB-02031-1.2 15 
Figure A.4. FPGA 
5
5
4
4
3
3
2
2
1
1
DD
C C
BB
AA
MAKE PWR TRACES
CAPABLE OF 1A
MAKE PWR TRACES
CAPABLE OF 1A
GBIN6/PIO3_26/DP13A
PIO2_01
PIO2_03
PIO2_07
PIO2_05
PIO2_09
PIO2_08
PIO2_15
PIO2_10
PIO2_18
PIO2_17
PIO2_16
PIO2_20
PIO2_21
PIO2_28
PIO2_24
PIO2_29
PIO2_36
PIO2_35
PIO2_34
PIO2_32
PIO2_31
PIO2_39
PIO2_38
PIO2_37
PIO2_43
PIO2_41
PIO2_45/CBSEL1
GBIN5/PIO2_26
PIO3_01/DP00B
PIO3_03/DP01B
PIO3_05/DP02B
PIO3_04/DP02A
PIO3_07/DP03B
PIO3_09/DP04B
PIO3_13/DP06B
PIO3_17/DP08B
PIO3_19/DP09B
PIO3_23/DP11B
PIO3_21/DP10B
PIO3_27/DP13B
PIO3_35/DP17B
PIO3_30/DP15A
PIO3_31/DP15B
PIO3_29/DP14B
PIO3_28/DP14A
PIO3_33/DP16B
PIO3_39/DP19B
PIO3_37/DP18B
PIO3_41/DP20B
PIO3_46/DP23A
PIO3_45/DP22B
PIO3_48/DP24A
PIO3_50/DP25A
GBIN7/PIO3_25/DP12B
PIO2_43
PIO2_35PIO2_41
PIO2_38PIO2_36
PIO2_39PIO2_45/CBSEL1
PIO2_32PIO2_37
PIO2_34
PIO2_31
PIO2_33PIO2_29
PIO2_17PIO2_28
PIO2_24GBIN5/PIO2_26
PIO2_20
PIO2_21
PIO2_18PIO2_16
PIO2_15PIO2_08
PIO2_07PIO2_10
PIO2_03PIO2_09
PIO2_01
PIO2_05
PIO3_50/DP25A
PIO3_46/DP23A
PIO3_48/DP24A
PIO3_45/DP22B
PIO3_41/DP20B
PIO3_39/DP19BPIO3_35/DP17B
PIO3_37/DP18B
PIO3_33/DP16B
PIO3_31/DP15B
PIO3_30/DP15A
PIO3_28/DP14APIO3_29/DP14B
PIO3_23/DP11B
GBIN6/PIO3_26/DP13A
PIO3_21/DP10BPIO3_27/DP13B
PIO3_17/DP08B
GBIN7/PIO3_25/DP12B
PIO3_13/DP06BPIO3_19/DP09B
PIO3_09/DP04BPIO3_07/DP03B
PIO3_04/DP02APIO3_05/DP02B
PIO3_03/DP01B
PIO3_01/DP00B
PIO2_33
VCCIO2
+3.3V
VCCIO3
+1.2V
+3.3V
VCCIO2
+3.3V
VCCIO3 VCC_3.3V
VCCIO2
iCE_CLK2
iCE_CDONE
2
iCE_CREST
2
Title
veRrebmuNtnemucoDeziS
teehS:etaD of
AXELSYS
ICE40HX8K-B-EVN
A
iCE40-HX8K Breakout Board - FPGA
B
46Jul 26, 2013
Title
veRrebmuNtnemucoDeziS
teehS:etaD of
AXELSYS
ICE40HX8K-B-EVN
A
iCE40-HX8K Breakout Board - FPGA
B
46Jul 26, 2013
Title
veRrebmuNtnemucoDeziS
teehS:etaD of
AXELSYS
ICE40HX8K-B-EVN
A
iCE40-HX8K Breakout Board - FPGA
B
46Jul 26, 2013
R25
1
R25
1
C33
0.1uF
C33
0.1uF
C35
0.1uF
C35
0.1uF
J4
Header2x20
DNI
J4
Header2x20
DNI
2
4
6
8
10
12
14
16
18
20
24
22
26
28
30
32
34
36
38
40 39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
D10
Green
D10
Green
12
C32
0.1uF
C32
0.1uF
C37
0.1uF
C37
0.1uF
C40
0.1uF
C40
0.1uF
C38
0.1uF
C38
0.1uF
C31
0.1uF
C31
0.1uF
TP11
DNI
TP11
DNI
1
TP12
DNI
TP12
DNI
1
TP15
DNI
TP15
DNI
1
C30
0.1uF
C30
0.1uF
C29
0.1uF
C29
0.1uF
R29 10KR29 10K
C34
0.1uF
C34
0.1uF
BANK3
iCE40HX8K-CT256
U3D
BANK3
iCE40HX8K-CT256
U3D
GBIN7/PIO3_25/DP12B
G1
GBIN6/PIO3_26/DP13A
J3
VCCIO3_01
E1
VCCIO3_02
G6
VCCIO3_03
J6
VCCIO3_04
N1
PIO3_00/DP00A E4
PIO3_01/DP00B B2
PIO3_02/DP01A F5
PIO3_03/DP01B B1
PIO3_04/DP02A C1
PIO3_05/DP02B C2
PIO3_06/DP03A F4
PIO3_07/DP03B D2
PIO3_08/DP04A G5
PIO3_09/DP04B D1
PIO3_10/DP05A G4
PIO3_11/DP05B E3
PIO3_12/DP06A H5
PIO3_13/DP06B E2
PIO3_14/DP07A G3
PIO3_15/DP07B F3
PIO3_16/DP08A H3
PIO3_17/DP08B F2
PIO3_18/DP09A H6
PIO3_19/DP09B F1
PIO3_20/DP10A H4
PIO3_21/DP10B G2
PIO3_22/DP11A J4
PIO3_23/DP11B H2
PIO3_24/DP12A J5
PIO3_27/DP13B H1
PIO3_28/DP14A J2
PIO3_29/DP14B J1
PIO3_30/DP15A K1
PIO3_31/DP15B K3
PIO3_32/DP16A L4
PIO3_33/DP16B L1
PIO3_34/DP17A K4
PIO3_35/DP17B M1
PIO3_36/DP18A L6
PIO3_37/DP18B L3
PIO3_38/DP19A K5
PIO3_39/DP19B M2
PIO3_40/DP20A L7
PIO3_41/DP20B N2
PIO3_42/DP21A M6
PIO3_43/DP21B M3
PIO3_44/DP22A L5
PIO3_45/DP22B N3
PIO3_46/DP23A P1
PIO3_47/DP23B M4
PIO3_48/DP24A P2
PIO3_49/DP24B M5
PIO3_50/DP25A R1
PIO3_51/DP25B N4
C36
10uF
C36
10uF
R26
100
R26
100
C41
0.1uF
C41
0.1uF
C39
0.1uF
C39
0.1uF
BANK2
iCE40HX8K-CT256
U3C
BANK2
iCE40HX8K-CT256
U3C
GBIN5/PIO2_26
R9 GBIN4/PIO2_27
K9
PLLGND_2
N8
PLLVCC2
L8
PIO2_44/CBSEL0
K11
PIO2_45/CBSEL1
P13
CDONE
M10
CRESET_B
N11
VCCIO2_01
K8
VCCIO2_02
P3
VCCIO2_03
R13
VCCIO2_04
R8
PIO2_00 N6
PIO2_01 T1
PIO2_02 P4
PIO2_03 R2
PIO2_04 N5
PIO2_05 T2
PIO2_06 P5
PIO2_07 R3
PIO2_08 R5
PIO2_09 T3
PIO2_10 R4
PIO2_11 M7
PIO2_12 N7
PIO2_13 P6
PIO2_14 M8
PIO2_15 T5
PIO2_16 R6
PIO2_17 P8
PIO2_18 T6
PIO2_19 L9
PIO2_20 T7
PIO2_21 T8
PIO2_22 P7
PIO2_23 N9
PIO2_24 T9
PIO2_25 M9
PIO2_28 P9
PIO2_29 R10
PIO2_30 L10
PIO2_31 P10
PIO2_32 N10
PIO2_33 T10
PIO2_34 T11
PIO2_35 T15
PIO2_36 T14
PIO2_37 M11
PIO2_38 T13
PIO2_39 N12
PIO2_40 L11
PIO2_41 T16
PIO2_42 M12
PIO2_43 R16
TP13
DNI
TP13
DNI
1
R27
1
R27
1
C28
0.1uF
C28
0.1uF
TP10
DNI
TP10
DNI
1
J3
Header2x20
DNI
J3
Header2x20
DNI
2
4
6
8
10
12
14
16
18
20
24
22
26
28
30
32
34
36
38
40 39
37
35
33
31
29
27
25
23
21
19
17
15
13
11
9
7
5
3
1
R28
649
R28
649
TP14
DNI
TP14
DNI
1
TP16
DNI
TP16
DNI
1
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iCE40HX-8K Breakout Board 
Evaluation Board User Guide 
 
© 2013-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 
16 FPGA-EB-02031-1.2 
Figure A.5. Power and LEDs 
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
AA
LEDs
+3.3V
+1.2V
+3.3V +1.2V
+3.3V
+1.2V
VBUS_5V VCC_3.3V
+3.31V
+1.22V VCC_1.2V
VBUS_5V
+3.3V
+1.2V
LED33
LED43
LED53
LED63
LED73
DM 2
DP 2
LED23
LED03
LED13
Title
veRrebmuNtnemucoDeziS
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AXELSYS
ICE40HX8K-B-EVN
A
iCE40-HX8K Breakout Board - Power, LEDs
B
56Jul 26, 2013
Title
veRrebmuNtnemucoDeziS
teehS:etaD of
AXELSYS
ICE40HX8K-B-EVN
A
iCE40-HX8K Breakout Board - Power, LEDs
B
56Jul 26, 2013
Title
veRrebmuNtnemucoDeziS
teehS:etaD of
AXELSYS
ICE40HX8K-B-EVN
A
iCE40-HX8K Breakout Board - Power, LEDs
B
56Jul 26, 2013
D3
Red
D3
Red
12
TP2
DNI
TP2
DNI
1
L2
600 Ohm 500 mA
L2
600 Ohm 500 mA
R47
1K
R47
1K
J5
SKT_MINIUSB_B_RA
J5
SKT_MINIUSB_B_RA
VCC 1
D- 2
D+ 3
ID 4
GND 5
R40
1K
R40
1K
C55
0.01uF
C55
0.01uF
C50
1uF
C50
1uF
D9
Red
D9
Red
12
R45
1K
R45
1K
R43
1K
R43
1K
R39
100
R39
100
L3
600 Ohm 500 mA
L3
600 Ohm 500 mA
R41
1K
R41
1K
L1
600 Ohm 500 mA
L1
600 Ohm 500 mA
R37
0.1
R37
0.1
U4
LT3030EFE#TRPBF
U4
LT3030EFE#TRPBF
GND3
5
IN1_1
18
SHDN2
11
GND2
15
PWRGD1
19
IN1_2
17
IN2_1
14
PWRGD2
12
GND4
6
IN2_2
13
SHDN1
20
GND1
16
OUT1_1 3
OUT1_2 4
BYP1 2
ADJ1 1
OUT2_1 7
OUT2_2 8
BYP2 9
ADJ2 10
THERMPAD
21
C49
10uF
C49
10uF
C48
0.01uF
C48
0.01uF
D4
Red
D4
Red
12
C58
4.7uF
C58
4.7uF
R35
1M
R35
1M
C46
0.1uF
C46
0.1uF
POWER
iCE40HX8K-CT256
U3F
POWER
iCE40HX8K-CT256
U3F
GND_01
A12
GND_02
A4
GND_03
E15
GND_04
G7
GND_05
G8
GND_06
G9
GND_07
H7
GND_08
H8
GND_09
H9
GND_10
J7
GND_11
J8
GND_12
J9
GND_13
K2
GND_14
K7
GND_15
L15
GND_16
R7
GND_17
T12
GND_18
T4
VCC_01 A14
VCC_02 F10
VCC_03 F6
VCC_04 K10
VCC_05 K6
VCC_06 L2
VPP_FAST D12
VPP_2V5 E12
R53
1K
R53
1K
C56
22uF
C56
22uF
C44
0.1uF
C44
0.1uF
C62 0.1uFC62 0.1uF
TP3
DNI
TP3
DNI
1
C57
0.1uF
C57
0.1uF
R38
1
R38
1
TP1
DNI
TP1
DNI
1
D5
Red
D5
Red
12
D7
Red
D7
Red
12
C54
10uF
C54
10uF
R46
1K
R46
1K
C59
0.01uF
C59
0.01uF
R36 210KR36 210K
D2
Red
D2
Red
12
R44
1K
R44
1K
C43
1uF
C43
1uF
D8
Red
D8
Red
12
C61
0.1uF
C61
0.1uF
R42
1K
R42
1K
R33
100
R33
100
C42
10uF
C42
10uF
D6
Red
D6
Red
12
D11
Green
D11
Green
12
C53
10uF
C53
10uF
C52
0.01uF
C52
0.01uF
R34
1M
R34
1M
C51
0.1uF
C51
0.1uF
C47
0.1uF
C47
0.1uF
R48 0R48 0
R32
357K
R32
357K
R31
0.1
R31
0.1
C60
22uF
C60
22uF
C45
0.1uF
C45
0.1uF
D1
CDSU4148
1
2
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iCE40HX-8K Breakout Board

Evaluation Board User Guide

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-EB-02031-1.2 17

Figure A.6. SPI

C C

B B

A A

For programming Flash - Shunt 1,3 and 2,4 (default)

For programming iCE - Shunt 3,4 and 1,2

J7: Remove shunt only for Programming iCE.

Replace shunt for programming Flash and for normal operation.

Short-circuit Jumper

iCE_MISO

FLASH_MOSI

iCE_MOSI

iCE_MISO

FLASH_MISO

+3.3V

iCE_SCK2

iCE_SS_B2

FLASH_MOSI2

FLASH_MISO 2

Title

veRrebmuNtnemucoDeziS

teehS:etaD of

AXELSYS

ICE40HX8K-B-EVN

iCE40-HX8K Breakout Board - SPI

66Jul 26, 2013

Title

veRrebmuNtnemucoDeziS

teehS:etaD of

AXELSYS

ICE40HX8K-B-EVN

iCE40-HX8K Breakout Board - SPI

66Jul 26, 2013

Title

veRrebmuNtnemucoDeziS

teehS:etaD of

AXELSYS

ICE40HX8K-B-EVN

iCE40-HX8K Breakout Board - SPI

66Jul 26, 2013

JU2

63429-202LF

JU2

63429-202LF

R51

10K

R51

10K

J7J7

C63

0.1uF

C63

0.1uF

R49

10K

R49

10K

J6J6

JU3

63429-202LF

JU3

63429-202LF

SPI

iCE40HX8K-CT256

U3E

SPI

iCE40HX8K-CT256

U3E

SPI_VCC

N13 PIOS_00/SPI_SO P12

PIOS_01/SPI_SI P11

PIOS_02/SPI_SCK R11

PIOS_03/SPI_SS_B R12

C64

0.1uF

C64

0.1uF

JU1

63429-202LF

JU1

63429-202LF

R52

10K

R52

10K

R50

10K

R50

10K

N25Q032A13ESC40F

SDI

SCK

HOLD 7

VCC 8

GND

SDO 2

iCE40HX-8K Breakout Board

Evaluation Board User Guide

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

18 FPGA-EB-02031-1.2

Revision History

Revision 1.2, July 2020

Section

Change Summary

All

Changed document number from EB85 to FPGA-EB-02031.

Updated document template.

Added Disclaimers section.

Acronyms in This Document

Added this section.

Board Power

Updated section content.

Appendix A. Schematic Diagrams

Updated Figure A.5.

Revision 1.1, January 2016

Section

Change Summary

Demonstration Design

Changed demonstration design to design file.

Technical Support Assistance

Updated this section.

Revision 1.0, November 2013

Section

Change Summary

All

Initial release.

www.latticesemi.com

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