Lattice Semiconductor MachXO5T-NX-Development Board User manual

MachXO5T-NX-Development Board
Evaluation Board User Guide
FPGA-EB-02052-1.0
April 2023

MachXO5T-NX-Development Board
Evaluation Board User Guide
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02058-1.0
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the Buyer.
Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited
testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice
products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a
situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is
proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at
any time without notice.

MachXO5T-NX-Development Board
Evaluation Board User Guide
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02058-1.0 3
Contents
Acronyms in This Document.................................................................................................................................................6
1. Introduction..................................................................................................................................................................7
1.1. MachXO5T-NX Development Board....................................................................................................................7
1.2. Features ..............................................................................................................................................................8
1.3. LFMXO5-100T Device ..........................................................................................................................................9
2. Applying Power to the Board......................................................................................................................................10
3. Hard JTAG/I2C Programming ......................................................................................................................................12
3.1. JTAG Download Interface..................................................................................................................................13
3.2. I2C Download Interface .....................................................................................................................................14
4. Soft JTAG/UART User Interface ..................................................................................................................................16
4.1. Soft JTAG User Interface ...................................................................................................................................16
4.2. Soft UART User Interface ..................................................................................................................................17
5. LFMXO5-100T Clock Sources ......................................................................................................................................18
6. SGMII Ethernet Connections ......................................................................................................................................19
7. PCIe Gold Finger .........................................................................................................................................................21
8. Optional SMA Headers ...............................................................................................................................................22
9. LPDDR4 Memory Controller Interface........................................................................................................................24
10. Generating the Programming File ..........................................................................................................................25
11. Programming the MachXO5-NX Device..................................................................................................................27
12. Headers and Test Connections ...............................................................................................................................32
12.1. Versa Headers ...................................................................................................................................................32
12.2. Arduino Board GPIO Headers............................................................................................................................34
12.3. FPC Headers ......................................................................................................................................................35
12.4. Aardvark Header (DNI)......................................................................................................................................36
12.5. Raspberry Pi Board GPIO Header ......................................................................................................................37
12.6. PMOD Headers..................................................................................................................................................37
12.7. User I2C Interface ..............................................................................................................................................38
12.8. ADC and Potentiometer ....................................................................................................................................38
13. LEDs and Switches ..................................................................................................................................................40
13.1. 8-Position DIP Switch ........................................................................................................................................40
13.2. General Purpose Push Buttons .........................................................................................................................41
13.3. General Purpose LEDs .......................................................................................................................................41
14. Software Requirements..........................................................................................................................................42
15. Storage and Handling .............................................................................................................................................42
16. Ordering Information..............................................................................................................................................42
TechnicalSupport Assistance ..............................................................................................................................................43
Appendix A. MachXO5T-NX Development Board Schematics............................................................................................44
Appendix B. MachXO5T-NX Development Board Bill of Materials.....................................................................................55
Appendix C. User Defined Preference File..........................................................................................................................63
Appendix D. MachXO5T-NX Development Board Errata....................................................................................................68
References..........................................................................................................................................................................69
RevisionHistory...................................................................................................................................................................70

MachXO5T-NX-Development Board
Evaluation Board User Guide
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02058-1.0
Figures
Figure 1.1. Top View of MachXO5T-NX Development Board ...............................................................................................7
Figure 1.2. Bottom View of MachXO5T-NX Development Board .........................................................................................8
Figure 2.1. Board Power Supply..........................................................................................................................................10
Figure 3.1. JTAG/I2C Programming Architecture ................................................................................................................12
Figure 3.2. Radiant Programmer Detect Dual Ports ...........................................................................................................12
Figure 3.3. Level Shift for JTAG Download Interface ..........................................................................................................13
Figure 3.4. JTAG Test Header..............................................................................................................................................13
Figure 3.5. I2C Programming Mode ....................................................................................................................................14
Figure 4.1. JTAG/UART User Interfacing.............................................................................................................................16
Figure 5.1. Onboard Clock Resources.................................................................................................................................18
Figure 6.1. SGMII ×2 Interfacing .........................................................................................................................................19
Figure 7.1. Top Side of PCIe Edge Connector......................................................................................................................21
Figure 8.1. SMA Interfacing for x1 Serdes RX and TX .........................................................................................................22
Figure 8.2. SMA Interfacing for x1 SerDes Rx and Tx..........................................................................................................22
Figure 8.3. SMA Clock Input................................................................................................................................................23
Figure 10.1. Radiant Software –Open Project Dialog Box .................................................................................................25
Figure 10.2. Radiant Software –Process Toolbar Initial State............................................................................................25
Figure 10.3. Radiant Software –State of the Processes Toolbar Completion ....................................................................26
Figure 11.1. Radiant Software –Radiant Programmer.......................................................................................................27
Figure 11.2. Radiant Programmer –Initial Opened............................................................................................................28
Figure 11.3. Radiant Programmer –Scan Device ...............................................................................................................28
Figure 11.4. Radiant Programmer –Device Detected ........................................................................................................29
Figure 11.5. Radiant Programmer –Select Target Memory for Device Properties ............................................................29
Figure 11.6. Radiant Programmer –Device Properties for FLASH Configuration Memory ................................................30
Figure 11.7. Radiant Programmer –Ready for Flash Programming ...................................................................................31
Figure 11.8. Radiant Programmer –Flash Programming Successful ..................................................................................31
Figure 12.1. Circuit Design for ADC0...................................................................................................................................39
Figure 12.2. Circuit Design for ADC1...................................................................................................................................39
Figure 12.3. Trimmer Wiper Description ............................................................................................................................39
Figure 13.1. Eight-Position DIP Switch Circuits...................................................................................................................40
Figure 13.2. Eight-position DIP Switch................................................................................................................................40
Figure A. 1. Title Page .........................................................................................................................................................44
Figure A. 2. Block Diagram and Power Tree .......................................................................................................................45
Figure A. 3. USB to Hard JTAG I/F .......................................................................................................................................46
Figure A. 4. USB to Soft JTAG I/F (BANK0) ..........................................................................................................................47
Figure A. 5. PMOD0/Versa Connector (BANK1/2) ..............................................................................................................48
Figure A. 6. LPDDR4 (BANK3)..............................................................................................................................................49
Figure A. 7. PCIE&FPC Headers (BANK4) ............................................................................................................................50
Figure A. 8. GBE and RJ45 (BANK5).....................................................................................................................................51
Figure A. 9. Multiple Headers (BANK6/7) ...........................................................................................................................52
Figure A. 10. Power Rails ....................................................................................................................................................53
Figure A. 11. Power Regulators ..........................................................................................................................................54

MachXO5T-NX-Development Board
Evaluation Board User Guide
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02058-1.0 5
Tables
Table 2.1. Onboard Major Power Rails...............................................................................................................................11
Table 2.2. LFMXO5-100T IO Bank Power Rails Stuff ...........................................................................................................11
Table 2.3. LFMXO5-100T Major Power Rails Stuff..............................................................................................................11
Table 3.1. Config JTAG Connections ...................................................................................................................................14
Table 3.2. Other Config JTAG Control Signals.....................................................................................................................14
Table 3.3. Download I2C Connections.................................................................................................................................15
Table 4.1. Soft JTAG Connections .......................................................................................................................................16
Table 4.2. Soft UART Connections ......................................................................................................................................17
Table 5.1. Input Clock Options............................................................................................................................................18
Table 6.1. SGMII Ethernet PHY Interfacing.........................................................................................................................19
Table 6.2. SGMII Ethernet PHY0 Strapping Configuration..................................................................................................20
Table 6.3. SGMII Ethernet PHY1 Strapping Configuration..................................................................................................20
Table 6.4. PHY device VDD Power Supply Options .............................................................................................................20
Table 7.1. Gold Finger Pin Connections..............................................................................................................................21
Table 8.1. Connections for SMA Serdes signal pair ............................................................................................................22
Table 8.2. Connections for External SMA Reference Clock ................................................................................................22
Table 8.3. Single-end External SMA Clock ..........................................................................................................................23
Table 9.1. LPDDR4 Memory Controller Interconnections ..................................................................................................24
Table 12.1. Versa J8 Header Pin Connections.....................................................................................................................32
Table 12.2. Versa J9 Header Pin Connections.....................................................................................................................33
Table 12.3. Arduino J2 Pin Connections .............................................................................................................................34
Table 12.4. Arduino J3 Pin Connections .............................................................................................................................34
Table 12.5. Arduino J4 Pin Connections .............................................................................................................................34
Table 12.6. Arduino J5 Pin Connections .............................................................................................................................35
Table 12.7. FPC Header Pin Connections............................................................................................................................35
Table 12.8. Aardvark J7 Header Pin Connections ...............................................................................................................36
Table 12.9. Raspberry Pi J6 Header Pin Connections .........................................................................................................37
Table 12.10. J15 Header Pin Connections ..........................................................................................................................37
Table 12.11. J16 Header Pin Connections ..........................................................................................................................38
Table 12.12. I2C Connections..............................................................................................................................................38
Table 13.1. Four-Position DIP Switch Signals......................................................................................................................40
Table 13.2. Push Button Switch Signals ..............................................................................................................................41
Table 13.3. LED Signals .......................................................................................................................................................41
Table 16.1 Ordering Information........................................................................................................................................42

MachXO5T-NX-Development Board
Evaluation Board User Guide
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02058-1.0
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
CMOS
Complementary Metal-Oxide Semiconductor
DNI
Do Not Install
FTDI
Future Technology Devices International
FPC
Flexible Printed Circuit
GPIO
General Purpose Input/Output
I2C
Inter-Integrated Circuit
LDO
Low Dropout
LVDS
Low Voltage Differential Signaling
PCIe
Peripheral Component Interconnect Express
SLVS
Scalable Low Voltage Signaling
SPI
Serial Peripheral Interface
TPI
Twisted Pair Interface

MachXO5T-NX-Development Board
Evaluation Board User Guide
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02058-1.0 7
1. Introduction
The Lattice Semiconductor MahXO5T™-NX Development Board allows you to investigate and experiment with the
features of the LFMXO5-100T device. The features of the MachXO5T-NX Development Board can assist you with the
rapid prototyping and testing of your specific designs.
The MachXO5T-NX Development Board is part of the MachXO5T-NX Development Kit, which includes the following:
•MachXO5T-NX Development Board pre-loaded with the demo design
•12 V AC/DC Power adapter
•Mini USB cable
•Quick Start Guide
The contents of this user guide include top-level functional descriptions of the various portions of the development
board, descriptions of the onboard headers, diodes and switches, and a complete set of schematics.
1.1. MachXO5T-NX Development Board
Along with the LFMXO5-100T device, the MachXO5T-NX Development Board also includes features to expand the
LFMXO5-100T usability with Arduino, Raspberry, PCIe, RJ45, Versa, and Aardvark headers.
Figure 1.1 shows the top view of the MachXO5T-NX Development Board.
Figure 1.2 shows the bottom view of this board.
LFMXO5-100T
Device (U3)
DIP Switches (SW1)
Versa Headers (J8, J9)
JTAG Header (J1)
Push Buttons
(SW2~SW5)
Trimmer 10K
(POT1)
PMOD
Header
(J16)
PMOD Header (J15)
Power Switch
(SW6)
User LEDs
(D1~D8)
LPDDR4
(U9)
FPC Header (CN2) RJ45 × 2 (J14)
× 1 PCIe Fingers (CN1)
Figure 1.1. Top View of MachXO5T-NX Development Board

MachXO5T-NX-Development Board
Evaluation Board User Guide
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-EB-02058-1.0
User USB
Header (J19)
Config USB Header
(J11)
User FTDI
Device (U18)
Config FTDI
Device (U1)
100 MHz HSCL
Clock (X8)
125 MHz
LVDS Clock
(X9)
12V DC Power Jack
(J17)
Fuse
(U10)
FPC Header
(CN3)
SGMII PHY1
(U7)
SGMII PHY0
(U6)
Arduino Headers (J2~J5)
Raspberry Pi
Header (J6)
27 MHz LVCMOS Clock
(X4)
Figure 1.2. Bottom View of MachXO5T-NX Development Board
1.2. Features
•On board LFMXO5-100T Device
•Two Gbe PHY RJ45 connectors, with SGMII PHY support
•LPDDR4 up to 1066 Mbps, ×16 bits
•PCIe Gen2 x1 Edge Connector
•Optional SMA to support ×1 PCIe
•Versa Headers bridge with Lattice ASC Demo Board to support L-ASC10
•General Purpose Input/Output (GPIO) interface with PMOD, Arduino and Raspberry Pi boards
•USB-B connection for device programming with JTAG and Inter-Integrated Circuit (I2C) utility
•Additional USB-B connection for user with Soft JTAG and UART utility
•Eight-position DIP Switches, four push buttons, and eight red LEDs for demo purposes
•ADC interface with 10K POT
•Two 50-pin FPC headers
•Multiple reference clock sources
•Optional Aardvark header
•Support FPGA Power Evaluation
•Lattice Radiant®programming support
Note:
DNI stands for Do Not Install parts and DI stands for Do Install parts for assembly.
Caution:
The MachXO5T-NX Development Board contains ESD-sensitive components. ESD safe
practices should be followed while handling and using the development board.

MachXO5T-NX-Development Board
Evaluation Board User Guide
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02058-1.0 9
1.3. LFMXO5-100T Device
The MachXO5T-NX Development Board features the LFMXO5-100T device in a 400-ball caBGA package. This device
offers a variety of features and programmability that enhances Secure Control PLD functionality with Multiple Boot
capabilities. Its cryptographic engine supports user-mode security features. Along with the cryptographic engine,
numerous system functions are included such as four PLLs and 3,744 kbits of embedded RAM plus hardened
implementations of I2C and SPI, MachXO5T-NX FPGAs feature one hard PCIe link layer IP block which supports PCIe
Gen1, Gen2 with one or two ×1 configuration, with flexible, high performance I/O support numerous single-ended and
differential standards including LPDDR4 controller and SLVS. For more information on the capabilities of LFMXO5-100T
device, see MachXO5-NX Family Data Sheet (FPGA-DS-02102).

MachXO5T-NX-Development Board
Evaluation Board User Guide
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-EB-02058-1.0
2. Applying Power to the Board
The MachXO5T-NX Development Board comes ready to power up with onboard DC/DC switching regulators and Low
Dropout (LDO) generators powered by an external 12 V DC power source. The external power supply can be connected
with the DC power input jack J17 or the PCIe edge connector CN1, which is fused with a surface mounted fuse U10. The
5A fuse prevents the crashed current from flowing into the internal circuits and cause serious damage, as shown in
Figure 2.1.
Fuse (U10)
12V DC
USB Header
(J11)
5V PC1
5V Regulator
(U11)
Slide Switch
(SW6)
PS_5V
VBUS_5V
+12V
1.0V Regulator
(U12) VCC Core/VCCSD/
VCCSDCK(U3)
+1.0V
2.5V LDO
(U13)
3.3V LDO
(U8)
1.8V LDO
(U15)
+2.5V
Raspberry Pi
Header (J6)
Arduino
Header (J4)
JP7
VCCIO1/2 (U3)
VCCIO0(U3)
JP6
J24
+3.3V
+3.3V
VCCIO6(U3)
J21
+3.3V
+3.3V_AR
VCCIO7(U3)
J22
+3.3V_RASP
+3.3V
VCCIO4(U3)
J23
+1.2V
+1.8V
J26
+5.0V
VCCAUX/VCCAUXA/VCCAUXH/VCCADC/
VCCPLLSD/VCCAUXSDQ (U3)
+1.8V
12V_IN_PICE
Power Jack
(J17)
+1.8V
LPDDR4 VDDQ/
VDD2 (U9)
PMOD0(J15)
User JTAG (J18)
USB Header
(J19)
5V PC2
JP15
12V PC
PCIe Edge
Connector (CN1)
+2.5V
PMOD1 (J16)
VCCIO5 (U3)
J20
+1.2V
+1.8V
1.1V LDO
(U17)
1.2V LDO
(U16)
+2.5V
+2.5V
VCCIO3(U3)
+1.1V
PHY0 VDDP/PHY1 VDDP (U6/U7)
PHY0 VDD (U6)
Reg0 out
PHY0 (U6)
+3.3V
J28
PHY1 VDD (U7)
Reg1 out
PHY1 (U7)
+3.3V
FTDI1 VCCIO (U18)
+3.3V
FTDI0 VCCIO (U1)
+3.3V
LPDDR4 VDD1 (U9)
+1.8V
Config JTAG (J1)
Figure 2.1. Board Power Supply
The onboard 5 V power regulator U11 provides 90% power convert efficiency from 12 V DC when output current
between 50 mA and 3 A. It is distributed to 3.3 V, 2.5 V LDOs and 1.0 V regulator through one side of slide switch SW6
to support onboard devices. Through another side of SW6, this board can take the 5 V DC power from USB header J11
as well to supply those LDOs. For some low power applications, JP15 can be used to double the power supplier
capability, if J19 is also plugged into the same PC that is connected to J11. You need to ensure 5 V DC power consume
less than maximum capability from each USB port of PC when taking power from J11 and J19.
For the board extension, 5 V DC power can also supply Raspberry Pi and Arduino boards through the jumpers and
onboard headers, to consolidate AC/DC adapters for stack boards system. Conversely, 5 V DC power for MachXO5T-NX
Development Board can be supplied either from mated Raspberry Pi or Arduino Boards, if they are powered up by
external AC/DC adapters already. You need to ensure 5 V power from a single source when adding JP6 or JP7 jumpers.
However, maintain 5 V DC supplier is the basic requirement to power on the board, by checking the power good blue
LED D18.
The onboard 1.1 V, 1.2 V, and 1.8 V LDOs take the power from 2.5 V LDO output.
Table 2.1 summarizes onboard major power rails and their test points.

MachXO5T-NX-Development Board
Evaluation Board User Guide
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02058-1.0 11
Table 2.1. Onboard Major Power Rails
Power Net Name
Primary Source
Test Point
+12V
DC Power Jack (J17) or PCIE Edge Connecter (CN1)
TP20
PS_5V
DC/DC Regulator (U11)
—
VBUS_5V
Mini-USB Headers (J11 or J19)
JP15
+5.0V
Selected by Slide switch (SW6)
TP14
+3.3V
LDO (U8)
TP15
+2.5V
LDO (U13)
TP16
+1.8V
LDO (U15)
TP17
+1.2V
LDO (U16)
TP18
+1.1V
LDO (U17)
TP19
+1.0V
DC/DC Regulator (U12)
TP21
+3.3V_RASP
Raspberry Pi Header (J6)
—
+3.3V_AR
Arduino Header (J4)
—
As shown in Figure 2.1, this board provides multiple power options for I/O bank voltage flexibility. Table 2.2
summarizes the VCCIO support matrix on this board. For an example, VCCIO1 and VCCIO2 share the same three positions
jumper J24 and short its Pin 1 and Pin 2 can bring the 3.3 V LDO output to both I/O bank 1 and bank 2. For power
consumption evaluation, this board facilitate some two-position jumpers with 1 Ωsense resistors to measure the
voltage drop on each power rail, then the supply current can be calculated.
Table 2.2. LFMXO5-100T IO Bank Power Rails Stuff
LFMXO5-100T
Power (U3)
Jumpers
3.3 V
2.5 V
1.8 V
1.2 V
1.1 V
Ext 3.3 V
Power
Test
Point
Sense
Resistor
of 1 Ω
VCCIO0
—
Fixed
—
—
—
—
—
JP19
R132
VCCIO1
J24
Pin 1-2
Pin 2-3
—
—
—
—
JP16
R133
VCCIO2
J24
Pin 1-2
Pin 2-3
—
—
—
—
JP20
R134
VCCIO3
—
—
—
—
—
Fixed
—
JP21
R61
VCCIO4
J23
—
—
Pin 1-2
Pin 2-3
—
—
JP22
R62
VCCIO5
J20
—
—
Pin 1-2
Pin 2-3
—
—
JP23
R63
VCCIO6
J21
Pin 1-2
—
—
—
—
Pin 2-3
JP24
R64
VCCIO7
J22
Pin 1-2
—
—
—
—
Pin 2-3
JP25
R153
Other than power rail for each I/O Bank, this board also provides some test points to evaluate the major power
consumptions for LFMXO5-100T device as listed in Table 2.3.
Table 2.3. LFMXO5-100T Major Power Rails Stuff
LFMXO5-100T Power (U3)
Power Test Point
Voltage Drop Resistor
Resistance
VCC_CORE
JP18
R112
0.01 Ω
VCC_AUX/VCC_AUXH/VCCAUXA
JP14
R131
1 Ω
VCC_ADC
JP17
R137
1 Ω

MachXO5T-NX-Development Board
Evaluation Board User Guide
© 2023 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-EB-02058-1.0
3. Hard JTAG/I2C Programming
The hardened JTAG/I2C programming architecture of the MachXO5T-NX Development Board is shown in Figure 3.1. The
board has a built-in download controller for programming the LFMXO5-100T device. It uses an FT2232H Future
Technology Devices International (FTDI) part U1 to convert USB to JTAG from port A, or convert USB to I2C from port B.
Using Detect Cable function with Radiant programming software installed, you can detect dual ports after power up
the board and connect the mini USB to USB-A cable from J11 to your PC,ensuring FTDI reset control jumper JP9 is not
populated as default. The software select option FTUSB-0 is dedicate for hard JTAG and FTUSB-1 is dedicated for hard
I2C which is mapping with port A and port B from hardware perspective, as shown in Figure 3.2.
Mini-USB
(J11)USB FT2232H
(U1)
Port A
Port B
LFMXO5-100T
(U3)
Level
Shift
(U14)
rst#
JP9
GND
FTDI_SCL
FTDI_SDA
SCL0
SDA0
JP12 JP13
TDI
TCK
TMS
TDO
NX_TDI
NX_TCK
NX_TMS
NX_TDO
OEN
Config JTAG Header (J1)
JP1
3.3V
JP27
Figure 3.1. JTAG/I2C Programming Architecture
Figure 3.2. Radiant Programmer Detect Dual Ports

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FPGA-EB-02058-1.0 13
3.1. JTAG Download Interface
A level shifter SN74AVC4T774 U14 from TI is inserted between Config FTDI Port A and LFMXO5-100T JTAG port to make
sure the FTDI fixed I/O voltage can adapt with flexible voltage selection of bank 2 of the FPGA, as shown in Figure 3.3.
An eight-pin header J1 (Figure 3.4) allowing you to probe the JTAG signals to access LFMXO5-100T JTAG port from the
external JTAG host, such as external Lattice HW-USBN-2B Programming Cable (available separately), or to access SSPI
port from the external SPI host. In those cases, jumper JP1 must be added to pull OEN high and ensure U14 to output
tri-state mode so as to avoid multi-drivers on those shared signals. The JTAG connections between J1 and
LFMXO5-100T are listed in Table 3.1.
Figure 3.3. Level Shift for JTAG Download Interface
Figure 3.4. JTAG Test Header

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14 FPGA-EB-02058-1.0
Table 3.1. Config JTAG Connections
J1 Pin Number
JTAG Net Name
LFMXO5-100T Ball Location
for JTAG
Optional SSPI Function
1
VCCIO2
—
—
2
NX_TDO
E16
SSI
3
NX_TDI
C16
SSO
4
—
—
—
5
—
—
—
6
NX_TMS
B16
SCSN
7
GND
—
—
8
NX_TCK
B19
SCLK
The MachXO5T-NX Development Board also provides test points for other dedicated JTAG configuration pins as shown
in Table 3.2.
Table 3.2. Other Config JTAG Control Signals
Net Name
LFMXO5-100T Ball Location
LED Indicator
Test Point
JTAGEN
A14
—
Pin 2 of JP2
PROGRAMN
G10
—
—
INITN
H10
D11
TP5
DONE
H11
D10
TP6
JP2 for JTAGEN is used to pull down the JTAGEN to disable JTAG port. Using SW5 push button with PROGRAMN reloads
the bitstream from internal Flash when PROGRAMN_PORT function is enabled by software.
3.2. I2C Download Interface
The USB hub on the PC can also detect the addition of the USB function on Config FTDI Port B. You can select the port
FTUSB-1 on the programmer interface for the accessing from Config FTDI Port B to the LFMXO5-100T dedicated I2C
download port (Figure 3.2) that is named as FTDI_SDA/FTDI_SCL with 2.2 kΩpull up resistor each. The Diode D21 is
inserted to support I2Cclock stretching mode with JP27 added to drive FTDI_SCL from FTDI, but JP27 cannot be added
when using I2C config mode. Figure 3.5 details the design of Config FTDI Port B for dedicated I2C download interface.
Table 3.3 summarizes the interconnection with LFMXO5-100T and its supported circuits. JP12 and JP13 are used to
connect the dedicated I2C download port of LFMXO5-100T with the bridge I2C bus SDA0/SCL0 cross the whole board, in
case you need access I2C download port from other on board headers other than Config FTDI part. For the detail
connection from other headers to bridge I2C bus SDA0/SCL0, refer to the User I2C Interface section.
Figure 3.5. I2C Programming Mode

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FPGA-EB-02058-1.0 15
Table 3.3. Download I2C Connections
Download I2C Net Name
LFMXO5-100T Ball
Location for JTAG
2.2 kΩPull up Resistor
Bridge I2C Net
Name
Bridge Jumper
FTDI_SCL
A19
R33
SCL0
JP12
FTDI_SDA
A18
R34
SDA0
JP13
For more information on LFMXO5-100T JTAG/ I2C programming, refer to MachXO5-NX Programming and Configuration
User Guide (FPGA-TN-02271).

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16 FPGA-EB-02058-1.0
4. Soft JTAG/UART User Interface
The soft JTAG/UART user interface for the MachXO5T-NX Development Board is shown in Figure 4.1. Supposedly it also
uses an FT2232H FTDI part U18 to convert USB to user JTAG from port A, or convert USB to UART from port B. Using
Detect Cable function with Radiant programming software installed and ensuring FTDI reset control jumper JP8 is not
populated in default, as shown in Figure 3.2, you can detect other dual ports after power up the board. You can then
connect the mini USB to USB-A cable from J19 to your PC. The software select option FTUSB-0 is targeted for user JTAG,
and FTUSB-1 is targeted for UART that is mapped with port A and port B from hardware perspective.
Mini-USB
(J19)USB FT2232H
(U18)
Port A
Port B
LFMXO5-100T
(U3)
rst#
JP8
GND
RS232_RX_TTL
UTDI
UTCK
UTMS
UTDO
User JTAG Header (J18)
RS232_TX_TTL
Figure 4.1. JTAG/UART User Interfacing
4.1. Soft JTAG User Interface
User FTDI Port A is connected with GPIOs in Bank 1 directly. You need allocate GPIOs for adaption with JTAG signals by
programmable logic, which is defined by FTDI Port A when converting USB to JTAG through FTUSB-0. J18 is an eight-pin
standalone JTAG header that is used with an external Lattice download cable (available separately) when the FTDI part
is disabled from the JTAG chain after setting JP8. J18 can also be used as test point when USB to JTAG is working.
Table 4.1. Soft JTAG Connections
J18 Pin Number
FTDI Signal
JTAG Net Name
LFMXO5-100T Ball Location
1
—
VCCIO1
—
2
UADBUS2
UTDO
F12
3
UADBUS1
UTDI
F13
4
—
—
—
5
—
—
—
6
UADBUS3
UTMS
G13
7
—
GND
—
8
UADBUS0
UTCK
G14

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FPGA-EB-02058-1.0 17
4.2. Soft UART User Interface
User FTDI Port B is also connected with GPIOs in Bank 0 directly. You need allocate GPIOs for adaption with UART
signals by programmable logic, which is defined by FTDI Port B when converting USB to UART through FTUSB-1.
Table 4.2. Soft UART Connections
FTDI Signal
UART Net Name
LFMXO5-100T Ball Location for Port A
UBDBUS0
RS232_RX_TTL
C15
UBDBUS1
RS232_TX_TTL
D15
UBDBUS2
RTSn
B15
UBDBUS3
CTSn
A15
UBDBUS4
DTRn
E13
UBDBUS5
DSRn
E12
UBDBUS6
DCDn
D14
UBDBUS7
RI
E15

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18 FPGA-EB-02058-1.0
5. LFMXO5-100T Clock Sources
The MachXO5T-NX Development Board has multiple external clock options for the LFMXO5-100T applications as shown
in Figure 5.1.
•12 MHz from U1 (FTDI)
•27 MHz from ×4 (OSC MEM)
•External clock source from J10 (SMA)
•Differential 100 MHz from ×7
•Differential 100 MHz from ×8
•Differential 125 MHz from ×9
•Differential external clock source from SMA4 and SMA5 (SMA pair)
J8
12 MHz
U1
x4
x9
x7
x8
J10
EXT_CLK
100 MHz
125 MHz
JP11
EXPCON_OSC J11
USB
27 MHz
SMA4/5
EXT1_CLK
100 MHz R159
Figure 5.1. Onboard Clock Resources
You need take care 12 MHz clocks from the FT2232H FTDI U1 device are not always on without some hardware
configuration. SMA clocks need source from external boards. Refer to Table 5.1 for those clock utilization and enable
conditions.
Table 5.1. Input Clock Options
Clock
Frequency
Net Name
LFMXO5-
100T Ball
Location
Clock
Source
IO Type
Enable Conditions
12 MHz
EXPCON_OSC
J16
U1
LVCMOS33
Need add R159 and JP11. USB header J11
connected with power on.
27 MHz
27M_OSC_IN
C2
X4
LVCMOS33
Always on. Use J25 to disable or control clock
output.
EXT_CLK
OSC_IN
A17
J10
LVCMOS33 or
LVCOMS25
Need add J10 SMA. Connect to external clock
generator through SMA cable.
100 MHz
EXT0_CLKp/
EXT0_CLKn
C11/C12
X7
LVDS
Always on. Dedicated reference clock for PCS.
Refer to the SerDes/PCS User Guide FPGA-TN-
02245 for details.
100 MHz
LVSTLD_100MHzp/
LVSTLD_100MHzn
U19/U20
X8
LVSTLD
Always on. Generated by the HSCL clock and AC
coupled to the 1.1 V I/O bank for LPDDR4.
125 MHz
LVDS_125MHzp/
LVDS_125MHzn
R3/P3
X9
LVDS
Always on. Dedicated reference clock for PCS.
Refer to the CertusPro-NX SerDes/PCS User Guide
(FPGA-TN-02245) for details.
SMA_CLK
EXT1_CLKp/EXT1_
CLKn
B13/C13
SMA4/
SMA5
LVDS
Need add SMA4 and SMA5. Connect to external
differential clock generator through SMA cables.

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FPGA-EB-02058-1.0 19
6. SGMII Ethernet Connections
This section describes the MachXO5T-NX Development Board SGMII application for Ethernet connections. This board
can support two independent Ethernet connections through on-board SGMII PHY devices PHY0 and PHY1, which is
GPY115C0VI from Maxlinear, as shown in Figure 6.1. Table 6.1 listed the signals from the FPGA interfacing with SGMII
PHY devices.
LFMXO5-100T
(U3)
PHY0
(U6)
PHY1
(U7)
RJ45 x2
(J14)
SGMII TX0
SGMII TX1
SGMII RX0
SGMII RX1
TPI0
Port B
Management Port 1
Management Port 0
TPI1
Port A
Figure 6.1. SGMII ×2 Interfacing
Table 6.1. SGMII Ethernet PHY Interfacing
PHY Interface
LFMXO5-100T Ball
Location
Net Name
Pin Number of PHY Device
PHY0 (U6)
P6
PHY0_MDIO
10
U2
PHY0_MDC
11
R4
PHY0_MDINT
12
T5
PHY0_EXINT0
13
P2
SGMII_FPGA_RX0P
25
R2
SGMII_FPGA_RX0N
24
T1
SGMII_FPGA_TX0P
27
U1
SGMII_FPGA_TX0N
28
PHY1 (U7)
P7
PHY1_MDIO
10
T2
PHY1_MDC
11
P4
PHY1_MDINT
12
U5
PHY1_EXINT0
13
R5
SGMII_FPGA_RX1P
25
P5
SGMII_FPGA_RX1N
24
P1
SGMII_FPGA_TX1P
27
R1
SGMII_FPGA_TX1N
28
The pin strapping configuration for both SGMII PHY devices have been implemented on board, as shown in Table 6.2
and Table 6.3.

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20 FPGA-EB-02058-1.0
Table 6.2. SGMII Ethernet PHY0 Strapping Configuration
U6 Pin Number
Configuration Item
Description
Logic Value in Default
1K Pull up Resistor
1K Pull down Resistor
37
PS_PHY_MADDR(0)
0
R182 (DNI)
R172
35
PS_PHY_MADDR(1)
0
R178 (DNI)
R173
34
PS_PHY_MADDR(2)
0
R179 (DNI)
R174
3
PS_PHY_MADDR(3)
0
R180 (DNI)
R175
2
PS_PHY_MADDR(4)
0
R181 (DNI)
R176
12
PS_MINT_POL
0
R183 (DNI)
R171
18
PS_RJ45_TAP
0
R184 (DNI)
R170
19
PS_MDIO_VOLTAGE
0
NA
R177
Table 6.3. SGMII Ethernet PHY1 Strapping Configuration
U7 Pin Number
Configuration Item
Description
Logic Value in Default
1K Pull up Resistor
1K Pull down Resistor
37
PS_PHY_MADDR(0)
0
R224(DNI)
R215
35
PS_PHY_MADDR(1)
0
R220(DNI)
R216
34
PS_PHY_MADDR(2)
0
R221(DNI)
R217
3
PS_PHY_MADDR(3)
0
R222(DNI)
R218
2
PS_PHY_MADDR(4)
0
R223(DNI)
R219
12
PS_MINT_POL
0
R225(DNI)
R214
18
PS_RJ45_TAP
0
R226(DNI)
R213
19
PS_MDIO_VOLTAGE
0
—
R202
MachXO5T-NX Development Board provides two options to supply the VDD power of PHY devices, as shown in
Table 6.4. One option is to supply the VDD with on-board 1.0 V regulator. The other option needs additional power
from the on-board 3.3 V LDO and converts to 1.0 V output by the internal regulator of PHY devices. It is recommended
to use the first option to improve the power efficiency and off load the 3.3V LDO on this board.
Table 6.4. PHY device VDD Power Supply Options
PHY VDD
Jumper
Supply from On-board Regulator
Supply from in-chip Regulator
U6
J26
Pin 2-3 (U12)
Pin 1-2 (U6)
U7
J28
Pin 2-3 (U12)
Pin 1-2 (U7)