Lattice Semiconductor MachXO2 Breakout Board User manual

MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
FPGA-EB-02051-2.3
February 2022

MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02051-2.3
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the
Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject
to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No
Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could
create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is
proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at
any time without notice.

MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02051-2.3 3
Contents
Acronyms in This Document.................................................................................................................................................5
1. Introduction..................................................................................................................................................................6
2. Features........................................................................................................................................................................6
3. Storage Handling ..........................................................................................................................................................8
4. Software Requirements................................................................................................................................................8
5. MachXO2 Device...........................................................................................................................................................8
6. Demonstration Design..................................................................................................................................................9
6.1. Run the Demonstration Design...........................................................................................................................9
6.2. Download Demo Designs ..................................................................................................................................10
6.3. Programming a Demo Design with the Lattice Diamond Programmer.............................................................11
7. MachXO2 Breakout Board..........................................................................................................................................12
7.1. Overview ...........................................................................................................................................................12
7.2. Subsystems........................................................................................................................................................13
7.2.1. Clock Sources................................................................................................................................................13
7.2.2. Expansion Header Landings..........................................................................................................................13
7.2.3. MachXO2 FPGA.............................................................................................................................................19
7.2.4. JTAG Interface Circuits..................................................................................................................................19
7.2.5. Power Supply................................................................................................................................................20
7.2.6. Test Points ....................................................................................................................................................20
7.2.7. USB Programming and Debug Interface.......................................................................................................20
7.3. Board Modifications..........................................................................................................................................21
7.3.1. Bypassing the USB Programming Interface ..................................................................................................21
7.3.2. Applying External Power...............................................................................................................................21
7.3.3. Measuring Bank and Core Power .................................................................................................................21
7.4. Mechanical Specifications.................................................................................................................................21
7.5. Environmental Requirements ...........................................................................................................................21
7.6. Glossary.............................................................................................................................................................21
8. Troubleshooting .........................................................................................................................................................22
8.1. LEDs Do Not Flash..............................................................................................................................................22
8.2. USB Cable Not Detected....................................................................................................................................22
8.3. To access the Troubleshooting the USB Driver Installation Guide....................................................................22
8.4. Determine the Source of a Pre-Programmed Device.........................................................................................22
9. Ordering Information .................................................................................................................................................23
TechnicalSupport Assistance ..............................................................................................................................................24
Appendix A. Schematic Diagrams.......................................................................................................................................25
Appendix B. Bill of Materials...............................................................................................................................................30
RevisionHistory...................................................................................................................................................................32

MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02051-2.3
Figures
Figure 2.1. MachXO2 Breakout Board, Top Side...................................................................................................................7
Figure 6.1. Demonstration Design Block Diagram ................................................................................................................9
Figure 7.1. MachXO2 Breakout Board Block Diagram ........................................................................................................12
Figure 7.2. J3/J4 Header Landing Callout............................................................................................................................18
Figure 7.3. J3/J5 Header Landing Callout............................................................................................................................18
Figure 7.4. J1 Header Landing and LED Array Callout.........................................................................................................19
Figure A.1. Block Diagram...................................................................................................................................................25
Figure A.2. USB Interface to JTAG.......................................................................................................................................26
Figure A.3. FPGA .................................................................................................................................................................27
Figure A.4. FPGA .................................................................................................................................................................28
Figure A.5. Power LEDs .......................................................................................................................................................29
Tables
Table 7.1. Breakout Board Components and Interfaces.....................................................................................................13
Table 7.2. Expansion Connector Reference........................................................................................................................13
Table 7.3. Expansion Header Pin Information (J2)..............................................................................................................14
Table 7.3. Expansion Header Pin Information (J3)..............................................................................................................15
Table 7.4. Expansion Header Pin Information (J4)..............................................................................................................16
Table 7.7. MachXO2 and MachXO3 FPGA Interface Reference..........................................................................................19
Table 7.8. JTAG Interface Reference...................................................................................................................................19
Table 7.9. JTAG Programming Pin Informationz.................................................................................................................20
Table 7.10. LEDs..................................................................................................................................................................20
Table 7.12. Power and User LEDs Reference......................................................................................................................20
Table 7.13. USB Interface Reference ..................................................................................................................................20
Table 9.1. Ordering Information.........................................................................................................................................23

MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02051-2.3 5
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
DIP
Dual In-line Package
FPGA
Field-Programmable Gate Array
LED
Light Emitting Diode
LUT
Look-Up Table
NVCM
Non Volatile Configuration Memory
PCB
Printed Circuit Board
RoHS
Restriction of Hazardous Substances Directive
USB
Universal Serial Bus
WDT
Watchdog Timer

MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02051-2.3
1. Introduction
This user guide describes how to start using the MachXO2™Breakout Board, an easy-to-use platform for evaluating and
designing with the MachXO2 ultra-low density FPGA. Along with the board and accessories, this kit includes a pre-
loaded demonstration design. You may also reprogram the on-board MachXO2 device to review your own custom
designs.
The MachXO2 Breakout Board currently features the MachXO2-7000HE device. A previous version of this board
featured the MachXO2-1200ZE. The board design and features have not changed, and consequently, this document can
be used as a guide for either version of the board. If you require a board featuring the MachXO2-1200ZE, Lattice
recommends the MachXO2 Pico Development Kit.
See the Ordering Information section for more information.
Note: Static electricity can severely shorten the lifespan of electronic components. See the Storage Handling section of
this document for handling and storage tips.
2. Features
The MachXO2 Breakout Board Evaluation Kit includes:
•MachXO2Breakout Board –The board is a 3 inches x 3 inches form factor that features the following on-board
components and circuits:
•MachXO2 FPGA – Current board version: LCMXO2-7000HE-4TG144C
(Previous board version no longer available: LCMXO2-1200ZE-1TG144C)
•USB mini-B connector for power and programming
•Eight LEDs
•60-hole prototype area
•Four 2 x 20 expansion header landings for general I/O, JTAG, and external power
•1 x 8 expansion header landing for JTAG
•3.3 V and 1.2 V supply rails
•Pre-loaded Demo –The kit includes a pre-loaded counter design that highlights use of the embedded MachXO2
oscillator and programmable I/O configured for LED drive.
•USB Connector Cable –The board is powered from the USB mini-B socket when connected to a host PC. The USB
channel also provides a programming interface to the MachXO2 JTAG port.
•Lattice Breakout Board Evaluation Kits Web Page –Visit www.latticesemi.com/breakoutboards for the latest
documentation (including this guide) and drivers for the kit.
The content of this user guide includes demo operation, programming instructions, top-level functional descriptions of
the Breakout Board, descriptions of the on-board connectors, and a complete set of schematics

MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02051-2.3 7
Two 2 × 20 Header
Landings (J3, J5)
Two 2 × 20
Header
Landings
(J2, J4)
MachXO2
PLD (U3)
FTDI USB to
UART/FIFOIC
(U1)
JTAG Header
Landing (J1) USB Mini-B
Socket (J7)
Power LED
(PWR_ON)
Power/GNDTest
Points (TP1, TP2, TP3)
4 × 15 60-Hole
Prototype Array (J6)
LED Array (J4)
Figure 2.1. MachXO2 Breakout Board, Top Side

MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-EB-02051-2.3
3. Storage Handling
Static electricity can shorten the lifespan of electronic components. Observe these tips to prevent damage that could
occur from electro-static discharge:
•Use anti-static precautions such as operating on an anti-static mat and wearing an anti-static wrist-band.
•Store the evaluation board in the packaging provided.
•Touch a metal USB housing to equalize voltage potential between you and the board.
4. Software Requirements
You should install the following software before you begin developing designs for the Breakout Board:
•Lattice Diamond® design software
•FTDI Chip USB hardware drivers (installed as an option within the Diamond installation program)
5. MachXO2 Device
This board currently features the MachXO2-7000HE FPGA which offers embedded Flash technology for instant-on, non-
volatile operation in a single chip. Numerous system functions are included, such as two PLLs and 256 Kbits of
embedded RAM plus hardened implementations of I2C, SPI, timer/counter, and user Flash memory. Flexible, high
performance I/O support numerous single-ended and differential standards including LVDS, and also source
synchronous interfaces to DDR/DDR2/LPDDR DRAM memory. The 144-pin TQFP package provides up to 114 user I/O in
a 20 mm × 20 mm form factor. Previous versions of this board featured the MachXO2-1200ZE PLD in the same package.
This version of the board is no longer available. A complete description of this device can be found in the MachXO2
Family Data Sheet (FPGA-DS-02056).

MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02051-2.3 9
6. Demonstration Design
Lattice provides a simple, pre-programmed demo to illustrate basic operation of the MachXO2 device. The design
integrates an up-counter with the on-chip oscillator.
Note: You may obtain your Breakout Board after it has been reprogrammed. To restore the factory default demo and
program it with other Lattice-supplied examples see the Download Demo Designs section.
6.1. Run the Demonstration Design
Upon power-up, the preprogrammed demonstration design automatically loads and drives the LED array in an
alternating pattern. The program shows a clock generator based on the MachXO2 on-chip oscillator. The counter
module is clocked at the oscillator default frequency of 2.08 MHz to illustrate how low speed timer functions can be
implemented with a FPGA. The 22-bit up-counter further divides the clock to advance the LED display approximately
every 500 ms. The resulting light pattern appears as an alternating pair of lit LEDs per row.
1 × 8 LED
Array
MachXO2
22-bit
Up-Counter
Clock
Generator 2.08 MHz
c_delay[21:0]
c_delay[20]
(~2 Hz)
Figure 6.1. Demonstration Design Block Diagram
WARNING: Do not connect the Breakout Board to your PC before you follow the driver installation procedure of this
section.
Communication with the Breakout Board with a PC via the USB connection cable requires installation of the FTDI chip
USB hardware drivers. Loading these drivers enables the computer to recognize and program the Breakout Board.
Drivers can be loaded as part of the installation of Lattice Diamond design software or Diamond Programmer, or as a
standalone package.
To load the FTDI Chip USB hardware drivers as part of the Lattice Diamond installation:
1. Select Programmer Drivers in the Product Options of Lattice Diamond Setup.
2. Select FTDI Windows USB Driver or All Drivers in the LSC Drivers Install/Uninstall dialog box.
3. Click Finish to install the USB driver.
4. After the driver installation is complete, connect the USB cable from a USB port on your PC to the board’s USB
mini-B socket (J2). After the connection is made, a blue Power LED (D1) lights indicating the board is powered on.
5. The demonstration design automatically loads and drive the LED array in a repeating pattern.
To load the FTDI chip USB hardware drivers via the stand-alone package on a Windows system:
1. Download the FTDI Chip USB Hardware Drivers package from the Lattice website.
2. Extract the FTDI chip USB Hardware driver package to your PC hard drive.
3. Connect the USB cable from a USB port on your PC to the board’s USB mini-B socket (J2). After the connection is
made, a blue Power LED (D1) lights indicating the board is powered on.

MachXO2 Breakout Board Evaluation Kit
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© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-EB-02051-2.3
4. If you are prompted, Windows may connect to Windows Update select No, not this time from available options and
click Next to proceed with the installation. Choose the Install from specific location (Advanced) option and click
Next.
5. Search for the best driver in these locations and click the Browse button to browse to the Windows driver folder
created in the Download Windows USB Hardware Drivers section. Select the CDM 2.04.06 WHQL Certified folder
and click OK.
6. Click Next. A screen displays as Windows copies the required driver files. Windows display a message indicating
that the installation was successful.
7. Click Finish to install the USB driver.
8. The demonstration design automatically loads and drive the LED array in a repeating pattern.
See the Troubleshooting section of this guide if the board does not function as expected.
6.2. Download Demo Designs
The counter demo is preprogrammed into the Breakout Board, however over time it is likely your board will be
modified. Lattice distributes source and programming files for demonstration designs compatible with the Breakout
Board. The demo design for the 1200ZE version of the board is available on the web. Use the same design files for
MachXO2-7000HE. Change the device in the Diamond Software tool and re-run the process flow to generate the JEDEC
for MachXO2-7000HE. The description below references the 7000HE version.
To download demo designs:
1. Browse to the Lattice Breakout Board Evaluation Kits web page (www.latticesemi.com/breakoutboards) of the
Lattice web site. Select MachXO2 Breakout Board Demo Source and save the file.
2. Extract the contents of MachXO21200ZEBreakoutBoardDemoDesignSource.zip to an accessible location on your
hard drive.
3. Open the Project in the Diamond Design Software and change the device to MachXO2-7000HE-4TG144C.
4. Run the Process Flow and regenerate the JEDEC file.
Continue to Programming a Demo Design with the Lattice Diamond Programmer.

MachXO2 Breakout Board Evaluation Kit
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© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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FPGA-EB-02051-2.3 11
6.3. Programming a Demo Design with the Lattice Diamond Programmer
The demonstration design is pre-programmed into the MachXO2/MachXO3 board by Lattice. If you have changed the
design but now want to restore the board to factory settings, use the procedure described below.
To program the MachXO2 device:
1. Install, license and run Lattice Diamond software. See http://www.latticesemi.com/latticediamond for download
and licensing information.
2. Connect the USB cable to the host PC and the MachXO3 board.
3. From Diamond, open the Default_pattern_w_standby.ldf project file.
4. Click the Programmer icon.
5. Click Detect Cable. The Programmer detects the cable (Cable: USB2, Port: FTUSB-0). If the cable is not detected,
see the Troubleshooting section.
6. Click the Program icon. When complete, PASS is displayed in the Status column.

MachXO2 Breakout Board Evaluation Kit
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© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-EB-02051-2.3
7. MachXO2 Breakout Board
This section describes the features of the MachXO2 Breakout Board in detail.
7.1. Overview
The Breakout Board is a complete development platform for the MachXO2 FPGA. The board includes a proto-typing
area, a USB program/power port, an LED array, and header landings with electrical connections to most of the FPGA’s
programmable I/O, power, and JTAG pins. The board is powered by the PC’s USB port or optionally with external
power. You may create or modify the program files and reprogram the board using Lattice Diamond software.
MachXO2-7000HE
or 1200ZE device
2 × 20 Header
Landing (J5)
LED
Array
GPIO
8
2 × 20 Header
Landing (J2)
GPIO 2 × 20 Header
Landing (J3)
Bank 1
Bank 2
Bank 0
2 × 20 Header
Landing (J4)
Bank 3 (–1200ZE)
Bank 3,4, and 5 (–7000HE)
GPIO
GPIO
USB
Controller
USB MiniB
Socket
1 × 8 Header
Landing (J1,
Optional JTAG
Interface)
A/Mini-B USB
Cable
JTAG
Programming
Figure 7.1. MachXO2 Breakout Board Block Diagram

MachXO2 Breakout Board Evaluation Kit
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© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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FPGA-EB-02051-2.3 13
Table 7.1 describes the components on the board and the interfaces it supports.
Table 7.1. Breakout Board Components and Interfaces
Component/Interface
Type
Schematic Reference
Description
Circuits
USB Controller
Circuit
U2: FT2232H
USB-to-JTAG interface and dual USB UART/FIFO IC
USB Mini-B Socket
I/O
J7:USB_MINI_B
Programming and debug interface
Components
LCMXO2
FPGA
U3: LCMXO2-7000HE-
4TG144C
7000-LUT device packaged in a 20 x 20mm, 144-pin TQFP
Interfaces
LED Array
Output
D8-D1
Red LEDs
Four 2 × 20 Header
Landings
I/O
J2: header_2x20
J3: header_2x20
J4: header_2x20
J5: header_2x20
User-definable I/O
1 × 8 Header Landing
I/O
J1: header_1x8
Optional JTAG interface
4 × 15 60-Hole
Prototype Area
—
—
Prototype area 100mil centered holes.
Test Points
Power
TP1: +3.3 V
TP2: +1.2 V
TP3: GND
Power and ground reference points
7.2. Subsystems
This section describes the principle subsystems for the Breakout Board in alphabetical order.
7.2.1. Clock Sources
All clocks for the counter demonstration designs originate from the MachXO2 on-chip oscillator. You may use an
expansion header landing to drive a FPGA input with an external clock source.
7.2.2. Expansion Header Landings
The expansion header landings provide access to user GPIOs, primary inputs, clocks, and VCCO pins of the MachXO2.
The remaining pins serve as power supplies for external connections. Each landing is configured as one 2 x 20 100 mil.
Table 7.2. Expansion Connector Reference
Item
Description
Reference Designators
J2, J3, J4, J5
Part Number
header_2x20

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14 FPGA-EB-02051-2.3
Table 7.3. Expansion Header Pin Information (J2)
Header Pin Number
-1200ZE Function
-7000HE Function
MachXO2 Pin
1
NC
NC
—
2
VCCIO0
VCCIO0
118, 123, 135
3
PT17D / DONE
PT36D / DONE
109
4
PT17C / INITn
PT36C / INITn
110
5
PT17B
PT36B
111
6
PT17A
PT36A
112
7
GND
GND
—
8
GND
GND
—
9
PT16D
PT33B
113
10
PT16C
PT33A
114
11
PT16B
PT28B
115
12
PT16A
PT28A
117
13
PT15D / PROGn
PT27D / PROGn
119
14
PT15C / JTAGen
PT27C / JTAGen
120
15
GND
GND
—
16
GND
GND
—
17
PT15B
PT25B
121
18
PT15A
PT25A
122
19
PT12D / SDA / PCLKC0_0
PT22D / SDA / PCLKC0_0
125
20
PT12C / SCL / PCLKT0_0
PT22C / SCL / PCLKT0_0
126
21
PT12B / PCLKC0_1
PT18B / PCLKC0_1
127
22
PT12A / PCLKT0_1
PT18A / PCLKT0_1
128
23
GND
GND
—
24
GND
GND
—
25
PT11D / TMS
PT17D / TMS
130
26
PT11C / TCK
PT17C / TCK
131
27
PT11B
PT15B
132
28
PT11A
PT15A
133
29
PT10D / TDI
PT14D / TDI
136
30
PT10C / TDO
PT14C / TDO
137
31
GND
GND
—
32
GND
GND
—
33
PT10B
PT11B
138
34
PT10A
PT11A
139
35
PT9D
PT10B
140
36
PT9C
PT10A
141
37
PT9B
PT9B
142
38
PT9A
PT9A
143
39
GND
GND
—
40
GND
GND
—

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FPGA-EB-02051-2.3 15
Table 7.4. Expansion Header Pin Information (J3)
Header Pin Number
-1200ZE Function
-7000HE Function
MachXO2 Pin
1
VCC_1.2V
VCC_1.2V
36, 72, 108, 144
2
VCCIO1
VCCIO1
79, 88, 102
3
VCC_1.2V
VCC_1.2V
36, 72, 108, 144
4
NC
NC
—
5
PR10C
PR24A
74
6
PR10D
PR24B
73
7
PR10A
PR23A
76
8
PR10B
PR23B
75
9
GND
GND
—
10
GND
GND
—
11
PR9C
PR21A
78
12
PR9D
PR21B
77
13
PR9A
PR18A
82
14
PR9B
PR18B
81
15
GND
GND
—
16
GND
GND
—
17
PR8C
PR17A
84
18
PR8D
PR17B
83
19
PR8A
PR16A
86
20
PR8B
PR16B
85
21
GND
GND
—
22
GND
GND
—
23
PR5C / PCLKT1_0
PR12A / PCLKT1_0
92
24
PR5D / PCLKC1_0
PR12B / PCLKC1_0
91
25
PR5A
PR11A
94
26
PR5B
PR11B
93
27
GND
GND
—
28
GND
GND
—
29
PR4C
PR9A
96
30
PR4D
PR9B
95
31
PR4A
PR7A
98
32
PR4B
PR7B
97
33
GND
GND
—
34
GND
GND
—
35
PR3A
PR5A
100
36
PR3B
PR5B
99
37
PR2C
PR3A
105
38
PR2D
PR3B
104
39
PR2A
PR2A
107
40
PR2B
PR2B
106

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16 FPGA-EB-02051-2.3
Table 7.5. Expansion Header Pin Information (J4)
Header Pin Number
-1200ZE Function
-7000HE Function
MachXO2 Pin
1
VCC_3.3V
VCC_3.3V
—
2
VCCIO3
VCCIO3/4/5
30(VCCIO3), 16(VCCIO4),
7(VCCIO5)
3
VCC_3.3V
VCC_3.3V
—
4
NC
NC
—
5
PL2A / L_GPLLT_FB
PL3A / L_GPLLT_FB
1
6
PL2B / L_GPPLC_FB
PL3B / L_GPPLC_FB
2
7
PL2C / L_GPLLT_IN
PL4A / L_GPLLT_IN
3
8
PL2D / L_GPLLC_IN
PL4B / L_GPLLC_IN
4
9
PL3A / PCLKT3_2
PL6A / PCLKT5_0
5
10
PL3B / PCLKC3_2
PL6B / PCLKC5_0
6
11
PL3C
PL8A
9
12
PL3D
PL8B
10
13
GND
GND
—
14
GND
GND
—
15
PL4A
PL9A
11
16
PL4B
PL9B
12
17
PL4C
PL10A
13
18
PL4D
PL10B
14
19
GND
GND
—
20
GND
GND
—
21
PL5A / PCLKT3_1
PL12A / PCLKT4_0
19
22
PL5B / PCLKC3_1
PL12B / PCLKC4_0
20
23
PL5C
PL15A
21
24
PL5D
PL15B
22
25
GND
GND
—
26
GND
GND
—
27
PL8A
PL17A
23
28
PL8B
PL17B
24
29
PL8C
PL19A
25
30
PL8D
PL19B
26
31
GND
GND
—
32
GND
GND
—
33
PL9A / PCLKT3_0
PL22A / PCLKT3_0
27
34
PL9B / PCLKC3_0
PL22B / PCLKC3_0
28
35
GND
GND
—
36
GND
GND
—
37
PL10A
PL24A
32
38
PL10B
PL24B
33
39
PL10C
PL25A
34
40
PL10D
PL25B
35

MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02051-2.3 17
Expansion Header Pin Information (J5)
Header Pin Number
-1200ZE Function
-7000HE Function
MachXO2 Pin
1
NC
NC
—
2
VCCIO2
VCCIO2
37, 51, 66
3
PB20D / SI / SISPI
PB38B / SI / SISPI
71
4
PB20B
PB37B
69
5
PB20C / SN
PB38A / SN
70
6
PB20A
PB37A
68
7
PB18D
PB35B
67
8
PB18B
PB31B
62
9
PB18C
PB35A
65
10
PB18A
PB31A
61
11
GND
GND
—
12
GND
GND
—
13
PB15D
PB29B
60
14
PB15B
PB26B
58
15
PB15C
PB29A
59
16
PB15A
PB26A
57
17
GND
GND
—
18
GND
GND
—
19
PB11B / PCLKC2_1
PB23B / PCLKC2_1
56
20
PB11D
PB18B
54
21
PB11A / PCLKT2_1
PB23A / PCLKT2_1
55
22
PB11C
PB18A
52
23
GND
GND
—
24
GND
GND
—
25
PB9B / PCLKC2_0
PB16B / PCLKC2_0
50
26
PB9D
PB13B
48
27
PB9A / PCLKT2_0
PB16A / PCLKT2_0
49
28
PB9C
PB13A
47
29
GND
GND
—
30
GND
GND
—
31
PB6D / S0 / SPISO
PB12B / S0 / SPISO
45
32
PB6B
PB9B
43
33
PB6C / MCLK / CCLK
PB12A / MCLK / CCLK
44
34
PB6A
PB9A
42
35
GND
GND
—
36
GND
GND
—
37
PB4D
PB6B
41
38
PB4B
PB4B
39
39
PB4C / CSSPIN
PB6A / CSSPIN
40
40
PB4A
PB4A
38

MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18 FPGA-EB-02051-2.3
NC IO0
109 110
111 112
GND GND
113 114
115 117
119 120
GND GND
121 122
125 126
127 128
GND GND
130 131
132 133
136 137
GND GND
138 139
140 141
142 143
GND GND
1 2
J2
3.3 IO3
3.3 NC
1 2
3 4
5 6
910
GND GND
11 12
13 14
GND GND
19 20
21 22
GND GND
23 24
25 26
GND GND
27 28
GND GND
32 33
34 35
1 2
J4
Top Side
J2 J4
LCM XO 2-7 000 HE4TG144C
Figure 7.2. J3/J4 Header Landing Callout
LCM XO 2-70 00HE4TG144C
1.2 IO1
1.2 NC
74 73
76 75
GND GND
78 77
82 81
GND GND
84 83
86 85
GND GND
92 91
94 93
GND GND
96 95
98 97
GND GND
100 99
105 104
107 106
1 2
J3
NC IO2
71 69
70 68
67 62
65 61
GND GND
60 58
59 57
GND GND
56 54
55 52
GND GND
50 48
49 47
GND GND
45 43
44 42
GND GND
41 39
40 38
1 2
J5
J3 J5
Top Side
Figure 7.3. J3/J5 Header Landing Callout

MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02051-2.3 19
LCM XO2-7000HE4TG144C
D8 LED7
D7 LED6
D6 LED5
D5 LED4
D4 LED3
D3 LED2
D2 LED1
D1 LED0
107
LED Function
LED Array
MachXO2
Pin
106
105
104
100
99
98
97
Top Side
D8
D1
J1
3.3
TDO
TDI
NC
NC
TMS
GND
TCK
1
8
J1
Figure 7.4. J1 Header Landing and LED Array Callout
7.2.3. MachXO2 FPGA
The MachXO2-7000HE-4TG144C is a 144-pin TQFP package FPGA device which provides up to 114 usable I/O in a 20
mm × 20 mm package. 108 I/O are accessible from the breakout board headers.
Table 7.6. MachXO2 and MachXO3 FPGA Interface Reference
Item
Description
Reference Designators
U3
Part Number
LCMXO2-7000HE-4TG144C
Manufacturer
Lattice Semiconductor
Web Site
www.latticesemi.com
7.2.4. JTAG Interface Circuits
For power and programming an FTDI USB UART/FIFO IC converter provides a communication interface between a PC host and
the JTAGprogramming chain of the Breakout Board. The USB 5V supply is also used as a source for the 3.3 V supply rail. A USB
mini-B socket is provided for the USB connector cable.
Table 7.7. JTAG Interface Reference
Item
Description
Reference Designators
U1
Part Number
FT2232HL
Manufacturer
Future Technology Devices International (FTDI)
Web Site
www.ftdichip.com

MachXO2 Breakout Board Evaluation Kit
Evaluation Board User Guide
© 2014-2022Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20 FPGA-EB-02051-2.3
Table 7.8. JTAG Programming Pin Informationz
Description
MachXO2 Pin
Test Data Output
137:TDO
Test Data Input
136:TDI
Test Mode Select
130:TMS
Test Clock
131:TCK
Table 7.9. LEDs
A green LED (D9) is used to indicate USB 5V power. Eight red LEDs are driven by I/O pins of the MachXO2 device.
Table 7.10. Power and User LEDs Reference
Item
Description
Reference Designators
Red LEDs (D1, D2, D3, D4, D5, D6, D7, D8)
Green LEDs (D9)
Part Number
LTST-C190KRKT (D1-D8)
LTST-C190KGKT (D9)
Manufacturer
Lite-On It Corporation
Web Site
www.liteonit.com
7.2.5. Power Supply
3.3 V and 1.2 V power supply rails are converted from the USB 5 V interface when the board is connected to a host
PC.
7.2.6. Test Points
In order to check the various voltage levels used, the following test points are provided:
•TP1: +3.3 V
•TP2: +1.2 V
•TP3: GND
7.2.7. USB Programming and Debug Interface
The USB mini-B socket of the Breakout Board serves as the programming and debug interface.
JTAG Programming: For JTAG programming, a preprogrammed USB PHY peripheral controller is provided on the
Breakout Board to serve as the programming interface to the MachXO2 FPGA.
Programming requires the Lattice Diamond or ispVM System software.
Table 7.11. USB Interface Reference
Item
Description
Reference Designators
U1
Part Number
FT2232HL
Manufacturer
Future Technology Devices International (FTDI)
Web Site
www.ftdichip.com