Lattice Semiconductor MachXO2 Series User manual

MachXO2 and MachXO3 Starter Kit
Evaluation Board User Guide
FPGA-EB-02036-1.4
January 2022

MachXO2 and MachXO3 Starter Kit Evaluation Board User Guide
Evaluation Board User Guide
© 2014-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02036-1.4
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS, with all faults and associated risk the responsibility entirely of the Buyer.
Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have been subject to limited
testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the same. No Lattice
products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s product could create a
situation where personal injury, death, severe property or environmental damage may occur. The information provided in this document is
proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any products at
any time without notice.

MachXO2 and MachXO3 Starter Kit Evaluation Board User Guide
Evaluation Board User Guide
© 2014-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02036-1.4 3
Contents
Acronyms in This Document.................................................................................................................................................5
1. Introduction..................................................................................................................................................................6
2. Features........................................................................................................................................................................7
3. Storage Handling ..........................................................................................................................................................9
4. Software Requirements..............................................................................................................................................10
5. MachXO2 and MachXO3 Devices ...............................................................................................................................11
6. Demonstration Design................................................................................................................................................12
Overview ...........................................................................................................................................................12
Run the Demonstration Design.........................................................................................................................13
Download Demo Designs ..................................................................................................................................15
Programming a Demo Design with the Lattice Diamond Programmer.............................................................15
7. MachXO2 and MachXO3 Starter Kits..........................................................................................................................17
Subsystems........................................................................................................................................................17
Clock Sources................................................................................................................................................17
Expansion Header Landings..........................................................................................................................17
MachXO2/MachXO3 FPGA ...........................................................................................................................23
Programming Interface Circuits....................................................................................................................23
LEDs...............................................................................................................................................................24
Power Supply................................................................................................................................................24
Test Points ....................................................................................................................................................24
USB Programming and Debug Interface.......................................................................................................24
Board Modifications..........................................................................................................................................25
Bypassing the USB Programming Interface ..................................................................................................25
Applying External Power...............................................................................................................................25
Measuring Bank and Core Power .................................................................................................................25
Mechanical Specifications.................................................................................................................................25
Environmental Requirements ...........................................................................................................................25
8. Troubleshooting .........................................................................................................................................................26
LEDs Do Not Flash..............................................................................................................................................26
USB Cable Not Detected....................................................................................................................................26
Accessing the Troubleshooting the USB Driver Installation Guide ...................................................................26
Restoring Original Demo Design .......................................................................................................................26
9. Ordering Information .................................................................................................................................................27
Technical Support Assistance .............................................................................................................................................28
Appendix A. Schematic Diagrams.......................................................................................................................................29
Appendix B. Bill of Materials...............................................................................................................................................37
RevisionHistory...................................................................................................................................................................39

MachXO2 and MachXO3 Starter Kit Evaluation Board User Guide
Evaluation Board User Guide
© 2014-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02036-1.4
Figures
Figure 2.1. MachXO3 Board (MachXO3L Version), Top Side ................................................................................................7
Figure 2.2. MachXO3 Board (MachXO3L Version), Bottom Side ..........................................................................................8
Figure 7.1. MachXO2 and MachXO3L/LF-6900C Block Diagram.........................................................................................12
Figure 6.1. Demonstration Design Block Diagram ..............................................................................................................13
Figure 7.2. J3/J4 Header Landing Callout............................................................................................................................22
Figure 7.3. J6/J8 Header Landing Callout............................................................................................................................22
Figure 7.4. J1 Header Landing and LED Array Callout.........................................................................................................23
Figure A.1. Block Diagram...................................................................................................................................................29
Figure A.2. USB Interface to JTAG.......................................................................................................................................30
Figure A.3. FPGA .................................................................................................................................................................31
Figure A.4. FPGA .................................................................................................................................................................32
Figure A.5. Power LEDs .......................................................................................................................................................33
Figure A.6. Bank 2 I/O.........................................................................................................................................................34
Figure A.7. Bank 3, 4, 5 I/O .................................................................................................................................................35
Figure A.8. Power Decoupling and LEDs .............................................................................................................................36
Tables
Table 7.1. Starter Kit Components and Interfaces..............................................................................................................13
Table 6.1. DIP Switch and LED Behavior .............................................................................................................................14
Table 7.2. Expansion Connector Reference........................................................................................................................17
Table 7.3. Expansion Header Pin Information (J3)..............................................................................................................18
Table 7.4. Expansion Header Pin Information (J4)..............................................................................................................19
Table 7.5. Expansion Header Pin Information (J6)..............................................................................................................20
Table 7.6. Expansion Header Pin Information (J8)..............................................................................................................21
Table 7.7. MachXO2 and MachXO3 FPGA Interface Reference..........................................................................................23
Table 7.8. USB/JTAG Interface Reference...........................................................................................................................23
Table 7.9. JTAG Programming Pin Information...................................................................................................................24
Table 7.10. SPI Programming Pin Information....................................................................................................................24
Table 7.11. I2C Programming Pin Information ....................................................................................................................24
Table 7.12. Power and User LEDs Reference......................................................................................................................24
Table 7.13. USB Interface Reference ..................................................................................................................................25
Table 9.1. Ordering Information.........................................................................................................................................27

MachXO2 and MachXO3 Starter Kit Evaluation Board User Guide
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© 2014-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02036-1.4 5
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
DIP
Dual In-line Package
FPGA
Field-Programmable Gate Array
LED
Light Emitting Diode
LUT
Look-Up Table
NVCM
Non Volatile Configuration Memory
PCB
Printed Circuit Board
RoHS
Restriction of Hazardous Substances Directive
USB
Universal Serial Bus
WDT
Watchdog Timer

MachXO2 and MachXO3 Starter Kit Evaluation Board User Guide
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© 2014-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02036-1.4
1. Introduction
This user guide describes how to start using the MachXO2 and MachXO3 Starter Kits, an easy-to-use platform for
evaluating and designing with the Mach XO2 and MachXO3 ultra-low-density FPGA. Along with the board and
accessories, this kit includes a pre-loaded demonstration design. You may also reprogram the on-board MachXO2 and
MachXO3 device to review your own custom designs.
The MachXO2 Start Kit currently features the LCMXO2-4000ZE (Flash Based) device in the 256-ball 0.8 mm pitch caBGA
package. The MachXO3 Starter Kit currently features the MachXO3L-6900C (NVCM Based) or the MachXO3LF-6900C
(Flash Based) device in the 256-ball 0.8 mm pitch caBGA package. The kits also include a Serial Flash Memory for
demonstrating external SPI boot-up. The external Flash Memory also supports a dual-boot mode in addition to Golden
boot/fail-safe boot options.
See the Ordering Information section for more information.
Note: Static electricity can severely shorten the lifespan of electronic components. See the Storage Handling section of
this document for handling and storage tips.

MachXO2 and MachXO3 Starter Kit Evaluation Board User Guide
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02036-1.4 7
2. Features
The MachXO2 and MachXO3 Starter Kits include:
•Mach XO2/MachXO3L/MachXO3LF Board –The board is a 3” x 3” form factor that features the following on-
board components and circuits:
•One of the following FPGAs
•LCMXO2-4000ZE-1BG256C (Flash Based)
•LCMXO3L-6900C-5BG256C (NVCM Based)
•LCMXO3LF-6900C-5BG256C (Flash Based)
•USB mini-B connector for power and programming
•4-Mb Serial Flash Memory for boot image and dual-boot support.
•Eight LEDs
•4-position DIP switch
•Momentary push button switch
•40-hole prototype area
•Four 2 x 20 expansion header landings for general I/O, JTAG, and external power
•1 x 8 expansion header landing for JTAG
•1 x 6 expansion header landing for SPI/I2C
•3.3 V and 1.2 V supply rails
•Pre-loaded Demo –The kit includes a pre-loaded counter design that highlights use of the embedded
MachXO2 and MachXO3 oscillators and programmable I/O configured for LED drive.
•USB Connector Cable –The board is powered from the USB mini-B socket when connected to a host PC. The
USB channel also provides a programming interface to the MachXO2 and MachXO3 JTAG ports.
•Lattice Development Kits and Boards Web Page –Visit www.latticesemi.com/breakoutboards for the latest
documentation (including this guide) and drivers for the kit.
The content of this user guide includes demo operation, programming instructions, top-level functional descriptions of
the Starter Kit, descriptions of the on-board connectors, and a complete set of schematics.
Two 2 x 20 Header
Landings (J3, J4)
Two 2 x 20 Header
Landings (J6, J8)
JTAG Header
Landing (J1)
SPI/I2C Header
Landing (J7)
MachXO3L PLD
(U5)
USB Mini -B
Socket (J2)
Power LED,
Blue (D1)
FTDI USB to
UART/FIFO IC (U1)
Push Button
Switch (SW1)
4-Position DIP
Switch (SW2)
4 x 10 40-Hole
Prototype array
LED array
(D9 -D2)
Figure 2.1. MachXO3 Board (MachXO3L Version), Top Side

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© 2014-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
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8 FPGA-EB-02036-1.4
SPI Flash Boot
Memory (U6)
Figure 2.2. MachXO3 Board (MachXO3L Version), Bottom Side

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FPGA-EB-02036-1.4 9
3. Storage Handling
Static electricity can shorten the lifespan of electronic components. Observe these tips to prevent damage that could
occur from electro-static discharge:
•Use anti-static precautions such as operating on an anti-static mat and wearing an anti-static wrist-band.
•Store the evaluation board in the packaging provided.
•Touch a metal USB housing to equalize voltage potential between you and the board.

MachXO2 and MachXO3 Starter Kit Evaluation Board User Guide
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© 2014-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-EB-02036-1.4
4. Software Requirements
You should install the following software before you begin developing designs for the Starter Kit:
•Lattice Diamond® design software
•FTDI Chip USB hardware drivers (installed as an option within the Diamond installation program)

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© 2014-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02036-1.4 11
5. MachXO2 and MachXO3 Devices
This board currently features the MachXO3L-6900C FPGA which offers embedded Non-Volatile Configuration Memory
(NVCM) technology, the MachXO3LF-6900C FPGA which offers embedded Non-Volatile Flash technology for instant-on
operation in a single chip, or MachXO2-4000ZE FPGA which also offers embedded Non-Volatile Flash technology for
instant-on operation in a single chip. Numerous system functions are included, such as two PLLs and 256 kbits of
embedded RAM plus hardened implementations of I2C and SPI. Flexible, high performance I/O support numerous
single-ended and differential standards including LVDS. The 256-ball BGA package provides up to 206 user I/O in a 14
mm x 14 mm form factor. A complete description of these devices can be found in the MachXO2 Family Data Sheet
(FPGA-DS-02056) or the MachXO3 Family Data Sheet (FPGA-DS-02032).

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© 2014-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-EB-02036-1.4
6. Demonstration Design
Lattice provides a simple, pre-programmed demo to illustrate basic operation of the MachXO2 and MachXO3 devices.
The design integrates an up-counter with the on-chip oscillator. For the XO3L Starter Kit, pre-programmed design
resides in the external Serial Flash Memory (SPANSION S25FL204K or S25FL208K, or ON Semiconductor LE25U40CMD).
For the XO2 and XO3LF Starter Kits, the pre-programmed design resides in the on-board configuration flash memory.
Note: To restore the factory default demo and program it with other Lattice-supplied examples see the Download
Demo Designs section.
Overview
The Starter Kit is a complete development platform for the MachXO2 and MachXO3 FPGAs. The board includes a
prototyping area, a USB program/power port, an LED array, switches, and header landings with electrical connections
to most of the FPGA’s programmable I/O, power, and configuration pins. The board is powered by the PC’s USB port or
optionally with external power. You may create or modify the program files and reprogram the board using Lattice
Diamond software.
MachXO3L/LF-6900C device
2 x 20 Header
Landing (J6)
LED
Array
GPIO
8
2 x 20 Header
Landing (J3)
GPIO 2 x 20 Header
Landing (J4)
Bank 1
Bank 2
Bank 0
Landing (J8)
Bank 3, 4 and 5
GPIO
GPIO
USB
Controller
USBMini B
Socket
1 x 8 Header
Landing (J1,
Optional JTAG
Interface)
JTAG
Programming
1 x 6 Header
Landing (J7,
Optional SPI,
I2C Intrfaces)
Bank 0, 2
DIP_SW 4
Figure 6.1. MachXO2 and MachXO3L/LF-6900C Block Diagram

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FPGA-EB-02036-1.4 13
Table 6.1 describes the components on the board and the interfaces it supports.
Table 6.1. Starter Kit Components and Interfaces
Component/Interface
Type
Schematic
Reference
Description
Circuits
USB Controller
Circuit
U1: FT2232H
USB-to-JTAG interface and dual USB UART/FIFO IC
USB Mini-B Socket
I/O
J2:USB_MINI_B
Programming and debug interface
Components
LCMXO2, LCMXO3L, or
LCMXO3LF
FPGA
U5: LCMXO2-
4000ZE-1BG256C,
LCMXO3L-6900C-
5BG256C or
LCMXO3LF-
6900C-5BG256C
4000-LUT and 6900-LUT devices are in a 14 mm x 14 mm,
256-ball caBGA package.
Interfaces
LED Array
Output
D9-D2
Red LEDs
Push Button Switch
Input
SW1
Momentary User Input
4-position DIP Switch
Input
SW2
User inputs
Four 2 x 20 Header
Landings
I/O
J3: header_2x20
J4: header_2x20
J6: header_2x20
J8: header_2x20
User-definable I/O
1 x 8 Header Landing
I/O
J1: header_1x8
Optional JTAG interface
1 x 6 Header Landing
I/O
J7: header_1x6
Optional SPI/I2C interfaces
4 x 10 40-Hole Prototype
Area
—
—
Prototype area 100 mil centered holes.
Test Points
Power
TP1: +3.3 V TP2:
+1.2 V TP3: GND
Power and ground reference points
Run the Demonstration Design
Upon power-up, the pre-programmed demonstration design automatically loads and drives the LED array in a 1-hertz
pattern. The program shows a clock divider driven either by the MachXO2/MachXO3 internal oscillator or the external
FTDI clock chip. The divider modules (heartbeat.v and kitcar.v) are clocked at the default frequency of 12 MHz which
divides the clock to cycle the LED display approximately once per second. The resulting light pattern is determined by
the DIP Switch (SW2) setting as shown in Table 6.2.
MachXO3
X1
12.0 M Hz
OSCH
12.09 MHz Kitcar .v
Heartbe at.v
SW2
4-Position DIPSW
1 x 8
LED
Array
XO3 L_SK_b li nk.v
SW1
Momentary PB Async Reset
Figure 6.2. Demonstration Design Block Diagram

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14 FPGA-EB-02036-1.4
Table 6.2. DIP Switch and LED Behavior
Switch
Setting
LED Behavior
DIP_SW[1]
0 (Down)
External 12.0 MHz (X1)
1 (Up)
Internal 12.09 MHz (OSCH)
DIP_SW[2:4]
001
1 Hz Sweep
011
1 Hz Left-Right
111
1 Hz Blink
Others
1 Hz Alternating
WARNING: Do not connect the board to your PC before you follow the driver installation procedure of this section.
Communication between the board and a PC, through the USB connection cable, requires installation of the FTDI chip
USB hardware drivers. Loading these drivers enables the computer to recognize and program the board. Drivers can be
loaded as part of the installation of Lattice Diamond design software or Diamond Programmer, or as a stand-alone
package.

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FPGA-EB-02036-1.4 15
To load the FTDI Chip USB hardware drivers as part of the Lattice Diamond installation:
1. Select Programmer Drivers in the Product Options of Lattice Diamond Setup.
2. Select FTDI Windows USB Driver or All Drivers in the LSC Drivers Install/Uninstall dialog box.
3. Click Finish to install the USB driver.
4. After the driver installation is complete, connect the USB cable from a USB port on your PC to the board’s USB
mini-B socket (J2). After the connection is made, a blue Power LED (D1) lights indicating the board is powered
on.
5. The demonstration design automatically loads and drive the LED array in a repeating pattern.
To load the FTDI chip USB hardware drivers via the stand-alone package on a Windows system:
1. Download the FTDI Chip USB Hardware Drivers package from the Lattice website.
2. Extract the FTDI chip USB Hardware driver package to your PC hard drive.
3. Connect the USB cable from a USB port on your PC to the board’s USB mini-B socket (J2). After the connection
is made, a blue Power LED (D1) lights indicating the board is powered on.
4. If you are prompted, Windows may connect to Windows Update select No, not this time from available
options and click Next to proceed with the installation. Choose the Install from specific location (Advanced)
option and click Next.
5. Search for the best driver in these locations and click the Browse button to browse to the Windows driver
folder created in the Download Windows USB Hardware Drivers section. Select the CDM 2.04.06 WHQL
Certified folder and click OK.
6. Click Next. A screen displays as Windows copies the required driver files. Windows display a message
indicating that the installation was successful.
7. Click Finish to install the USB driver.
8. The demonstration design automatically loads and drive the LED array in a repeating pattern.
See the Troubleshooting section of this guide if the board does not function as expected.
Download Demo Designs
The counter demo is preprogrammed into the board, however over time it is likely your board is modified. Lattice
distributes source and programming files for demonstration designs compatible with the Starter Kit. The demo design
for the board is available on the web.
To download demo designs:
1. In the Lattice website, browse to Development Kits and Boards. Go to the MachXO3L Starter Kit, the
MachXO3LF Starter Kit, or the MachXO2ZE Breakout Board web page. In the Documentation section, select the
Design File tab. Select MachXO3L Starter Kit Demo Program, the MachXO3LF Starter Kit Demo Program, or
the MachXO2 Starter Kit Demo Program and save the file.
2. Extract the contents of MachXO3L_Starter_Kit.zip, the MachXO3LF_Starter_Kit.zip, or the
MachXO2_Starter_Kit.zip to an accessible location on your hard drive.
3. Open the Blink.ldf project file in the Lattice Diamond design software.
4. Run the Process Flow and regenerate the Bitstream file.
Continue to Programming a Demo Design with the Lattice Diamond Programmer.
Programming a Demo Design with the Lattice Diamond Programmer
The demonstration design is pre-programmed into the MachXO2/MachXO3 board by Lattice. If you have changed the
design but now want to restore the board to factory settings, use the procedure described below.
To program the MachXO2/MachXO3 device:
1. Install, license and run Lattice Diamond software. See http://www.latticesemi.com/latticediamond for
download and licensing information.

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16 FPGA-EB-02036-1.4
2. Connect the USB cable to the host PC and the MachXO3 board.
3. From Diamond, open the Blink.ldf project file.
4. Click the Programmer icon.
5. Click Detect Cable. The Programmer detects the cable (Cable: USB2, Port: FTUSB-0). If the cable is not
detected, see the Troubleshooting section.
6. Click Device Properties.
Internal Flash Programming (MachXO2 and MachXO3LF):
1. Change Access Mode to Flash Programming Mode.
2. Choose FLASH Erase, Program, Verify operation.
3. Select Blink_impl1.jed programming file. Click OK.
4. Click the Program icon. When complete, PASS is displayed in the Status column.
SPI Flash Programming (MachXO3L):
1. Change Access Mode to SPI Flash Programming.
2. Choose SPI Flash Background Erase, Program, Verify operation.
3. Select the Blink_impl1.bit programming file.
4. Under SPI Flash Options, change Vendor to SPANSION or ON Semi (as appropriate), and change Device to SPI-
S25FL204K or S25FL208K or LE25U40CMDTWG (as appropriate). Click OK.
5. Click the Program icon. When complete, PASS is displayed in the Status column.
6. Change Access mode to NVCM Programming Mode and NVCM Refresh, then click Program (or power-cycle
the Starter Kit board) to initiate a re-boot from the SPI flash.

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FPGA-EB-02036-1.4 17
7. MachXO2 and MachXO3 Starter Kits
This section describes the features of the MachXO2 and MachXO3 Starter Kits in detail.
Subsystems
This section describes the principal subsystems for the Starter Kit in alphabetical order.
Clock Sources
Clock sources for the LED demonstration designs originate from the MachXO2/MachXO3 on-chip oscillator or the 12
MHz crystal X1. You may use an expansion header landing to drive a FPGA input with an external clock source.
Expansion Header Landings
The expansion header landings provide access to user GPIOs, primary inputs, clocks, and VCCO pins of the
MachXO2/MachXO3 device. The remaining pins serve as power supplies for external connections. Each landing is
configured as one 2 x 20 100 mil.
Table 7.1. Expansion Connector Reference
Item
Description
Reference Designators
J3, J4, J6, J8
Part Number
header_2x20

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18 FPGA-EB-02036-1.4
Table 7.2. Expansion Header Pin Information (J3)
Header Pin Number
-4000 Function
-6900C Function
MachXO2/MachXO3 Ball
1
VCCIO0
VCCIO0
D5,D12,G8,G9
2
VCCIO0
VCCIO0
D5,D12,G8,G9
3
PT28C/INITn
PT36C/INITn
A13
4
PT28D/DONE
PT36D/DONE
C13
5
PT20A
PT22A
F8
6
PT27B
PT35B
B12
7
PT27A
PT35A
C12
8
PT22B
PT26B
E11
9
PT23B
PT27B
E10
10
PT23A
PT27A
D10
11
GND
GND
—
12
GND
GND
—
13
PT22A
PT26A
F9
14
PT23C/JTAGENB
PT27C/JTAGENB
C10
15
PT15B
PT17B
E8
16
PT19B
PT21B
E9
17
PT13B
PT14B
E7
18
PT19A
PT21A
D8
19
PT14D
PT16B
D7
20
PT14B
PT15B
C7
21
GND
GND
—
22
GND
GND
—
23
PT10B
PT10B
C5
24
PT13A
PT14A
D6
25
PT14C
PT16A
E6
26
PT9A
PT9A
C4
27
PT21B
PT25B
A10
28
PT15A
PT17A
F7
29
PT20B
PT22B
D9
30
PT21A
PT25A
B9
31
GND
GND
—
32
GND
GND
—
33
PT11B
PT11B
B6
34
PT14A
PT15A
B7
35
PT9B
PT9B
B5
36
PT11A
PT11A
A5
37
PT12B
PT12B
B4
38
PT10A
PT10A
A4
39
GND
GND
—
40
PT12A
PT12A
A3

MachXO2 and MachXO3 Starter Kit Evaluation Board User Guide
Evaluation Board User Guide
© 2014-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02036-1.4 19
Table 7.3. Expansion Header Pin Information (J4)
Header Pin Number
-4000 Function
-6900C Function
MachXO2/MachXO3 Ball
1
VCCIO1
VCCIO1
E13,H10,J10,M13
2
VCCIO1
VCCIO1
E13,H10,J10,M13
3
PR15D
PR19D
K12
4
PR15C
PR19C
K13
5
PR18A
PR23A
M14
6
PR19B
PR24B
N14
7
PR15B
PR18B
L14
8
PR19A
PR24A
N16
9
PR18B
PR23B
M15
10
PR16B
PR21B
M16
11
GND
GND
—
12
GND
GND
—
13
PR16A
PR21A
L15
14
PR15A
PR18A
L16
15
PR14A
PR17A
K14
16
PR13B
PR16B
K16
17
PR14B
PR17B
K15
18
PR10D
PR15B
J14
19
PR10A/PCLKT1_0
PR12A/PCLKT1_0
H14
20
PR13A
PR16A
J15
21
GND
GND
—
22
GND
GND
—
23
PR10C
PR15A
J16
24
PR9B
PR11B
H15
25
PR10B/PCLKC1_0
PR12B/PCLKC1_0
H16
26
PR8A
PR9A
G15
27
PR9A
PR11A
G16
28
PR5B
PR5B
F15
29
PR6B
PR7B
F16
30
PR2B
PR2B/R_GPLLC_FB
E15
31
GND
GND
—
32
GND
GND
—
33
PR5A
PR5A
E16
34
PR3B/R_GPLLC_IN
PR3B/R_GPLLC_IN
E14
35
PR3A/R_GPLLT_IN
PR3A/R_GPLLT_IN
D16
36
PR2C
PR2C
C15
37
PR2A/R_GPLLT_FB
PR2A/R_GPLLT_FB
D14
38
PR6A
PR7A
F14
39
PR8B
PR9B
G14
40
PR2D
PR2D
B16

MachXO2 and MachXO3 Starter Kit Evaluation Board User Guide
Evaluation Board User Guide
© 2014-2022 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20 FPGA-EB-02036-1.4
Table 7.4. Expansion Header Pin Information (J6)
Header Pin Number
-4000 Function
-6900C Function
MachXO2/MachXO3 Ball
1
VCCIO2
VCCIO2
K8,K9,N5,N12
2
VCCIO2
VCCIO2
K8,K9,N5,N12
3
PB27B
PB35B
T12
4
PB26B
PB34B
T14
5
PB27A
PB35A
R11
6
PB26A
PB34A
R13
7
PB24A
PB31A
T11
8
PB23D
PB28B
M11
9
PB24B
PB31B
P11
10
PB23C
PB28A
N10
11
GND
GND
—
12
GND
GND
—
13
PB21B
PB26B
T10
14
PB23A
PB29A
P10
15
PB21A
PB26A
R9
16
PB23B
PB29B
R10
17
PB20A
PB23A/PCLKT2_1
T9
18
PB18B
PB21B
N9
19
PB20B/PCLKC2_1
PB23B/PCLKC2_1
P9
20
PB18A
PB21A
M8
21
GND
GND
—
22
GND
GND
—
23
PB15B
PB18B
T8
24
PB12B
PB15B
L8
25
PB15A
PB18A
P8
26
PB12A
PB15A
M6
27
PB10A
PB13A
R7
28
PB13B/PCLKC2_0
PB16B/PCLKC2_0
R8
29
PB10B
PB13B
P7
30
PB13A/PCLKT2_0
PB16A/PCLKT2_0
T7
31
GND
GND
—
32
GND
GND
—
33
PB9D
PB10B
L7
34
PB7B
PB9B
R6
35
PB9C
PB10A
N6
36
PB7A
PB9A
T5
37
PB6B
PB7B
R4
38
PB3A
PB4A
P4
39
PB6A
PB7A
T3
40
PB3B
PB4B
T4