Lattice Semiconductor LFSC80E-P4-EV User manual

September 2009
Revision: EB31_01.2
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LatticeSC PCI Express x4 Evaluation Board
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User’s Guide

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LatticeSC PCI Express x4 Evaluation Board
Lattice Semiconductor User’s Guide
Introduction
This user’s guide describes the LatticeSC PCI Express x4 Evaluation Board featuring the LatticeSC
LFSCM3GA80EP1-6FC1152C FPGA device. This stand-alone evaluation PCB provides a functional platform for
development and rapid prototyping of applications that require high-speed SERDES interfaces and/or PCI Express
protocols.
The evaluation board includes provisioning to connect high-speed SERDES channels via SMA connectors to test
and measurement equipment. The board is manufactured using standard FR4 dielectric and through-hole vias.
The nominal impedance is 50-ohm for single-ended traces and 100-ohm for differential traces.
The board has several debugging and analyzing features for complete user evaluation of the LatticeSC device. This
user’s guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the Lattic-
eSC FPGA.
Figure 1. LatticeSC PCI Express x4 Evaluation Board
DDR2
SDRAM
LVDS I/O PCI Express x4
Edge
Mictor Connector
for Logic Analyzer
LatticeSC-80
1152 fpBGA
Power
Supplies
PCI Express
Cable Connectors
SERDES I/O Test LEDs Clock I/O
Features
• LatticeSCM-80 device in 1152 fcBGA package
• SERDES interface to x4 PCI Express edge fingers
• Two x1 PCI Express cable connections
• DDR2 memory device
• SERDES high-speed interface SMA test points and clock connections
• Power connections and power sources
•ispVM
®programming support

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Lattice Semiconductor User’s Guide
• On-board and external reference clock sources
• Interchangeable clock oscillators
• ORCAstra demonstration software interface via standard ispVM JTAG connection
• Various high-speed layout structures
• User-defined input and output points
• SMA connectors included (10) for high-speed clock or data interfacing
• Performance monitoring via test headers, LEDs and switches
This user’s guide includes top-level functional descriptions of the various portions of the evaluation board, descrip-
tions of the on-board connectors, diodes and switches and a complete set of schematics of the board. Figure 2
shows the functional partitioning of the board.
Additional Resources
For additional information and resources related to this board, including updated documentation and hard-
ware/software demos, please see the Lattice web site at www.latticesemi.com/boards and navigate to the appropri-
ate page for this board.
A PCI Express demonstration is also available on-line, including a GUI and drivers for a PCI Express solution using
this board.
Lattice makes its best effort to provide evaluation board designs to help users with evaluation and development.
However it remains the user's responsibility to verify proper and reliable operation of Lattice products in their end
application by consulting documentation provided by Lattice. Differences in component selection and/or PCB layout
in the user's application may significantly affect circuit performance and reliability.
Figure 2. Evaluation Board Block Diagram
LatticeSC
1152 fcBGA
LVDS SMAs
4-bit
Input/Output
DDR2
Memory
84 fBGA
PCI Express x4
PCI Express Card
Edge Fingers
LVDS
Bus Loop
PCI Express x1
Cable Connector
PCI Express x1
Cable Connector
LatticeSC Device
This board features a LatticeSC FPGA with a 1.2V core supply. It can accommodate all pin compatible LatticeSC
devices in the 1152-ball fpBGA (1mm pitch) package. A complete description of this device can be found in the Lat-
ticeSC/M Family Data Sheet.

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Note: The connections referenced in this document refer to the LFSCM3GA80 device. Available I/Os and associ-
ated sysIO™ banks may differ for other densities within this device family.
Applying Power to the Board
The LatticeSC PCI Express x4 Evaluation Board is ready to power on. The evaluation board can be supplied with
power from an AC wall-type transformer power supply shipped with the board. Or it can be supplied from a bench-
top supply via terminal screw connections. It also has provisions to be supplied from the PCI Express edge fingers
from a host board.
To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cord
to J3 and plug the wall transformer into an AC wall outlet.
Power Supplies
(see Appendix A, Figure 9)
The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to
accept a main supply via the TB1 connection. This connection is provided to use with a bench-top supply adjusted
to provide a nominal 12V DC.
All input power sources and on-board power supplies are fused with surface mounted fuses and have green LEDs
to indicate power GOOD status of the intermediate supplies
Table 1. Board Power Supply Fuses- (see Appendix A, Figure 9)
F1 1.0V/1.2V Fuse
F2 3.3V Fuse
F3 1.5V Fuse
F4 1.2V Fuse
F5 2.5V Fuse
F6 1.8V Fuse
Table 2. Board Power Supply Indicators- (see Appendix A, Figure 9)
D14 1.0V/1.2V VCC Core Source Good Indicator
D15 1.5V Source Good Indicator
D16 1.8V Source Good Indicator
D12 2.5V Source Good Indicator
D13 3.3V Source Good Indicator
D17 1.2V Source Good Indicator
Alternatively, external power can be connected rather than the wall transformer power pack.
Table 3. Board Supply Disconnects- (see Appendix A, Figure 9)
TB1 Screw terminal for 12V DC Pin1(square PCB pad) -> +12V DC Pin2 -> Ground
PCI Express Power Interface
(see Appendix A, Figure 10)
Power can be sourced to the board via the PCB Edge Finger (CN1). This interface allows the user to provide power
from a PCI Express host board.

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Programming/FPGA Configuration
(see Appendix A, Figure 7)
A programming header is provided on the evaluation board, providing access to the LatticeSC JTAG port.
Note: An ispDOWNLOAD®Cable is included with each ispLEVER®design tool shipment. Cables may also be pur-
chased separately from Lattice.
ispVM Download Interface
J2 is a10-pin JTAG connector used in conjunction with the ispVM System software and ispDOWNLOAD Cable to
program and control the device.
Table 4. JTAG Programming Connector (see Appendix A, Figure 7)
Pin 1 VCC
Pin 2 TDO
Pin 3 TDI
Pin 4 PROGRAMN
Pin 5 NC
Pin 6 TMS
Pin 7 GND
Pin 8 TCK
Pin 9 DONE
Pin 10 INITN
Programming Daisy Chain
This board includes two Lattice programmable devices that can be programmed in a daisy chain. A jumper setting
of J93 controls the chain. Both devices are in the programming chain from the JTAG header J2 with jumpers across
Pins{1-2} and Pins{3-4}. If the user desires to only program U1, only a jumper should be across Pins{2-4}.
Download Procedures
Requirements
• PC with ispVM System v.14.3 (or later) programming management software, installed with appropriate drivers
(USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable). Note: An option
to install these drivers is included as part of the ispVM System set-up.
• ispDOWNLOAD Cable (HW-USBN-2A, HW-DLN-3C, etc.)
JTAG Download
The LatticeSC device can be configured easily via its JTAG port. The device is SRAM-based; it must remain pow-
ered on to retain its configuration when programmed in this fashion.
1. Connect the ispDOWNLOAD cable to the appropriate header. J2 is used for the 1x10 cable.
Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the isp-
DOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any
other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeSC FPGA device and
render the board inoperable.
2. Connect the LatticeSC Evaluation Board to the appropriate power sources and power up the board.
3. Start the ispVM System software.

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4. Press the SCAN button located in the toolbar. The LatticeSC device should be automatically detected.
Figure 3. ispVM Main Window
5. Double-click the device to open the device information dialog. In the device information dialog, click the Browse
button located under Data File. Locate the desired bitstream file (.bit). Click OK to both dialog boxes.

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Lattice Semiconductor User’s Guide
Figure 4. Device Information Dialog Box
6. Click the green GO button. This will begin the download process into the device. Upon successful download, the
device will be operational.
Configuration Status Indicators
(see Appendix A, Figure 7)
These LEDs indicate the status of configuration to the FPGA.
• D1 illuminated (red) – This indicates that the programming was aborted or reinitialized driving the INITN output
low.
• D4 illuminated (green) – This indicates the successful completion of configuration by releasing the open collector
DONE output pin.
• D11 illuminated (green) – Flashes to indicate TDI activity.
• D21 illuminated (red) – This indicates that PROGRAMN is low.
• D23 illuminated (red) – This indicates that GSRN is low.
PROGRAMN & RESETN
(see Appendix A, Figure 7)
These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW5) and RESETN (SW4).
Depressing the button drives a logic level “0” to the device.

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Lattice Semiconductor User’s Guide
MODE [3:0]
(see Appendix A, Figure 7)
The FPGA MODE pins are set on the board for a particular programming mode via the SW6 DIP switch. JTAG pro-
gramming is independent of the MODE pins and is always available to the user. Pushing in (depressing) the switch
is ON and sets the value to 0.
LatticeSC devices support many configuration modes. Listed below are the configuration modes supported on this
board. The modes are either directly supported or emulated using the CPLD on board.
Table 5. Configuration Mode Selections
MODE3 SW6-4 MODE2 SW6-3 MODE1 SW6-2 MODE0 SW6-1 Configuration Mode
0 (ON) 1 (OFF) 0 (ON) 1 (OFF) SPI Flash
1 (OFF) 0 (ON) 0 (ON) 0 (ON) Master Serial
1 (OFF) 1 (OFF) 1 (OFF) 1 (OFF) Slave Serial
1 (OFF) 1 (OFF) 0 (ON) 0 (ON) Master Parallel
0 (ON) 1 (OFF) 1 (OFF) 0 (ON) Master Byte
1 (OFF) 0 (ON) 0 (ON) 1 (OFF) Slave Parallel
X (don’t care) X (don’t care) X (don’t care) X (don’t care) ispJTAG
Bank1 VCCIO
(see Appendix A, Figure 8)
VCCIO1 can be selected on the board to be either 3.3V or 2.5V using J107.
A jumper shunt placed between pin 1 and pin 2 will connect 2.5V. A jumper shunt between pin 2 and pin 3 will con-
nect 3.3V. The user must pay attention to the design and select the correct supply for VCCIO1.
On-Board Flash Memory
(see Appendix A, Figure 7)
Three memory devices (U3 and U22) are on board for non-volatile configuration memory storage. SW3 is used to
control writing and reading from the memory. U3 is an 8M, 8-pin SOIC Flash device and U22 is a 64M, 16-pin
TSSOP Flash device. U22 is located on the bottom side (secondary) of the PCB.
Refer to TN1100, SPI Serial Flash Programming Using ispJTAG in LatticeSC Devices for recommended proce-
dures and software usage.
To use both SPI Flash devices to program the LatticeSC device, the user must write to the Flash devices individu-
ally. This is accomplished by setting SW3 accordingly. Writing to Flash #1 (U22), close 3 and 5 switch positions
(ON) and open all others.
Writing to Flash #2 (U3), close 2 and 4 switch positions (ON) and open all others.
For reading from the Flash devices individually, use the same switch settings as described for writing. For reading
from both Flash devices in a cascading format, close switch positions (1, 3, 4, 5, 8).
FPGA Clock Management
(see Appendix A, Figure 14)
The evaluation board includes various features for generating and managing on-board clocks. The clocks are gen-
erated from either input provided from SMAs (see Ta bl e 6) or from crystal oscillators (Y1 and Y3). Y1 is socketed
for interchangeability and Y3 is a 312.5MHz surface-mount with an enable/disable jumper (J102). Y4 and Y5 also
can be selected using J108 to disable Y5.

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Lattice Semiconductor User’s Guide
When Y3 or Y5 are enabled, the user should remove Y1 or Y4 respectively to eliminate contention issues between
the clock sources.
There are several resistor stuffing options that may be needed based on the user’s requirements, R183 and R184
are left OPEN by factory default allowing connection to SMA inputs via R181 and R182. R181 and R182 are factory
populated with 0-ohm resistors. To utilize the Y1 or Y3 oscillators, the user should move the 0-ohms resistors from
R183 and R184 to R181 and R182.
This scenario is the same for R208 and R209 with R212 and R213 respectively.
A 100-ohm termination is optionally available and needs to be added to R185 and R186 if the SMA clock input are
not used. R185 and R186 are left OPEN at the factory and provide input termination to the B and A SERDES
Quads respectively.
Table 6. Reference Clock Input SMA Connections
J91 Reference + Input PCS361
J92 Reference - Input PCS361
J110 Reference + Input PCS360
J111 Reference - Input PCS360
A 100.0MHz surface-mounted oscillator (Y2) is also provided and fanned-out to three general-purpose FPGA
inputs.
SERDES
(see Appendix A, Figure 10)
SERDES Reference Clock
The 50-ohm terminated SMA connectors provide the supply reference clocks directly to the LatticeSC device. This
device will drive clocks to both SERDES quads via 100-ohm LVDS signaling. On-board clock oscillators mentioned
in the previous sections can be chosen to drive the same SERDES reference clocks.
SERDES Channels
Surface Mounted SMA Connections
(see Appendix A, Figure 10)
DC coupled top-mounted SMA connectors connect to the SERDES Tx and Rx channels of Quad B SERDES on
the left side (PCS 361). These pins are directly coupled to the designated SMA connector creating a path for both
input and output differential data.
Table 7. SERDES Connectors (see Appendix A, Figure 10)
J11 B_HDINN0_L
J6 B_HDINP0_L
J20 B_HDINN1_L
J16 B_HDINP1_L
J27 B_HDINN2_L
J23 B_HDINP2_L
J31 B_HDINN3_L
J28 B_HDINP3_L
J10 B_HDOUTN0_L
J5 B_HDOUTP0_L

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PCI Express x1 Cable Connectors
PCI Express x1 Cable Connectors (CON1 and CON2) are provided to demonstrate cable capabilities of the
SERDES channels. These cable connectors conform with the PCI Express Cable Specifications. A simple cable
loopback connected between the connectors can be used to evaluate this feature.
SERDES SMPTE Channels
(see Appendix A, Figure 10)
A single-channel 75-ohm SERDES channel is connected to BNC edge connectors. These connections are pro-
vided to connect to SMPTE video equipment. The channels include the appropriate passive components for
interoperability to SMPTE devices.
Table 8. SERDES SMPTE BNC Connectors (see Appendix A, Figure 10)
J9 A_HDINN1_L
J4 A_HDINP1_L
J21 A_HDOUTN1_L
J14 A_HDOUTP1_L
SERDES PCI Express Channels
(see Appendix A, Figure 10)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge-
fingers (CN1) to fit directly into an x4 host receptacle. Power can be supplied directly from the PCI Express host via
the edge-finger connections.
FPGA Test Pins
General-purpose FPGA pins are available for user applications. FPGA pins are connected to switches and LEDS
designated according to the following table.
Table 9. FPGA Test Pins (see Appendix A, Figure 7)
Switch BGA Netname LED BGA NetName
SW2D A20 Switch1 D2 A19 RED1
SW2C K22 Switch2 D5 J21 YELLOW1
SW2B K21 Switch3 D7 H21 GREEN1
SW2A G20 Switch4 D9 B18 BLUE1
SW1D F20 Switch5 D3 A18 RED2
SW1C J22 Switch6 D6 H20 YELLOW2
SW1B H22 Switch7 D8 H19 GREEN2
SW1A B19 Switch8 D10 E19 BLUE2
Note: LEDs will illuminate if connected to an un-programmed FPGA pin. It is recommended that a pull-down be
programmed on FPGA output pins.
J19 B_HDOUTN1_L
J15 B_HDOUTP1_L
J26 B_HDOUTN2_L
J22 B_HDOUTP2_L
J30 B_HDOUTN3_L
J28 B_HDOUTP3_L