Lattice Semiconductor MachXO2 Series User manual

February 2013
Revision: EB68_02.0

MachXO2 Breakout Board Evaluation Kit 
User’s Guide

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MachXO2 Breakout Board
Evaluation Kit User’s Guide
Introduction
Thank you for choosing the Lattice Semiconductor MachXO2™ Breakout Board Evaluation Kit!
This user’s guide describes how to start using the MachXO2 Breakout Board, an easy-to-use platform for evaluat-
ing and designing with the MachXO2 ultra-low density FPGA. Along with the board and accessories, this kit
includes a pre-loaded demonstration design. You may also reprogram the on-board MachXO2 device to review
your own custom designs.
The MachXO2 Breakout Board currently features the MachXO2-7000HE device. A previous version of this board
featured the MachXO2-1200ZE. The board design and features have not changed, and consequently, this docu-
ment can be used as a guide for either version of the board. If you require a board featuring the MachXO2-1200ZE,
Lattice recommends the MachXO2 Pico Development Kit.
See “Ordering Information” on page 16 for more information.
Note: Static electricity can severely shorten the lifespan of electronic components. See the Storage and Handling
section of this document for handling and storage tips.
Features
The MachXO2 Breakout Board Evaluation Kit includes:
•MachXO2 Breakout Board – The board is a 3” x 3” form factor that features the following on-board components
and circuits:
– MachXO2 FPGA – Current board version: LCMXO2-7000HE-4TG144C 
(Previous board version no longer available: LCMXO2-1200ZE-1TG144C)
– USB mini-B connector for power and programming
– Eight LEDs
– 60-hole prototype area
– Four 2x20 expansion header landings for general I/O, JTAG, and external power
– 1x8 expansion header landing for JTAG
– 3.3V and 1.2V supply rails
•Pre-loaded Demo – The kit includes a pre-loaded counter design that highlights use of the embedded MachXO2
oscillator and programmable I/Os configured for LED drive.
•USB Connector Cable – The board is powered from the USB mini-B socket when connected to a host PC. The
USB channel also provides a programming interface to the MachXO2 JTAG port.
•Lattice Breakout Board Evaluation Kits Web Page – Visit www.latticesemi.com/breakoutboards for the latest
documentation (including this guide) and drivers for the kit.
The content of this user’s guide includes demo operation, programming instructions, top-level functional descrip-
tions of the Breakout Board, descriptions of the on-board connectors, and a complete set of schematics.

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Figure 1. MachXO2 Breakout Board, Top Side
Two 2x20
Header Landings
(J3, J5)
Two 2x20
Header Landings
(J2, J4)
MachXO2
PLD (U3)
FTDI
USB to UART/FIFO
IC (U1)
JTAG Header
Landing (J1)
USB Mini-B
Socket (J7)
Power LED
(PWR_ON)
Power/GND
Test Points
(TP1, TP2, TP3)
4x15 60-Hole
Prototype Array (J6)LED Array (J4)
Storage and Handling
Static electricity can shorten the lifespan of electronic components. Please observe these tips to prevent damage
that could occur from electro-static discharge:
• Use anti-static precautions such as operating on an anti-static mat and wearing an anti-static wrist-band.
• Store the evaluation board in the packaging provided.
• Touch a metal USB housing to equalize voltage potential between you and the board.
Software Requirements
You should install the following software before you begin developing new designs for the Breakout board:
• Lattice Diamond®design software
• FTDI Chip USB hardware drivers (installed as an option within the Diamond installation program)
MachXO2 Device
This board currently features the MachXO2-7000HE FPGA which offers embedded Flash technology for instant-
on, non-volatile operation in a single chip. Numerous system functions are included, such as two PLLs and 256
Kbits of embedded RAM plus hardened implementations of I2C, SPI, timer/counter, and user Flash memory. Flexi-
ble, high performance I/Os support numerous single-ended and differential standards including LVDS, and also
source synchronous interfaces to DDR/DDR2/LPDDR DRAM memory. The 144-pin TQFP package provides up to

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114 user I/Os in a 20mm x 20mm form factor. Previous versions of this board featured the MachXO2-1200ZE PLD
in the same package. This version of the board is no longer available. A complete description of this device can be
found in the MachXO2 Family Data Sheet.
Demonstration Design
Lattice provides a simple, pre-programmed demo to illustrate basic operation of the MachXO2 device. The design
integrates an up-counter with the on-chip oscillator.
Note: You may obtain your Breakout Board after it has been reprogrammed. To restore the factory default demo
and program it with other Lattice-supplied examples see the Download Demo Designs section of this document.
Run the Demonstration Design
Upon power-up, the preprogrammed demonstration design automatically loads and drives the LED array in an
alternating pattern. The program shows a clock generator based on the MachXO2 on-chip oscillator. The counter
module is clocked at the oscillator default frequency of 2.08MHz to illustrate how low speed timer functions can be
implemented with a FPGA. The 22-bit up-counter further divides the clock to advance the LED display approxi-
mately every 500ms. The resulting light pattern will appear as an alternating pair of lit LEDs per row.
Figure 2. Demonstration Design Block Diagram
1x8LED
Array
MachXO2
22-bit
Up-Counter
Clock
Generator 2.08MHz
c_delay[21:0]
c_delay[20]
(~2 Hz)
WARNING: Do not connect the Breakout Board to your PC before you follow the driver installation procedure of
this section.
Communication with the Breakout Board with a PC via the USB connection cable requires installation of the FTDI
chip USB hardware drivers. Loading these drivers enables the computer to recognize and program the Breakout
Board. Drivers can be loaded as part of the installation of Lattice Diamond design software or Diamond Program-
mer, or as a stand-alone package.
To load the FTDI Chip USB hardware drivers as part of the Lattice Diamond installation:
1. Select Programmer Drivers in the Product Options of Lattice Diamond Setup.
2. Select FTDI Windows USB Driver or All Drivers in the LSC Drivers Install/Uninstall dialog box.
3. Click Finish to install the USB driver.
4. After the driver installation is complete, connect the USB cable from a USB port on your PC to the board’s USB
mini-B socket (J2). After the connection is made, a green Power LED (D9) will light indicating the board is pow-
ered on.
5. The demonstration design will automatically load and drive the LED array in an alternating pattern.

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To load the FTDI chip USB hardware drivers via the stand-alone package:
1. Browse to www.latticesemi.com/breakoutboards and download the FTDI Chip USB Hardware Drivers package.
2. Extract the FTDI chip USB Hardware driver package to your PC hard drive.
3. Connect the USB cable from a USB port on your PC to the board’s USB mini-B socket (J7). After the connec-
tion is made, a green Power LED (D9) will light indicating the board is powered on.
4. If you are prompted, “Windows may connect to Windows Update” select No, not this time from available
options and click Next to proceed with the installation. Choose the Install from specific location (Advanced)
option and click Next.
5. Search for the best driver in these locations and click the Browse button to browse to the Windows driver folder
created in the Download Windows USB Hardware Drivers section. Select the CDM 2.04.06 WHQL Certified
folder and click OK.
6. Click Next. A screen will display as Windows copies the required driver files. Windows will display a message
indicating that the installation was successful.
7. Click Finish to install the USB driver.
8. The demonstration design will automatically load and drive the LED array in an alternating pattern.
See the Troubleshooting section of this guide if the board does not function as expected.
Download Demo Designs
The counter demo is preprogrammed into the Breakout Board, however over time it is likely your board will be mod-
ified. Lattice distributes source and programming files for demonstration designs compatible with the Breakout
Board. Please make sure you're downloading the demo design that matches your version of the board. Demo
designs for both the 1200ZE and 7000HE versions of the board are available. The description below references the
7000HE version, but instructions are similar for the 1200ZE version.
To download demo designs:
1. Browse to the Lattice Breakout Board Evaluation Kits web page (www.latticesemi.com/breakoutboards) of the
Lattice web site. Select MachXO2 Breakout Board Demo Source and save the file.
2. Extract the contents of MachXO2_7000HE_BB_Eval_Kit_v01.0.zip to an accessible location on your hard
drive.
The demo design directory Demo_LED is unpacked with all design files needed for the demo, including the JEDEC
programming data file.
Continue to Programming a Demo Design with Lattice Diamond Design Software.
Programming a Demo Design with the Lattice Diamond Programmer
The demonstration design is pre-programmed into the MachXO2 Breakout Board by Lattice. If you have changed
the design but now want to restore the Breakout Board to factory settings, use the procedure described below.
To program the MachXO2 device:
1. Install, license and run Lattice Diamond software. See www.latticesemi.com/latticediamond for download and
licensing information.
2. Connect the USB cable to the host PC and the MachXO2 Breakout Board.
3. From Diamond, open the Demo_LED_OSC.ldf project file.

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4. Click the Programmer icon.
5. Click Detect Cable. The Programmer will detect the cable (Cable: USB2, Port: FTUSB-0).
6. Click the Program icon. When complete, PASS is displayed in the Status column.
MachXO2 Breakout Board
This section describes the features of the MachXO2 Breakout Board in detail.
Overview
The Breakout Board is a complete development platform for the MachXO2 FPGA. The board includes a prototyping
area, a USB program/power port, an LED array, and header landings with electrical connections to most of the
FPGA’s programmable I/O, power, and JTAG pins. The board is powered by the PC’s USB port or optionally with
external power. You may create or modify the program files and reprogram the board using Lattice Diamond soft-
ware.
Figure 3. MachXO2 Breakout Board Block Diagram
MachXO2-7000HE or
1200ZE device
2x20 Header
Landing (J5)
LED
Array
GPIO
8
2x20 Header
Landing (J2)
GPIO
2x20 Header
Landing (J3)
Bank 1
Bank 2
Bank 0
2x20 Header
Landing (J4)
Bank 3 (-1200ZE)
Bank 3,4 & 5 (-7000HE)
GPIO
GPIO
USB
Controller
USB Mini B
Socket
1x8Header
Landing (J1,
Optional JTAG
Interface)
A/Mini-B
USB Cable
JTAG
Programming

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Table 1 describes the components on the board and the interfaces it supports.
Table 1. Breakout Board Components and Interfaces
Component/Interface Type Schematic Reference Description
Circuits
USB Controller Circuit U2: FT2232H USB-to-JTAG interface and dual USB UART/FIFO IC
USB Mini-B Socket I/O J7:USB_MINI_B Programming and debug interface
Components
LCMXO2 FPGA U3: LCMXO2-
7000HE-4TG144C 7000-LUT device packaged in a 20 x 20mm, 144-pin TQFP
Interfaces
LED Array Output D8-D1 Red LEDs
Four 2x20 Header
Landings I/O
J2: header_2x20
J3: header_2x20
J4: header_2x20
J5: header_2x20
User-definable I/O
1x8 Header Landing I/O J1: header_1x8 Optional JTAG interface
4x15 60-Hole Prototype
Area Prototype area 100mil centered holes.
Test Points Power
TP1: +3.3V
TP2: +1.2V
TP3: GND
Power and ground reference points
Subsystems
This section describes the principle sub systems for the Breakout Board in alphabetical order.
Clock Sources
All clocks for the counter demonstration designs originate from the MachXO2 on-chip oscillator. You may use an
expansion header landing to drive a FPGA input with an external clock source.
Expansion Header Landings
The expansion header landings provide access to user GPIOs, primary inputs, clocks, and VCCO pins of the
MachXO2. The remaining pins serve as power supplies for external connections. Each landing is configured as
one 2x20 100 mil.
Table 2. Expansion Connector Reference
Item Description
Reference Designators J2, J3, J4, J5
Part Number header_2x20

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Table 3. Expansion Header Pin Information (J2)
Header Pin Number -1200ZE Function -7000HE Function MachXO2 Pin
1NC NC -
2VCCIO0 VCCIO0 118, 123, 135
3PT17D / DONE PT36D / DONE 109
4PT17C / INITn PT36C / INITn 110
5PT17B PT36B 111
6PT17A PT36A 112
7GND GND -
8GND GND -
9PT16D PT33B 113
10 PT16C PT33A 114
11 PT16B PT28B 115
12 PT16A PT28A 117
13 PT15D / PROGn PT27D / PROGn 119
14 PT15C / JTAGen PT27C / JTAGen 120
15 GND GND -
16 GND GND -
17 PT15B PT25B 121
18 PT15A PT25A 122
19 PT12D / SDA / PCLKC0_0 PT22D / SDA / PCLKC0_0 125
20 PT12C / SCL / PCLKT0_0 PT22C / SCL / PCLKT0_0 126
21 PT12B / PCLKC0_1 PT18B / PCLKC0_1 127
22 PT12A / PCLKT0_1 PT18A / PCLKT0_1 128
23 GND GND -
24 GND GND -
25 PT11D / TMS PT17D / TMS 130
26 PT11C / TCK PT17C / TCK 131
27 PT11B PT15B 132
28 PT11A PT15A 133
29 PT10D / TDI PT14D / TDI 136
30 PT10C / TDO PT14C / TDO 137
31 GND GND -
32 GND GND -
33 PT10B PT11B 138
34 PT10A PT11A 139
35 PT9D PT10B 140
36 PT9C PT10A 141
37 PT9B PT9B 142
38 PT9A PT9A 143
39 GND GND -
40 GND GND -

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Table 4. Expansion Header Pin Information (J3)
Header Pin Number -1200ZE Function -7000HE Function MachXO2 Pin
1VCC_1.2V VCC_1.2V 36, 72, 108, 144
2VCCIO1 VCCIO1 79, 88, 102
3VCC_1.2V VCC_1.2V 36, 72, 108, 144
4NC NC -
5PR10C PR24A 74
6PR10D PR24B 73
7PR10A PR23A 76
8PR10B PR23B 75
9GND GND -
10 GND GND -
11 PR9C PR21A 78
12 PR9D PR21B 77
13 PR9A PR18A 82
14 PR9B PR18B 81
15 GND GND -
16 GND GND -
17 PR8C PR17A 84
18 PR8D PR17B 83
19 PR8A PR16A 86
20 PR8B PR16B 85
21 GND GND -
22 GND GND -
23 PR5C / PCLKT1_0 PR12A / PCLKT1_0 92
24 PR5D / PCLKC1_0 PR12B / PCLKC1_0 91
25 PR5A PR11A 94
26 PR5B PR11B 93
27 GND GND -
28 GND GND -
29 PR4C PR9A 96
30 PR4D PR9B 95
31 PR4A PR7A 98
32 PR4B PR7B 97
33 GND GND -
34 GND GND -
35 PR3A PR5A 100
36 PR3B PR5B 99
37 PR2C PR3A 105
38 PR2D PR3B 104
39 PR2A PR2A 107
40 PR2B PR2B 106

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Table 5. Expansion Header Pin Information (J4)
Header Pin Number -1200ZE Function -7000HE Function MachXO2 Pin
1VCC_3.3V VCC_3.3V -
2VCCIO3 VCCIO3/4/5 30, 16, 7
3VCC_3.3V VCC_3.3V -
4NC NC -
5PL2A / L_GPLLT_FB PL3A / L_GPLLT_FB 1
6PL2B / L_GPPLC_FB PL3B / L_GPPLC_FB 2
7PL2C / L_GPLLT_IN PL4A / L_GPLLT_IN 3
8PL2D / L_GPLLC_IN PL4B / L_GPLLC_IN 4
9PL3A / PCLKT3_2 PL6A / PCLKT5_0 5
10 PL3B / PCLKC3_2 PL6B / PCLKC5_0 6
11 PL3C PL8A 9
12 PL3D PL8B 10
13 GND GND -
14 GND GND -
15 PL4A PL9A 11
16 PL4B PL9B 12
17 PL4C PL10A 13
18 PL4D PL10B 14
19 GND GND -
20 GND GND -
21 PL5A / PCLKT3_1 PL12A / PCLKT4_0 19
22 PL5B / PCLKC3_1 PL12B / PCLKC4_0 20
23 PL5C PL15A 21
24 PL5D PL15B 22
25 GND GND -
26 GND GND -
27 PL8A PL17A 23
28 PL8B PL17B 24
29 PL8C PL19A 25
30 PL8D PL19B 26
31 GND GND -
32 GND GND -
33 PL9A / PCLKT3_0 PL22A / PCLKT3_0 27
34 PL9B / PCLKC3_0 PL22B / PCLKC3_0 28
35 GND GND -
36 GND GND -
37 PL10A PL24A 32
38 PL10B PL24B 33
39 PL10C PL25A 34
40 PL10D PL25B 35

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Table 6. Expansion Header Pin Information (J5)
Header Pin Number -1200ZE Function -7000HE Function MachXO2 Pin
1NC NC -
2VCCIO2 VCCIO2 37, 51, 66
3PB20D / SI / SISPI PB38B / SI / SISPI 71
4PB20B PB37B 69
5PB20C / SN PB38A / SN 70
6PB20A PB37A 68
7PB18D PB35B 67
8PB18B PB31B 62
9PB18C PB35A 65
10 PB18A PB31A 61
11 GND GND -
12 GND GND -
13 PB15D PB29B 60
14 PB15B PB26B 58
15 PB15C PB29A 59
16 PB15A PB26A 57
17 GND GND -
18 GND GND -
19 PB11B / PCLKC2_1 PB23B / PCLKC2_1 56
20 PB11D PB18B 54
21 PB11A / PCLKT2_1 PB23A / PCLKT2_1 55
22 PB11C PB18A 52
23 GND GND -
24 GND GND -
25 PB9B / PCLKC2_0 PB16B / PCLKC2_0 50
26 PB9D PB13B 48
27 PB9A / PCLKT2_0 PB16A / PCLKT2_0 49
28 PB9C PB13A 47
29 GND GND -
30 GND GND -
31 PB6D / S0 / SPISO PB12B / S0 / SPISO 45
32 PB6B PB9B 43
33 PB6C / MCLK / CCLK PB12A / MCLK / CCLK 44
34 PB6A PB9A 42
35 GND GND -
36 GND GND -
37 PB4D PB6B 41
38 PB4B PB4B 39
39 PB4C / CSSPIN PB6A / CSSPIN 40
40 PB4A PB4A 38

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Figure 4. J2/J4 Header Landing Callout
NC IO0
109 110
111 112
GND GND
113 114
115 117
119 120
GND GND
121 122
125 126
127 128
GND GND
130 131
132 133
136 137
GND GND
138 139
140 141
142 143
GND GND
12
J2
3.3 IO3
3.3 NC
12
34
56
910
GND GND
11 12
13 14
GND GND
19 20
21 22
GND GND
23 24
25 26
GND GND
27 28
GND GND
32 33
34 35
12
J4
Top Side
J2 J4
LCMXO2-7000HE
4TG144C
Figure 5. J3/J5 Header Landing Callout
LCMXO2-7000HE
4TG144C
1.2 IO1
1.2 NC
74 73
76 75
GND GND
78 77
82 81
GND GND
84 83
86 85
GND GND
92 91
94 93
GND GND
96 95
98 97
GND GND
100 99
105 104
107 106
12
J3
NC IO2
71 69
70 68
67 62
65 61
GND GND
60 58
59 57
GND GND
56 54
55 52
GND GND
50 48
49 47
GND GND
45 43
44 42
GND GND
41 39
40 38
12
J5
J3 J5
Top Side

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Figure 6. J1 Header Landing and LED Array Callout
LCMXO2-7000HE
4TG144C
D8LED7
D7 LED6
D6 LED5
D5 LED4
D4 LED3
D3 LED2
D2 LED1
D1 LED0
107
LED Function
LED Array
MachXO2
Pin
106
105
104
100
99
98
97
Top Side
D8
D1
J1
3.3
TDO
TDI
NC
NC
TMS
GND
TCK
1
8
J1
MachXO2 FPGA
The MachXO2-7000HE-4TG144C is a 144-pin TQFP package FPGA device which provides up to 114 usable I/Os
in a 20 x 20mm package. 108 I/Os are accessible from the breakout board headers.
Table 7. MachXO FPGA Interface Reference
Item Description
Reference Designators U3
Part Number LCMXO2-7000HE-4TG144C
Manufacturer Lattice Semiconductor
Web Site www.latticesemi.com
JTAG Interface Circuits
For power and programming an FTDI USB UART/FIFO IC converter provides a communication interface between a
PC host and the JTAG programming chain of the Breakout Board. The USB 5V supply is also used as a source for
the 3.3V supply rail. A USB mini-B socket is provided for the USB connector cable.
Table 8. JTAG Interface Reference
Item Description
Reference Designators U1
Part Number FT2232HL
Manufacturer Future Technology Devices International (FTDI)
Web Site www.ftdichip.com

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Table 9. JTAG Programming Pin Information
Description MachXO2 Pin
Test Data Output 137:TDO
Test Data Input 136:TDI
Test Mode Select 130:TMS
Test Clock 131:TCK
LEDs
A green LED (D9) is used to indicate USB 5V power. Eight red LEDs are driven by I/O pins of the MachXO2 device.
Table 10. Power and User LEDs Reference
Item Description
Reference Designators D1, D2, D3, D4, D5, D6, D7, D8, D9
Part Number LTST-C190KRKT (D1-D8)
LTST-C190KGKT (D9)
Manufacturer Lite-On It Corporation
Web Site www.liteonit.com
Power Supply
3.3V and 1.2V power supply rails are converted from the USB 5V interface when the board is connected to a host
PC.
Test Points
In order to check the various voltage levels used, test points are provided:
•TP1:+3.3V
•T
P2:+1.2V
• TP3: GND
USB Programming and Debug Interface
The USB mini-B socket of the Breakout Board serves as the programming and debug interface.
JTAG Programming: For JTAG programming, a preprogrammed USB PHY peripheral controller is provided on the
Breakout Board to serve as the programming interface to the MachXO2 FPGA.
Programming requires the Lattice Diamond or ispVM System software.
Table 11. USB Interface Reference
Item Description
Reference Designators U1
Part Number FT2232HL
Manufacturer Future Technology Devices International (FTDI)
Web Site www.ftdichip.com

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Board Modifications
This section describes modifications to the board to change or add functionality.
Bypassing the USB Programming Interface
The USB programming interface circuit (USB Programming and Debug Interface section) may be optionally
bypassed by removing the 0 ohm resistors: R5, R6, R7, R8 (See Appendix A. Schematics, Sheet 2 of 5). Header
landing J1 provides JTAG signal access for jumper wires or a 1x8 pin header.
Applying External Power
The Breakout Board is powered by the circuit of Schematic Sheet 5 of 5 based on the 5V USB power source. You
may disconnect this power source by removing the 0 ohm resistors: R42 (VCC_1.2V) and R44 (VCC_3.3V). Power
connections are available from the expansion header landings, J3 (+1.2V, pins 1 and 3, schematic sheet 3 of 5) and
J4 (+3.3V, pins 1 and 3, schematic sheet 4 of 5).
Measuring Bank and Core Power
In addition to the expansion headers, test points (TP1, TP2) provide access to power supplies of the MachXO2
FPGA. Inline 1 ohm resistors: R24 (VCCIO0, +3.3V, Bank 0), R25 (VCCIO1, +3.3V, Bank 1), R26 (VCCIO2, +3.3V,
Bank 2), R27 (VCCIO3, +3.3V, Bank 3), R56 (VCC core, +1.2V) can be used to measure current for the power sup-
plies.
Mechanical Specifications
Dimensions: 3 in. [L] x 3 in. [W] x 1/2 in. [H]
Environmental Requirements
The evaluation board must be stored between -40° C and 100° C. The recommended operating temperature is
between 0° C and 90° C.
The board can be damaged without proper anti-static handling.
Glossary
FPGA: Field Programmable Gate Array
DIP: Dual in-line package
LED: Light Emitting Diode.
LUT: Look Up Table
PCB: Printed Circuit Board
RoHS: Restriction of Hazardous Substances Directive
USB: Universal Serial Bus
WDT: Watchdog Timer
Troubleshooting
Use the tips in this section to diagnose problems with the Breakout Board.
LEDs Do Not Flash
If power is applied but the board does not flash according to the preprogrammed counter demonstration then it is
likely the board has been reprogrammed with a new design. Follow the directions in the Demonstration Design sec-
tion to restore the factory default.

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USB Cable Not Detected
If Lattice Diamond Programmer or ispVM System does not recognize the USB cable after installing the Lattice USB
port drivers and rebooting, the incorrect USB driver may have been installed. This usually occurs if you attach the
board to your PC prior to installing the Lattice-supplied USB driver.
To access the Troubleshooting the USB Driver Installation Guide:
For Diamond software and standalone Diamond Programmer:
1. Start Diamond or Diamond Programmer and choose Help.
2. Search for USB driver or Troubleshooting, then select the Troubleshooting the USB Driver topic.
3. Follow the directions to install the Lattice USB driver.
For ispVM:
1. Start ispVM System and choose Options > Cable and I/O Port Setup.
The Cable and I/O Port Setup Dialog appears.
2. Click the Troubleshooting the USB Driver Installation Guide link.
The Troubleshooting the USB Driver Installation Guide document appears in your system’s PDF file reader.
3. Follow the directions to install the Lattice USB driver.
Determine the Source of a Pre-Programmed Device
If the Breakout Board has been reprogrammed, the original demo design can be restored. To restore the board to
the factory default, see the Download Demo Designs section for details on downloading and reprogramming the
device.
Ordering Information
Description Ordering Part Number China RoHS Environment-Friendly Use Period (EFUP)
MachXO2-7000HE Breakout Board Evaluation Kit LCMXO2-7000HE-B-EVN
MachXO2 Breakout Board Evaluation Kit LCMXO2-1200ZE-B-EVN1
1.For reference only. This version of the board is no longer available for sale.
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
[phone] (Outside North America)
e-mail: [e-mail]
Internet: www.latticesemi.com

17
MachXO2 Breakout Board
Evaluation Kit User’s Guide
Revision History
Date Version Change Summary
December 2011 01.0 Initial release.
January 2012 01.1 Figure “MachXO2-1200ZE Breakout Board, Top Side” updated with revi-
sion B board photo.
December 2012 01.2 Updated document to describe new version of the board featuring the
MachXO2-7000HE. Indicated that the MachXO2-1200ZE version of the
board is no longer available.
February 2013 02.0 Updated Tables 3-6 to include -7000HE information. Added -7000HE
notes to Figure 3 and Appendix A.
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.

18
MachXO2 Breakout Board
Evaluation Kit User’s Guide
Appendix A. Schematics
Note: The schematics are drawn using the MachXO2-1200ZE device. Please consult Tables 3 through 6 for -1200
and -7000HE pin name and bank synonyms. Pin numbers are correct for either device.
Figure 7. Block Diagram
5 5
4
4
3 3
2 2
1
1
D D CC B B A A
FPGA
Power from USB 5V
BANK 3
BANK 1
BANK 0
BANK 2
LCMXO2-7000HE-4TG144C or LCMXO2-1200ZE-1TG144C
HEADER
HEADER
HEADER
I/Os + SPI
I/Os
I/Os
HEADER
I/Os + I2C
JTAG
RS232
USB CONNECTOR
USB to JTAG / RS232
LEDS(1-8)
Title Size Document Number Date: Sheet of
AXELSYS
Lattice MachXO2 1200ZE Breakout Board - Block Diagram
B
15Thursday, April 21, 2011
Title Size Document Number Date: Sheet of
AXELSYS
Lattice MachXO2 1200ZE Breakout Board - Block Diagram
B
15Thursday, April 21, 2011
Title Size Document Number Rev Date: Sheet of
AXELSYS
LCMXO2-7000HE-B-EVN or LCMXO2-1200ZE-B-EVN
A
Lattice MachXO2 1200ZE Breakout Board - Block Diagram
B
15Thursday, April 21, 2011

19
MachXO2 Breakout Board
Evaluation Kit User’s Guide
Figure 8. USB Interface to JTAG
5 5
4
4
3 3
2
2
1
1
D D CC B B A A
FOR FUTURE RS232 FUNCTION
FT_EECS FT_EECLK
FT_EEDATA
TMS TDI TDO
TCK
TDO
TDI
TMS
TCK
+3.3V
VCC1_8FT
VCC1_8FT
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
TCK 3 TDI 3
TDO 3 TMS 3
DM5 DP5
RS232_Rx_TTL 3
RS232_Tx_TTL 3
RTSn 3
DTRn 3
CTSn 3
DSRn 3 DCDn 3
Title Size Document Number Rev Date: Sheet of
AXELSYS
LCMXO2-1200ZE-B-EVN
A
Lattice MachXO2 1200ZE Breakout Board -USB to JTAG B
25Thursday, April 21, 2011
Title Size Document Number Rev Date: Sheet of
AXELSYS
LCMXO2-1200ZE-B-EVN
A
Lattice MachXO2 1200ZE Breakout Board -USB to JTAG B
25Thursday, April 21, 2011
Title Size Document Number Rev Date: Sheet of
AXELSYS
LCMXO2-1200ZE-B-EVN
A
Lattice MachXO2 1200ZE Breakout Board -USB to JTAG B
25Thursday, April 21, 2011
R170DNI
L1
600ohm 500mA
12
R13 10k
C14
18pF
R3 5k1
R180DNI
R92k2
C8 0.1uF
C10 10uF
R70
R140DNI
R19 2k2
R200DNI
FTDI High-Speed USB FT2232H
FT2232HL U1
VREGIN
50
VREGOUT
49
DM
7
DP
8
REF
6
RESET#
14
EECS
63
EECLK
62
EEDATA
61
OSCI
2
OSCO
3
TEST
13
ADBUS0 16
ADBUS1 17
ADBUS2 18 ADBUS3 19
VPHY 4
VPLL 9
VCORE 12
VCORE 37
VCORE 64
VCCIO 20
VCCIO 31
VCCIO 42
VCCIO 56
AGND
10
GND
1
GND
5
GND
11
GND
15
GND
25
GND
35
GND
47
GND
51
PWREN# 60
SUSPEND# 36
ADBUS4 21
ADBUS5 22 ADBUS6 23
ADBUS7 24 ACBUS0 26
ACBUS1 27 ACBUS2 28 ACBUS3 29
ACBUS4 30
ACBUS5 32
ACBUS6 33
ACBUS7 34 BDBUS0 38 BDBUS1 39
BDBUS2 40
BDBUS3 41 BDBUS4 43
BDBUS5 44 BDBUS6 45
BDBUS7 46 BCBUS0 48 BCBUS1 52 BCBUS2 53
BCBUS3 54 BCBUS4 55
BCBUS5 57 BCBUS6 58
BCBUS7 59
R1 5k1
X1
12MHZ
1
133
G1
2G2 4
R10 12k 1%
C6 0.1uF
R2 5k1
R210DNI
C13
18pF
C11 0.1uF
93LC56-SO8
U2
CS 1
CLK 2
DI 3
DO 4
VSS
5ORG 6NU 7VCC
8
C1 4u7
12
C3 4u7
12
R60
R150DNI
C4 0.1uF
C9 0.1uF
R4 2k2
R50
R11 10k
L2
600ohm 500mA
1
2
C2 0.1uF
R160DNI
R80
C5 0.1uF
R12 10k
J1
header_1x8
DNI
11
22
33 44 55 66 77 88
C12
0.1uF
C7 0.1uF

20
MachXO2 Breakout Board
Evaluation Kit User’s Guide
Figure 9. FPGA
5 5
4
4
3 3
2 2
1
1
D D CC B B A A
MAKE PWR TRACES CAPABLE OF 1A
MAKE PWR TRACES CAPABLE OF 1A
PR10D PR10C PR10B PR10A PR9D
PR9C
PR9B
PR9A
PR8D PR8C PR8B PR8A
PCLKC1_PR5D
PR5B
PCLKT1_PR5C
PR5A
PR4D
PR4B PR4C
PR4A
PT17D_DONE
PT17C_INITn
PT17B
PT17A
PT16D PT16C PT15D_PROGn
PT15C_JTAGen
PT15B
PT15A
PT12D_SDA_PCLKC0_0
PT12B_PCLKC0_1
PT12C_SCL_PCLT0_0
PT12A_PCLKT0_1 PT11D_TMS
PT11B
PT11C_TCK_TESTCLK
PT11A
PT10D_TDI
PT10C_TDO
PT10B PT10A PT9D PT9C PT9B
PT9A
PR10D
PR10B
PR10C
PR10A
PR9D PR9B
PR9C
PR9A
PR8D PR8B
PR8C PR8A
PCLKC1_PR5D PR5B
PCLKT1_PR5C
PR5A
PR4D PR4C PR4B PR4A PR3B PR2D
PR2B
PR3A
PR2C
PR2A
PT16B
PT16A
PR2B PR2A
PR2D PR2C PR3B
PR3A
PT17BPT17A PT16B
PT16A
PT15A PT15B
PT12B_PCLKC0_1PT12A_PCLKT0_1
PT11B
PT11A
PT10BPT10A
PT9BPT9A
PT12C_SCL_PCLT0_0 PT12D_SDA_PCLKC0_0
PT17C_INITn PT17D_DONE
PT16C
PT15D_PROGnPT15C_JTAGen
PT11D_TMS
PT11C_TCK_TESTCLK
PT9DPT9C
PT10D_TDIPT10C_TDO
PT16D
VCCIO0 VCCIO1
VCC_1.2V
VCCIO0
VCCIO1
+3.3V
VCCIO0
+3.3V VCCIO1
+3.3V
TDO2 TDI2
TMS2 TCK2
LED0 5 LED1 5 LED2 5 LED3 5 LED4 5 LED5 5 LED6 5 LED7 5
RS232_Rx_TTL 2
RS232_Tx_TTL 2
RTSn 2
DTRn 2
CTSn 2
DSRn 2
DCDn 2
Title Size Document Number Rev Date: Sheet of
AXELSYS
LCMXO2-1200ZE-B-EVN
A
Lattice MachXO2 1200ZE Breakout Board - FPGA
B
35Thursday, April 21, 2011
Title Size Document Number Rev Date: Sheet of
AXELSYS
LCMXO2-1200ZE-B-EVN
A
Lattice MachXO2 1200ZE Breakout Board - FPGA
B
35Thursday, April 21, 2011
Title Size Document Number Rev Date: Sheet of
AXELSYS
LCMXO2-1200ZE-B-EVN
A
Lattice MachXO2 1200ZE Breakout Board - FPGA
B
35Thursday, April 21, 2011
J2 Header2x20 DNI
2 4
6
8
10 12 14 16 18 20
24
22
26
28
30 32
34
36
38
40 39
37
35 33 31
29 27
25
23 21
19 17
15 13 11 9
7 5
3
1
C23
0.1uF
C15 0.1uF
C21
0.01uF
J3 Header2x20 DNI
2 4 6 8
10 12 14
16
18
20
24 22
26 28
30 32 34 36
38
40 39
37
35
33
31
29
27 25
23
21
19 17 15
13
11
9 7
5
3
1
C18 0.1uF
C20 0.1uF
BANK 0 BANK 1
LCMXO2-7000HE-4TG144C or LCMXO2-1200ZE-1TG144C
U3-2 PT17D/DONE
109
PT17C/INITn
110
PT17B
111
PT17A
112
PT16D
113
PT16C
114
PT16B
115
PT16A
117
VCCIO0
118
PT15D/PROGRAMn
119
PT15C/JTAGENB
120
PT15B
121
PT15A
122
VCCIO0
123
VCCIO0
135
PT12D/SDA/PCLKC0_0
125
PT12C/SCL/PCLKT0_0
126
PT12B/PCLKC0_1
127
PT12A/PCLKT0_1
128
PT11D/TMS
130
PT11C/TCK/TEST_CLK
131
PT11B
132
PT11A
133
PT10D/TDI
136
PT10C/TDO
137
PT10B
138
PT10A
139
PT9D
140
PT9C
141
PT9B
142
PT9A
143
PR10D 73 PR10C 74
PR10B 75 PR10A 76
VCCIO1 79 VCCIO1 88 VCCIO1 102
PR9D 77 PR9C 78
PR9B 81 PR9A 82
PR8D 83 PR8C 84
PR8B 85 PR8A 86
NC4 87
NC5 89
PCLKC1_0/PR5D 91
PCLKT1_0/PR5C 92
PR5B 93 PR5A 94
PR4D 95
PR4C 96
PR4B 97 PR4A 98 PR3B 99 PR3A 100
NC6 103
PR2D 104 PR2C 105
PR2B 106 PR2A 107
C22 0.1uF
C16 0.1uF
R24 1
R23 2k2
C17
0.01uF
C19 0.1uF
R22 2k2
R25 1
C24 0.1uF