Lattice Semiconductor ECP5 Versa User manual

ECP5 VIP Processor Board
Evaluation Board User Guide
FPGA-EB-02001 Version 1.2
June 2017

ECP5 VIP Processor Board
Evaluation Board User Guide
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02001-1.2
Contents
Acronyms in This Document .................................................................................................................................................4
Introduction...................................................................................................................................................................5
Headers and Test Connections ......................................................................................................................................7
Programming Circuit......................................................................................................................................................8
ECP5 Interface Support..................................................................................................................................................9
4.1. Clock Interface.....................................................................................................................................................9
4.2. DDR3 Interface ....................................................................................................................................................9
4.3. Nanovesta Interface ............................................................................................................................................9
4.4. Upstream and Downstream interface...............................................................................................................10
4.5. ispClock5406D Interface....................................................................................................................................10
4.6. Debugging Interface ..........................................................................................................................................11
Power Supply ...............................................................................................................................................................12
ECP5 I/O Ball Mapping to Connectors .........................................................................................................................14
Status Indicators ..........................................................................................................................................................18
Ordering Information ..................................................................................................................................................19
References ..........................................................................................................................................................................20
Technical Support Assistance...............................................................................................................................................20
Appendix A. ECP5 VIP Processor Board Schematics ...........................................................................................................21
Appendix B. ECP5 VIP Processor Board Bill of Materials ....................................................................................................29
Revision History...................................................................................................................................................................38
Figures
Figure 1.1. Top View of ECP5 VIP Processor Board and its Key Components .......................................................................6
Figure 1.2. Bottom View of ECP5 VIP Processor Board.........................................................................................................6
Figure 3.1. Programming Block using USB Interface.............................................................................................................8
Figure 4.1. DDR3 Interface....................................................................................................................................................9
Figure 4.2. Nanovesta Connector Interface ..........................................................................................................................9
Figure 4.3. Upstream and Downstream Connector ............................................................................................................10
Figure 4.4. ispClock5406D Interface ...................................................................................................................................10
Figure 5.1. Power Supply Block...........................................................................................................................................12
Figure A.1. Block Diagram...................................................................................................................................................21
Figure A.2. FTDI and Programming Interface......................................................................................................................22
Figure A.3. Power Regulator Interface................................................................................................................................23
Figure A.4. MIPI and GPIO Connector Interface .................................................................................................................24
Figure A.5. DDR3 Interface .................................................................................................................................................25
Figure A.6. SERDES Interface ..............................................................................................................................................26
Figure A.7. ECP5 Decoupling ...............................................................................................................................................27
Figure A.8. HISPI/CSI2 Connector .......................................................................................................................................28

ECP5 VIP Processor Board
Evaluation Board User Guide
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02001-1.2 3
Tables
Table 2.1. Headers and Test Connectors ..............................................................................................................................7
Table 4.1. Header (J14) .......................................................................................................................................................11
Table 4.2. Switch (SW3) ......................................................................................................................................................11
Table 4.3. JTAG Connector (J1) ...........................................................................................................................................11
Table 5.1. Power LEDs ........................................................................................................................................................12
Table 5.2. Device Power Rail Summary and Test Points.....................................................................................................13
Table 6.1. Upstream Connector Mapping ..........................................................................................................................14
Table 6.2. Downstream Connector Pin Mapping................................................................................................................15
Table 6.3. Nanovesta Connector Pin Mapping ...................................................................................................................17
Table 7.1. Status LED I/O Map ............................................................................................................................................18
Table 8.1. Reference Part Number......................................................................................................................................19

ECP5 VIP Processor Board
Evaluation Board User Guide
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02001-1.2
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
CMOS
Complementary Metal-Oxide Semiconductor
CSI-2
Camera Serial Interface
DDR
Double Data Rate
DSI
Display Serial Interface
FTDI
Future Technology Devices International
GPIO
General Purpose Input/Output
I2C
Inter-Integrated Circuit
LVDS
Low-Voltage Differential Signaling
SPI
Serial Peripheral Interface
VIP
Video Interface Platform
VTT
Tracking Termination Voltage

ECP5 VIP Processor Board
Evaluation Board User Guide
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02001-1.2 5
1. Introduction
This document describes the Lattice Semiconductor ECP5 VIP Processor Board which is a key component of Lattice’s
Video Interface Platform (VIP) board interconnect. Lattice VIP boards can be interconnected to create solutions for
MIPI®CSI-2/DSI, SERDES, LVDS and more.
The content of this user guide includes descriptions of onboard jumper settings, programming circuit, a complete set of
schematics, and bill of materials for ECP5 VIP processor board.
Key features of the ECP5 VIP processor board include:
ECP5/5G
SERDES interface
Dual DDR3 interface
LVDS/MIPI Transmitter/Receiver interface
SPI flash configuration
General Purpose Input/Output
Programming Circuit
Mini-B USB connector to FTDI
FTDI to ECP5 using JTAG
FTDI to ispClock using JTAG
ispClock
SERDES reference clock generation interface
Figure 1.1 on the next page shows the top view of the ECP5 VIP processor board and its key components. Figure 1.2
shows the bottom view of the board.
Further Information
For more information on boards and kits available for the VIP system, visit www.latticesemi.com/boards
The board‘s key component is the ECP5™ FPGA. For details about ECP5, refer to FPGA-DS-02012, ECP5 and ECP5-
5G Family Data Sheet.
For the latest information about this board, demo files, further documentation and more, visit
www.latticesemi.com/Products/FPGAandCPLD/ECP5.aspx
Refer to Appendix A and Appendix B for the schematics and BOM of the ECP5 VIP processor board.

ECP5 VIP Processor Board
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© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02001-1.2
Figure 1.1. Top View of ECP5 VIP Processor Board and its Key Components
Figure 1.2. Bottom View of ECP5 VIP Processor Board

ECP5 VIP Processor Board
Evaluation Board User Guide
© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02001-1.2 7
2. Headers and Test Connections
Figure 1.1 shows the top view of the ECP5 VIP processor board. The headers and test connections on the board provide
access to ECP5 VIP processor board circuits. Table 2.1 lists the headers and test connectors.
Table 2.1. Headers and Test Connectors
Part
Description
Setting
J1
External JTAG interface
—
J2
Mini-B USB connector for programming
—
J52
JTAG/SPI Selection header
1–2 (SPI), 2–3 (JTAG)
J50
JTAG Daisy Chain connector
Refer to Schematic note in Appendix A
J3
ECP5 Configuration mode selection header
Refer to Schematic note in Appendix A
J53
FTDI Mode selection
1–2 (Normal), 2–3 (Reset)
J4
12 V DC power jack
—
J5, J6, J51, J9
ECP5 Banks 8, 1, 3, 4 voltage selection
1–2 (3V3), 2–3 (2V5)
J7, J55
ECP5 Banks 0, 2 voltage selection
1–2 (3V3), 2–3 (2V5), 2–4 (CN1/CN2_VCC)
J14
Debug Header
—
SW1
Global reset
—
SW4
Program reset for reprogram
—
SW3
General purpose DIP switches
—
SW2
Power on switch
—
J54
ispClock 5406 reference clock selector
1–2 (External), 2–3 (Internal)
CN2
Nanovesta serial interface connector
—
CN1
Nanovesta parallel interface connector
—
J10, J11
General purpose upstream connector
—
J12, J13
General purpose downstream connector
—

ECP5 VIP Processor Board
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-EB-02001-1.2
3. Programming Circuit
The Mini-B USB connector is used for programming the board by using Lattice Diamond®Programmer software.
Figure 3.1 shows the programming block of ECP5 VIP processor board.
The Mini-B USB connector interfaces to the FTDI FT2232H IC. The FTDI IC works with Diamond programmer software to
provide interfaces for:
JTAG –to program LFE5UM-85F and its SPI Flash and ispClock
SPI –to program external devices connected to the ECP5 VIP processor board
USB Mini-B
(J2)
FTDI Chip
(U1)
SPI Flash
(U52)
Upstream
connector
(J10)
LFE5UM-85F-
BG756 (U17)
JTAG
SPI/
JTAG
ispCLOCK5406D
(U53)
Downstream
connector
(J12)
SPI/
JTAG
JTAG
SPI/JTAG
Figure 3.1. Programming Block using USB Interface

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© 2017 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02001-1.2 9
4. ECP5 Interface Support
The ECP5 VIP processor board supports various onboard interfaces and external interfaces through board-to-board
connectors. The sections below describe key onboard interfaces supported on ECP5 VIP processor board.
Clock Interface
Clocking for the ECP5 device on the ECP5 VIP processor board can be done through onboard fixed frequency crystal
oscillators, and also internal OSC built inside the ECP5 device. The board has 100 MHz fixed frequency OSC to support
DDR3 Memory controller, and 27 MHz to support MIPI/LVDS related interfaces.
DDR3 Interface
Figure 4.1 shows the block diagram of the DDR3 Interface. The LFE5UM-85F-BG756 (U17) device DDR3 memory
controller is used to interface with onboard DD3 memory device and it supports a single rank and multiple memory
devices connected on the board.
Each memory device supports 16-bit parallel data with 1 Gb memory capacity. The combined capacity supported is
2 Gb. The DDR3 memory controller can be configured to support either 32-bit or 16-bit wide memory interface by
enabling the chip select signals for both memory devices.
This board is designed to support both on board VTT termination as well as on-die termination and can be configured
by memory controller.
LFE5UM-85F-BG756
(U17)
DDR3 Chip 1
(U12)
16-bit data
DDR3 Chip 2
(U19)
16-bit data
CNTRL
Figure 4.1. DDR3 Interface
Nanovesta Interface
Figure 4.2 shows the block diagram of the Nanovesta connector interface. The LFE5UM-85F-BG756 (U17) device
receives camera input from the Nanovesta connectors. Pin mapping of the Nanovesta connector interface is designed
such that the legacy Lattice Nanovesta camera sensor boards can be interfaced with ECP5 VIP processor board. It
supports both parallel and SLVS interface for receiving camera input from sensor module.
LFE5UM-85F-BG756
(U17)
Nanovesta Serial
Interface
Connector (CN2)
GPIO/SLVS I/F SLVS I/F
Nanovesta
Parallel Interface
Connector (CN1)
Figure 4.2. Nanovesta Connector Interface

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-EB-02001-1.2
Upstream and Downstream interface
Figure 4.3 shows the block diagram of the Upstream and Downstream connector. Upstream and Downstream
connectors act as board to board connector and are used to interface the ECP5 VIP processor board to any other
external boards for bridging applications. These connectors support interfaces, such as LVDS, MIPI, SPI, JTAG, SERDES
and general purpose interface.
LFE5UM-85F-BG756
(U17)
Downstream
connector 1 ( J12)
Downstream
connector 2 (J13)
LVDS/MIPI Rx,
SPI, JTAG,
SERDES Rx
MIPI/LVDS Tx,
GPIO I/F
LVDS/MIPI Tx,
SPI, JTAG,
SERDES Tx
Upstream
connector 2 (J11)
Upstream
connector 1 (J10)
LVDS/MIPI Rx,
GPIO I/F
Figure 4.3. Upstream and Downstream Connector
ispClock5406D Interface
Figure 4.4 shows the block diagram of the ispClock5406D interface. For more information on Lattice ispClock, visit
www.latticesemi.com/ispclock.
The ispClock5406D device can be programmed using JTAG through FTDI interface. This circuitry is used as a reference
clock generation circuit for the ECP5 SERDES interface. The input clock source for the reference clock generation circuit
can be onboard oscillator or the PLL output from ECP5 FPGA which can be selected by the ref_sel input of the
ispClock5406D.
ispClock5406D
(U53)
LFE5UM-85F-BG756
(U17)
156.25 MHz Clock OSC
(X4)
JTAG
Ref_Sel
ECP5_PLL
SERDES RefCLK LFE5UM-85F-BG756
(U17)
Figure 4.4. ispClock5406D Interface

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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02001-1.2 11
Debugging Interface
The ECP5 VIP processor board supports onboard debugging in the form of JTAG, GPIO Headers and onboard DIP
switches. Table 4.1–Table 4.3 list the ECP5 ball mapping for the debugging interfaces.
Table 4.1. Header (J14)
Header (J14)
Pin Number
Net Name
ECP5 Ball number
4
Header1
AK32
6
Header2
AJ32
8
Header3
AM30
10
Header4
AL30
1
Header5
AQK31
3
Header6
AJ31
5
Header7
AM31
7
Header8
AL32
2
VCCIO2
—
9
GND
—
Table 4.2. Switch (SW3)
Switch (SW3)
Pin Number
Net Name
ECP5 Ball Number
1
SW1
B26
2
SW2
C26
3
SW3
D26
4
SW4
A28
5
SW5
A29
6
SW6
A30
7
SW7
A31
8
SW8
B28
Table 4.3. JTAG Connector (J1)
JTAG Connector (J1)
Pin Number
Net Name
1
3V3
2
FTDI_TDO
3
FTDI_TDI
4
NC
5
NC
6
FTDI_TMS
7
GND
8
FTDI_TCK

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12 FPGA-EB-02001-1.2
5. Power Supply
The power supply to the development kit is provided from an external 12 V DC adaptor.
Figure 5.1 shows the power supply block of the ECP5 VIP processor board. The Mini-B USB connector is used only for
programming and the external power adaptor must be connected to source power for the on board regulators for the
normal operation and successful programming.
The external adaptor provides 12 V power source through voltage regulators on the board as well as to the external
boards connected to Nanovesta, upstream and downstream connectors. Each I/O bank voltage can be selected by
putting jumpers on J5, J6, J7, J9, J51, J55. See Table 5.1 for the voltage selection. All voltage generation from the
onboard regulator can be measured by a respective test point on the board.
J4 12 V to 5 V
converter (U54)
LDO (U10)
LDO (U11)
Mini-B USB
1.1 V
J3
12 V
VUSB
12 V to 2.5 V or
3.3 V dual
converter (U8)
12 V to 1.5 V or
1.1 V dual
converter (U9)
5 V
3.3 V
1.5 V
2.5 V
1.1 V
1.1 V
Power Jack
SW2
U7
FUSE
Figure 5.1. Power Supply Block
Table 5.1 lists the device power rails. There are five voltage regulators on the board used to supply the 5 V, 3.3 V, 2.5 V
1.5 V, and 1.1 V rails. The input to these regulators is either the external 12 V adaptor or on board regulators that is
connected to the board. Switch SW2 is used to connect or disconnect the external adaptor power to the board.
Table 5.1. Power LEDs
Voltage
Rail
LEDs
Colour
12
D15
Green
5
D23
Green
3.3
D17
Green
2.5
D14
Green
1.5
D16
Green
VCC_CORE
D18
Green
VCCA
D19
Green
VCCHTX
D20
Green

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FPGA-EB-02001-1.2 13
Table 5.2 lists the board voltage rails, including the rail source voltage, test point number, and voltage on net.
Table 5.2. Device Power Rail Summary and Test Points
Net Name
Source Rail
Test Points
Voltage on Net (V)
12 V
12_Ext
—
12
5 V
12 V
5V
5
3V3
12 V
3V3
3.3
2V5
12 V
2V5
2.5
1V5
12 V
1V5
1.5
VCC_CORE
12 V
VCC_CORE
1.1
VCCHTX
5 V
VCCHTX
1.1
VCCA
5 V
VCCA
1.1

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14 FPGA-EB-02001-1.2
6. ECP5 I/O Ball Mapping to Connectors
Table 6.1. Upstream Connector Mapping
J10
J11
Pin number on
Connector
Net Name
ECP5 Ball
Pin Number on
Connector
Net Name
ECP5 Ball
1
3V3
—
1
3V3
—
2
5V
—
2
3V3
—
3
3V3
—
3
3V3
—
4
5V
—
4
3V3
—
5
GND
—
5
UP_GPIO9
F29
6
5V
—
6
UP_GPIO17
A13
7
LVDS_CP
P27
7
UP_GPIO10
F28
8
GND
—
8
UP_GPIO18
A8
9
LVDS_CN
P26
9
UP_GPIO1
C29
10
LVDS_D2P
J30
10
UP_GPIO19
F9
11
GND
—
11
UP_GPIO2
C30
12
LVDS_D2N
K30
12
UP_GPIO20
D9
13
LVDS_D0P
D30
13
LDI_RX_D3_P
F32
14
GND
—
14
UP_GPIO21
C9
15
LVDS_D0N
D31
15
LDI_RX_D3_N
H32
16
LVDS_D3P
L31
16
UP_GPIO22
A9
17
GND
—
17
GND
—
18
LVDS_D3N
L30
18
GND
—
19
LVDS_D1P
K32
19
GND
—
20
GND
—
20
GND
—
21
LVDS_D1N
L32
21
LDI_RX_D2_P
J29
22
2V5
—
22
GND
—
23
GND
—
23
LDI_RX_D2_N
K29
24
2V5
—
24
UP_GPIO25
C10
25
DIR_GPIO3
—
25
UP_GPIO33
D13
26
GND
—
26
UP_GPIO26
B10
27
UP_MCLK
—
27
UP_GPIO34
C13
28
GSRN
AH1
28
UP_GPIO27
A10
29
UP_SISPI
—
29
LDI_RX_D0_P
K27
30
UP_GPIO48
C16
30
UP_GPIO28
E11
31
UP_SPISO
—
31
LDI_RX_D0_N
K26
32
UP_GPIO49
B16
32
UP_GPIO29
D11
33
UP_CSSPIN
—
33
GND
—
34
GND
—
34
UP_GPIO30
C11
35
UP_CDONE
—
35
GND
—
36
HDRXP0_D1CH0
AM17
36
GND
—
37
UP_CRESETB
—
37
LDI_RX_D1_P
J26
38
HDRXN0_D1CH0
AM18
38
GND
—
39
DIR_GPIO4
—
39
LDI_RX_D1_N
J27
40
GND
—
40
GND
—
41
SCL
AG1
41
UP_GPIO31
B11
42
HDRXP0_D1CH1
AM20
42
UP_GPIO39
B14

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FPGA-EB-02001-1.2 15
Table 6.1. Upstream Connector Mapping (Continued)
J10
J11
Pin number on
Connector
Net Name
ECP5 Ball
Pin Number on
Connector
Net Name
ECP5 Ball
43
SDA
AJ1
43
UP_GPIO32
F13
44
HDRXN0_D1CH1
AM21
44
UP_GPIO40
A14
45
FTDI_TCK
AK5
45
UP_GPIO37
D14
46
GND
—
46
UP_GPIO41
B4
47
FTDI_TDO
—
47
UP_GPIO38
C14
48
HDRXP0_D0CH0
AM8
48
UP_GPIO42
F15
49
FTDI_TDI
—
49
UP_GPIO45
A15
50
HDRXN0_D0CH0
AM9
50
UP_GPIO43
D15
51
FTDI_TMS
AM5
51
UP_GPIO50
D17
52
GND
—
52
UP_GPIO44
C15
53
DIR_GPIO5
—
53
GND
—
54
HDRXP0_D0CH1
AM11
54
GND
—
55
GND
—
55
GND
—
56
HDRXN0_D0CH1
AM12
56
GND
—
57
GND
—
57
2V5
—
58
GND
—
58
2V5
—
59
GND
—
59
2V5
—
60
DIR_GPIO1
—
60
2V5
—
Table 6.2. Downstream Connector Pin Mapping
J12
J13
Pin number on
Connector
Net Name
ECP5 Ball
Pin number on
Connector
Net Name
ECP5 Ball
1
GND
—
1
3V3
—
2
12V
—
2
3V3
—
3
MIPITX_CLKP
A18
3
3V3
—
4
12V
—
4
3V3
—
5
MIPITX_CLKN
C18
5
LDI_TX_D0_P
W31
6
12V
—
6
LDI_TX_D1_P
AB30
7
GND
—
7
LDI_TX_D0_N
Y32
8
12V
—
8
LDI_TX_D1_N
AB29
9
MIPITX_DATA0P
F18, R27
9
LDI_TX_D3_P
R32
10
MIPITX_DATA2P
D19, U29
10
LDI_TX_D2_P
AD27
11
MIPITX_DATA0N
A19, T27
11
LDI_TX_D3_N
T31
12
MIPITX_DATA2N
E19, V29
12
LDI_TX_D2_N
AE27
13
GND
—
13
DW_GPIO5
T29
14
GND
—
14
DW_GPIO27
AB28
15
MIPITX_DATA1P
B19, R29
15
DW_GPIO6
U28
16
MIPITX_DATA3P
F19, P31
16
DW_GPIO28
AB27
17
MIPITX_DATA1N
C19, T28
17
DW_GPIO7
V27
18
MIPITX_DATA3N
P30, A20
18
DW_GPIO29
AC26
19
GND
—
19
DW_GPIO8
V26
20
GND
—
20
GND
—
21
DW_GPIO46
A25
21
GND
—

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16 FPGA-EB-02001-1.2
Table 6.2. Downstream Connector Pin Mapping (Continued)
J12
J13
Pin number on
Connector
Net Name
ECP5 Ball
Pin number on
Connector
Net Name
ECP5 Ball
22
DW_GPIO48
D25
22
DW_GPIO30
AD26
23
DW_GPIO47
C25
23
DW_GPIO44
C24
24
DW_GPIO49
E25
24
DW_GPIO23
Y27
25
DIR_GPIO3
—
25
DW_GPIO45
D24
26
GND
—
26
DW_GPIO24
W28
27
ECP_SCLK
AM3
27
DW_GPIO11
P32
28
GSRN
AH1
28
DW_GPIO33
AE29
29
ECP_MOSI
AK2
29
DW_GPIO12
U31
30
DW_GPIO50
F25
30
DW_GPIO25
Y29
31
ECP_MISO
AJ2
31
DW_GPIO3
U27
32
DW_GPIO51
F17
32
DW_GPIO26
W29
33
FPGA_CSN
AG3
33
DW_GPIO4
U26
34
GND
—
34
DW_GPIO36
AC28
35
DW_DONE
AJ4
35
DW_GPIO15
W30
36
HDTXP0_D0CH0
AK9
36
DW_GPIO1
T30
37
DW_INITN
AG4
37
DW_GPIO16
Y30
38
HDTXN0_D0CH0
AK10
38
DW_GPIO2
N32
39
DIR_GPIO4
—
39
GND
—
40
GND
—
40
GND
—
41
SCL
AG1
41
DW_GPIO17
T32
42
HDTXP0_D0CH1
AK12
42
DW_GPIO39
AC31
43
SDA
AJ1
43
DW_GPIO18
AC30
44
HDTXN0_D0CH1
AK13
44
DW_GPIO40
AB32
45
FTDI_TCK
AK5
45
DW_GPIO19
AB31
46
GND
—
46
DW_GPIO41
AC32
47
FTDI_TDO
—
47
DW_GPIO20
V32
48
HDTXP0_D1CH0
AK18
48
DW_GPIO42
AD32
49
FTDI_TDI
—
49
DW_GPIO21
W32
50
HDTXN0_D1CH0
AK19
50
DW_GPIO43
A24
51
FTDI_TMS
AM5
51
DW_GPIO22
Y26
52
GND
—
52
LDI_TX_CK_P
R26
53
DIR_GPIO5
—
53
GND
—
54
HDTXP0_D1CH1
AK21
54
LDI_TX_CK_N
T26
55
GND
—
55
GND
—
56
HDTXN0_D1CH1
AK22
56
GND
—
57
VCCHTX
—
57
2V5
—
58
GND
—
58
2V5
—
59
VCCHTX
—
59
2V5
—
60
DIR_GPIO1
—
60
2V5
—

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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02001-1.2 17
Table 6.3. Nanovesta Connector Pin Mapping
Connector 1 (CN2)
Top - High SPI to Sensor
Connector 1 (CN1)
Top - Parallel up to Sensor1
Pin number on
Connector
Net Name
ECP5 Ball
Pin number on
Connector
Net Name
ECP5 Ball
1
5V
—
1
5V
—
2
5V
—
2
5V
—
3
CN2_VCC
—
3
CN1_VCC
—
4
VDDIO_RP
—
4
VDDIO_RH
A16
5
GND
—
5
GND
—
6
GND
—
6
GND
—
7
GND
—
7
GND
—
8
GND
—
8
GND
—
9
—
—
9
EXTCLK_FPGA
B17
10
HISPI_RESETN
C8
10
PIXCLK
C17
11
SLVS_3N
E30
11
LINE_VALID
A4
12
SLVS_5N
N29
12
FRAME_VALID
A5
13
SLVS_3P
F30
13
DOUT6
F11
14
SLVS_5P
N30
14
DOUT4
E10
15
PANASONIC_B1N
H30
15
SLVS_6N
D32
16
SLVS_CN
N26
16
SLVS_8N
H28
17
PANASONIC_B1P
H31
17
SLVS_6P
C32
18
SLVS_CP
N27
18
SLVS_8P
H27
19
SLVS_2N
C31
19
SLVS_7N
L29
20
PANASONIC_B0N
J32
20
SLVS_9N
L27
21
SLVS_2P
B32
21
SLVS_7P
K28
22
PANASONIC_B0P
K31
22
SLVS_9P
L26
23
SLVS_4N
E32
23
DOUT11
F14
24
SLVS_0N
D28
24
DOUT9
A11
25
SLVS_4P
F31
25
SIGNAL_TRIGGER
D7
26
SLVS_0P
C28
26
SADDR
F8
27
SLVS_1N
E29
27
RESET_BAR
C7
28
RESERVED
B8
28
SDCLK
E8
29
SLVS_1P
D29
29
OUTPUT_EN_BAR
B7
30
HISPI_SDA
A2
30
SDATA
D8
31
—
—
31
STANDBY
A7
32
HISPI_SCLK
A3
32
OSC_EN
B3
33
GND
—
33
GND
—
34
GND
—
34
GND
—
35
GND
—
35
GND
—
36
GND
—
36
GND
—
37
CN2_VCC
—
37
CN1_VCC
—
38
CN2_VCC
—
38
CN1_VCC
—
39
5V
—
39
5V
—
40
5V
—
40
5V
—
SHIELD1
5V
—
SHIELD1
5V
—
SHIELD2
5V
—
SHIELD2
5V
—

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18 FPGA-EB-02001-1.2
7. Status Indicators
The LED status indicators on the board show power, configuration, and application status. Table 7.1 lists the status LED
I/O map.
Table 7.1. Status LED I/O Map
Device
LED
Net Name
Colour
LFE5UM-85F-BG756
D24
LED1
Green
LFE5UM-85F-BG756
D25
LED2
Green
LFE5UM-85F-BG756
D26
LED3
Green
LFE5UM-85F-BG756
D27
LED4
Green
LFE5UM-85F-BG756
D28
LED5
Green
LFE5UM-85F-BG756
D29
LED6
Green
LFE5UM-85F-BG756
D30
LED7
Green
LFE5UM-85F-BG756
D31
LED8
Green
ispClock5406D
D21
—
Blue
LFE5UM-85F-BG756
D3
FPGA_CSN
Blue
LFE5UM-85F-BG756
D4
FPGA_CSN1
Blue
LFE5UM-85F-BG756
D1
DW_INITN
Blue
LFE5UM-85F-BG756
D2
DW_DONE
Green

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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02001-1.2 19
8. Ordering Information
This board is included as part of a kit, and not available as a separate item. The below part number is for reference only,
so it is clear which board is described in this document. Please visit www.latticesemi.com/boards for the latest ordering
information.
Table 8.1. Reference Part Number
Description
Ordering Part Number
ECP5 VIP Processor Board
LFE5-VIP-P-EVN

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20 FPGA-EB-02001-1.2
References
For more information, refer to:
FPGA-DS-02012 (previously DS1044), ECP5 and ECP5-5G Family Data Sheet
FPGA-UG-02015, Lattice Embedded Vision Development Kit User Guide
FPGA-EB-02002, CrossLink VIP Input Bridge Board
FPGA-EB-02003, HDMI VIP Output Bridge Board
For more information on ispClock, visit
www.latticesemi.com/ispclock
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.