Lauterbach XC800 User manual

MANUAL
Release 09.2021
XC800 Debugger

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XC800 Debugger
TRACE32 Online Help
TRACE32 Directory
TRACE32 Index
TRACE32 Documents ...................................................................................................................... 
ICD In-Circuit Debugger ................................................................................................................ 
Processor Architecture Manuals .............................................................................................. 
XC800 ....................................................................................................................................... 
XC800 Debugger ................................................................................................................... 1
Introduction ....................................................................................................................... 4
Brief Overview of Documents for New Users 4
Warning .............................................................................................................................. 5
Quick Start ......................................................................................................................... 6
Troubleshooting ................................................................................................................ 8
SYStem.Up Errors 8
FAQ ..................................................................................................................................... 8
Configuration ..................................................................................................................... 9
XC800 Specific Implementations ..................................................................................... 10
Breakpoints 10
Software Breakpoints 10
On-chip Breakpoints 10
CPU specific SYStem Settings and Restrictions ........................................................... 11
SYStem.state Open system window 11
SYStem.CONFIG Configure debugger according to target topology 11
Daisy-Chain Example 14
TapStates 15
SYStem.CONFIG.CORE Assign core to TRACE32 instance 16
SYStem.CONFIG.state Display target configuration 17
SYStem.CPU Select CPU 17
SYStem.MemAccess Select memory access mode 18
SYStem.Mode Establish communication with the target 19
SYStem.LOCK Tristate the JTAG port 19
System Options ................................................................................................................. 21
SYStem.Option.IMASKASM Disable interrupts while single stepping 21
SYStem.Option.IMASKHLL Disable interrupts while HLL single stepping 21

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SYStem.Option.LittleEndian Treat memory as little endian 21
SYStem.Option.TRAPEN Change the TRAP_EN bit 22
SYStem.JtagClock Define JTAG clock 23
TrOnchip Commands ........................................................................................................ 24
TrOnchip.CONVert Adjust range breakpoint in on-chip resource 24
TrOnchip.RESet Set on-chip trigger to default state 24
TrOnchip.state Display on-chip trigger window 24
TrOnchip.VarCONVert Adjust complex breakpoint in on-chip resource 25
OCDS1 Connector ............................................................................................................. 26
Memory Classes ................................................................................................................ 28

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XC800 Debugger
Version 04-Nov-2021
Introduction
This document describes the processor specific settings and features for TRACE32-ICD for the
Infineon XC800 CPU family.
Please keep in mind that only the Processor Architecture Manual (the document you are reading at the
moment) is CPU specific, while all other parts of the online help are generic for all CPUs supported by
Lauterbach. So if there are questions related to the CPU, the Processor Architecture Manual should be your
first choice.
Brief Overview of Documents for New Users
Architecture-independent information:
•“Debugger Basics - Training” (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
•“T32Start” (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances
for different configurations of the debugger. T32Start is only available for Windows.
•“General Commands” (general_ref_<x>.pdf): Alphabetic list of debug commands.
Architecture-specific information:
•“Processor Architecture Manuals”: These manuals describe commands that are specific for the
processor architecture supported by your Debug Cable. To access the manual for your processor
architecture, proceed as follows:
- Choose Help menu > Processor Architecture Manual.
•“OS Awareness Manuals” (rtos_<os>.pdf): TRACE32 PowerView can be extended for operating
system-aware debugging. The appropriate OS Awareness manual informs you how to enable the
OS-aware debugging.

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Warning
WARNING: To prevent debugger and target from damage it is recommended to connect or
disconnect the Debug Cable only while the target power is OFF.
Recommendation for the software start:
1. Disconnect the Debug Cable from the target while the target power is
off.
2. Connect the host system, the TRACE32 hardware and the Debug
Cable.
3. Power ON the TRACE32 hardware.
4. Start the TRACE32 software to load the debugger firmware.
5. Connect the Debug Cable to the target.
6. Switch the target power ON.
7. Configure your debugger e.g. via a start-up script.
Power down:
1. Switch off the target power.
2. Disconnect the Debug Cable from the target.
3. Close the TRACE32 software.
4. Power OFF the TRACE32 hardware.

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Quick Start
Starting up the debugger is done as follows:
Select the device prompt for the ICD Debugger and reset the system.
The device prompt B:: is normally already selected in the TRACE32 command line. If this is not the case,
enter B:: to set the correct device prompt. The RESet command is only necessary if you do not start
directly after booting the TRACE32 development tool.
5. Specify the CPU specific settings.
The default values of all other options are set in such a way that it should be possible to work without
modification. Please consider that this is probably not the best configuration for your target.
6. Set up data for electrical interface.
Use the subcommands of MAP to define inaccessible memory areas. Bus errors can be removed by
executing SYStem.Up. Make sure that there isn’t any TRACE32 window open which accesses to a
inaccessible memory that is not masked out, otherwise the bus error can occur again.
7. Enter debug mode.
This command resets the CPU and enters debug mode. After this command is executed, it is possible
to access memory and registers.
8. Load your application program.
The format of the Data.LOAD command depends on the file format generated by the compiler. This
test discovers a problem with the electrical connection, wrong chip configurations or linker command
file settings.
A detailed description of the Data.LOAD command and all available options is given in the “General
Commands Reference”.
B::
SYStem.CPU <cpu_type>
SYStem.JtagClock <frequency>
SYStem.Up
Data.LOAD.OMF myprogram /Verify ; OMF specifies the format,
; myprogram is the file name)

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The start-up can be automated using the programming language PRACTICE. A typical start sequence for
the XC888-8FF is shown below:
b:: ; Select the ICD device prompt
WinCLEAR ; Clear all windows
SYStem.CPU XC888 ; Select CPU
SYStem.Up ; Reset the target and enter debug mode
Data.LOAD.OMF MYPROG /VERFY ; Load the application, verify the
; process
Go main ; Run and break at main()
Data.List ; Open source window
Register.view /SpotLight ; Open register window
Var.Local ; Open window with local variables

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Troubleshooting
SYStem.Up Errors
The SYStem.Up command is the first command of a debug session where communication with the target is
required. If you receive error messages while executing this command this may have the following reasons.
• The JTAG lines are not connected correctly.
• The target has no power.
• The pull-up resistor between the JTAG[VCCS] pin and the target VCC is too large.
• The target is in reset:
The debugger controls the processor reset and use the RESET line to reset the CPU on every
SYStem.Up. Therefore no external R-C combination or external reset controller is allowed.
• There is logic added to the JTAG state machine:
By default the debugger supports only one processor in one JTAG chain. If the processor is only
one member of a JTAG chain the debugger has to be informed about the target JTAG chain
configuration. Use the SYStem.CONFIG command to specify the position of the device in the
JTAG-chain.
• There are additional loads or capacities on the JTAG lines.
FAQ
Please refer to our Frequently Asked Questions page on the Lauterbach website.

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Configuration
The processor type must be selected by the SYStem.CPU command before issuing any other target related
commands.

POWER DEBUG USB INTERFACE / USB 3
POWER DEBUG INTERFACE / USB 3
PC or
Workstation
USB
Cable
Target
Debug
Connector
Debug Cable

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XC800 Specific Implementations
Breakpoints
There are two types of breakpoints available: Software breakpoints and on-chip breakpoints.
Software Breakpoints
Software breakpoints are the default breakpoints for program breakpoints. A software breakpoint is
implemented by patching a break code into the memory.
There is no restriction in the number of software breakpoints.
On-chip Breakpoints
The resources for the on-chip breakpoints are provided by the CPU.
The following list gives an overview of the on-chip breakpoints for the XC800:
•On-chip breakpoints: Total amount of available on-chip breakpoints.
•Instruction breakpoints: Number of on-chip breakpoints that can be used to set Program
breakpoints into ROM/FLASH/EEPROM.
•Read/Write breakpoints: Number of on-chip breakpoints that can be used as Read or Write
breakpoints.
•Data breakpoint: Number of on-chip data breakpoints that can be used to stop the program
when a specific data value is written to an address or when a specific data value is read from an
address.
On-chip
Breakpoints
Instruction
Breakpoints
Read/Write
Breakpoints
Data
Breakpoint
XC800 4 up to 4
up to 1 range
(2 single needed)
up to 1 single
address read or
address range
up to 1 single
address write or
address range
—

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CPU specific SYStem Settings and Restrictions
SYStem.state Open system window
Opens a window with settings of CPU specific system commands. Settings can also be changed here.
SYStem.CONFIG Configure debugger according to target topology
The SYStem.CONFIG commands have no effect in Simulator. These commands describe the physical
configuration at the JTAG port and the trace port of a multi-core hardware target. Since the simulator
normally just simulates the instruction set, these commands will be ignored. Refer to the relevant Processor
Architecture Manual in case you want to know the effect of these commands on a debugger.
The four parameters IRPRE, IRPOST, DRPRE, DRPOST are required to inform the debugger about the
TAP controller position in the JTAG chain, if there is more than one core in the JTAG chain (e.g. Arm + DSP).
The information is required before the debugger can be activated e.g. by a SYStem.Up. See Daisy-chain
Example.
For some CPU selections (SYStem.CPU) the above setting might be automatically included, since the
required system configuration of these CPUs is known.
Format: SYStem.state
Format: SYStem.CONFIG <parameter> <number_or_address>
SYStem.MultiCore <parameter> <number_or_address> (deprecated)
<parameter>:CORE <core>
<parameter>:
(JTAG):
DRPRE <bits>
DRPOST <bits>
IRPRE <bits>
IRPOST <bits>
TAPState <state>
TCKLevel <level>
TriState [ON | OFF]
Slave [ON | OFF]

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TriState has to be used if several debuggers (“via separate cables”) are connected to a common JTAG port
at the same time in order to ensure that always only one debugger drives the signal lines. TAPState and
TCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristate
mode. Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down
resistor, other trigger inputs need to be kept in inactive state.
Multicore debugging is not supported for the DEBUG INTERFACE (LA-7701).
CORE For multicore debugging one TRACE32 PowerView GUI has to be started
per core. To bundle several cores in one processor as required by the
system this command has to be used to define core and processor
coordinates within the system topology.
Further information can be found in SYStem.CONFIG.CORE.
DRPRE (default: 0) <number> of TAPs in the JTAG chain between the core of
interest and the TDO signal of the debugger. If each core in the system
contributes only one TAP to the JTAG chain, DRPRE is the number of
cores between the core of interest and the TDO signal of the debugger.
DRPOST (default: 0) <number> of TAPs in the JTAG chain between the TDI signal
of the debugger and the core of interest. If each core in the system
contributes only one TAP to the JTAG chain, DRPOST is the number of
cores between the TDI signal of the debugger and the core of interest.
IRPRE (default: 0) <number> of instruction register bits in the JTAG chain
between the core of interest and the TDO signal of the debugger. This is
the sum of the instruction register length of all TAPs between the core of
interest and the TDO signal of the debugger.
IRPOST (default: 0) <number> of instruction register bits in the JTAG chain
between the TDI signal and the core of interest. This is the sum of the
instruction register lengths of all TAPs between the TDI signal of the
debugger and the core of interest.
TAPState (default: 7 = Select-DR-Scan) This is the state of the TAP controller when
the debugger switches to tristate mode. All states of the JTAG TAP
controller are selectable.
TCKLevel (default: 0) Level of TCK signal when all debuggers are tristated.

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TriState (default: OFF) If several debuggers share the same debug port, this
option is required. The debugger switches to tristate mode after each
debug port access. Then other debuggers can access the port. JTAG:
This option must be used, if the JTAG line of multiple debug boxes are
connected by a JTAG joiner adapter to access a single JTAG chain.
Slave (default: OFF) If more than one debugger share the same debug port, all
except one must have this option active.
JTAG: Only one debugger - the “master” - is allowed to control the signals
nTRST and nSRST (nRESET).

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Daisy-Chain Example
Below, configuration for core C.
Instruction register length of
• Core A: 3 bit
• Core B: 5 bit
• Core D: 6 bit
SYStem.CONFIG.IRPRE 6. ; IR Core D
SYStem.CONFIG.IRPOST 8. ; IR Core A + B
SYStem.CONFIG.DRPRE 1. ; DR Core D
SYStem.CONFIG.DRPOST 2. ; DR Core A + B
SYStem.CONFIG.CORE 0. 1. ; Target Core C is Core 0 in Chip 1
Core A Core B Core C Core D TDOTDI
Chip 0 Chip 1

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TapStates
0 Exit2-DR
1 Exit1-DR
2 Shift-DR
3 Pause-DR
4 Select-IR-Scan
5 Update-DR
6Capture-DR
7Select-DR-Scan
8 Exit2-IR
9 Exit1-IR
10 Shift-IR
11 Pause-IR
12 Run-Test/Idle
13 Update-IR
14 Capture-IR
15 Test-Logic-Reset

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SYStem.CONFIG.CORE Assign core to TRACE32 instance
Default core_index: depends on the CPU, usually 1. for generic chips
Default chip_index: derived from CORE= parameter of the configuration file (config.t32). The CORE
parameter is defined according to the start order of the GUI in T32Start with ascending values.
To provide proper interaction between different parts of the debugger, the systems topology must be
mapped to the debugger’s topology model. The debugger model abstracts chips and sub cores of these
chips. Every GUI must be connect to one unused core entry in the debugger topology model. Once the
SYStem.CPU is selected, a generic chip or non-generic chip is created at the default chip_index.
Non-generic Chips
Non-generic chips have a fixed number of sub cores, each with a fixed CPU type.
Initially, all GUIs are configured with different chip_index values. Therefore, you have to assign the
core_index and the chip_index for every core. Usually, the debugger does not need further information to
access cores in non-generic chips, once the setup is correct.
Generic Chips
Generic chips can accommodate an arbitrary amount of sub-cores. The debugger still needs information
how to connect to the individual cores e.g. by setting the JTAG chain coordinates.
Start-up Process
The debug system must not have an invalid state where a GUI is connected to a wrong core type of a non-
generic chip, two GUIs are connected to the same coordinate or a GUI is not connected to a core. The initial
state of the system is valid since every new GUI uses a new chip_index according to its CORE= parameter
of the configuration file (config.t32). If the system contains fewer chips than initially assumed, the chips must
be merged by calling SYStem.CONFIG.CORE.
Format: SYStem.CONFIG.CORE <core_index> <chip_index>
SYStem.MultiCore.CORE <core_index><chip_index>(deprecated)
<chip_index>:1…i
<core_index>:1…k

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SYStem.CONFIG.state Display target configuration
Opens the SYStem.CONFIG.state window, where you can view and modify most of the target
configuration settings. The configuration settings tell the debugger how to communicate with the chip on
the target board and how to access the on-chip debug and trace facilities in order to accomplish the
debugger’s operations.
Alternatively, you can modify the target configuration settings via the TRACE32 command line with the
SYStem.CONFIG commands. Note that the command line provides additional SYStem.CONFIG
commands for settings that are not included in the SYStem.CONFIG.state window.
SYStem.CPU Select CPU
Selects the processor type.
Format: SYStem.CONFIG.state [/<tab>]
<tab>: DebugPort | Jtag
<tab> Opens the SYStem.CONFIG.state window on the specified tab:
DebugPort, JTAG.
DebugPort Lets you configure the electrical properties of the debug connection, such
as the communication protocol or the used pinout.
Jtag Informs the debugger about the position of the Test Access Ports (TAP) in
the JTAG chain which the debugger needs to talk to in order to access the
debug and trace facilities on the chip.
Format: SYStem.CPU <cpu>
<cpu>:XC866 | XC866L | XC886 | XC888 | XC886C | XC888C | XC886CM |
XC888CM | XC886LM | XC888LM | XC886CLM | XC888CLM | XC878 |
XC878M | XC878CM | XC878L | XC878C | TC2X_SCR | TLE9832 | TLE9834

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SYStem.MemAccess Select memory access mode
Default: Denied.
Format: SYStem.MemAccess <mode>
<mode>: Enable
Denied
StopAndGo
Enable
CPU (deprecated)
A run-time memory access is made without CPU intervention while the
program is running. This is only possible on the instruction set simulator.
StopAndGo Temporarily halts the core(s) to perform the memory access. Each stop
takes some time depending on the speed of the JTAG port, the number of
the assigned cores, and the operations that should be performed.

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SYStem.Mode Establish communication with the target
SYStem.LOCK Tristate the JTAG port
Default: OFF.
Format: SYStem.Mode <mode>
SYStem.Attach (alias for SYStem.Mode Attach)
SYStem.Down (alias for SYStem.Mode Down)
SYStem.Up (alias for SYStem.Mode Up)
<mode>: Down
NoDebug
Go
Attach
Up
Down The CPU is held in reset, debug mode is not active.
Default state and state after fatal errors.
NoDebug Disables the debugger. The state of the CPU remains unchanged.
The JTAG port is tri-stated.
Go Resets the target and enables the debugger and start the program
execution.
Program execution can be stopped by the break command or if any break
condition occurs.
Attach User program remains running (no reset) and the debug mode is
activated.
After this command the user program can be stopped with the break
command or if any break condition occurs.
Up Resets the target, sets the CPU to debug mode and stops the CPU.
After the execution of this command the CPU is stopped and all register
are set to defaults.
StandBy Not supported.
Format: SYStem.LOCK [ON | OFF]

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If the system is locked, no access to the JTAG port will be performed by the debugger. While locked the
JTAG connector of the debugger is tristated. The intention of the SYStem.LOCK command is, for example,
to give JTAG access to another tool.