Linear Technology LTC2430 User manual

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LTC2430/LTC2431
1
24301f
The LTC
®
2430/LTC2431 are 2.7V to 5.5V micropower
20-bit differential ∆Σanalog-to-digital converters with an
integrated oscillator, 3ppm INL and 0.56ppm RMS noise.
They use delta-sigma technology and provide single cycle
settling time for multiplexed applications. Through a
single pin, the
LTC2430/LTC2431 can be configured for
better than 110dB differential mode rejection at 50Hz or
60Hz ±2%, or they can be driven by an external oscillator
for a user-defined rejection frequency. The internal oscil-
lator requires no external frequency setting components.
The converters accept any external differential reference
voltage from 0.1V to V
CC
for flexible ratiometric and
remote sensing measurement configurations. The full-
scale differential input range is from –0.5V
REF
to 0.5V
REF
.
The reference common mode voltage, V
REFCM
, and the
input common mode voltage, V
INCM
, may be indepen-
dently set anywhere within GND to V
CC
. The DC common
mode input rejection is better than 120dB.
The LTC 2430/LTC2431 communicate through a flexible
3-wire digital interface that is compatible with SPI and
MICROWIRE
TM
protocols.
■
Direct Sensor Digitizer
■
Weight Scales
■
Direct Temperature Measurement
■
Gas Analyzers
■
Strain Gauge Transducers
■
Instrumentation
■
Data Acquisition
■
Industrial Process Control
■
DVMs and Meters
, LTC and LT are registered trademarks of Linear Technology Corporation.
■
Low Supply Current (200µA in Conversion Mode
and 4µA in Autosleep Mode)
■
Differential Input and Differential Reference
with GND to V
CC
Common Mode Range
■
3ppm INL, No Missing Codes
■
10ppm Full-Scale Error and 1ppm Offset
■
0.56ppm Noise, 20.8 ENOBs
■
No Latency: Digital Filter Settles in a Single Cycle.
Each Conversion Is Accurate, Even After an
Input Step
■
Single Supply 2.7V to 5.5V Operation
■
Internal Oscillator—No External Components
Required
■
110dB Min, 50Hz/60Hz Notch Filter
■
Pin Compatible with 24-Bit LTC2410/LTC2411
20-Bit No Latency ∆Σ
TM
ADCs
with Differential Input and
Differential Reference
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
V
CC
F
O
64
12
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
0.1µF
0.1µF
LTC2431
24301 TA01
4.7µF
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
V
CC
LT1790
(V
OUT
+ 0.25V) TO 20V
V
OUT
3V TO 5V
DESCRIPTIO
U
FEATURES
APPLICATIO S
U
TYPICAL APPLICATIO S
U
INPUT VOLTAGE (V)
–2.5
TUE (ppm OF V
REF
)
1
3
5
1.5
24301 G01
–1
–3
0
2
4
–2
–4
–5 –1.5–2 –0.5–1 0.5 1 2
02.5
V
CC
= 5V
V
REF
= 5V
V
INCM
= V
INCM
= 2.5V
F
O
= GND
85°C25°C
–45°C
Total Unadjusted Error
(VCC = 5V, VREF = 5V)

LTC2430/LTC2431
2
24301f
2430
2430I
(Notes 1, 2)
ORDER PART NUMBER
Supply Voltage (V
CC
) to GND.......................–0.3V to 7V
Analog Input Pins Voltage
to GND ......................................... –0.3V to (V
CC
+ 0.3V)
Reference Input Pins Voltage
to GND ......................................... –0.3V to (V
CC
+ 0.3V)
Digital Input Voltage to GND ........ –0.3V to (V
CC
+ 0.3V)
T
JMAX
= 125°C, θ
JA
= 120°C/W
LTC2430CGN
LTC2430IGN
GN PART MARKING
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
1
2
3
4
5
VCC
REF+
REF–
IN+
IN–
10
9
8
7
6
FO
SCK
SDO
CS
GND
TOP VIEW
MS PACKAGE
10-LEAD PLASTIC MSOP
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Digital Output Voltage to GND ..... –0.3V to (V
CC
+ 0.3V)
Operating Temperature Range
LTC2430C/LTC2431C .............................. 0°C to 70°C
LTC2430I/LTC2431I ........................... – 40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
LTXD
LTXE
ORDER PART NUMBER
LTC2431CMS
LTC2431IMS
MS PART MARKING
GN PACKAGE
16-LEAD PLASTIC SSOP
1
2
3
4
5
6
7
8
TOP VIEW
16
15
14
13
12
11
10
9
GND
V
CC
REF
+
REF
–
IN
+
IN
–
GND
GND
GND
GND
F
O
SCK
SDO
CS
GND
GND
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤V
REF
≤V
CC
, –0.5 • V
REF
≤V
IN
≤0.5 • V
REF
(Note 5) ●20 Bits
Integral Nonlinearity 4.5V ≤V
CC
≤5.5V, REF
+
= 2.5V, REF
–
= GND, V
INCM
= 1.25V (Note 6) 2 ppm of V
REF
5V ≤V
CC
≤5.5V, REF
+
= 5V, REF
–
= GND, V
INCM
= 2.5V (Note 6) ●3 20 ppm of V
REF
REF
+
= 2.5V, REF
–
= GND, V
INCM
= 1.25V (Note 6) 10 ppm of V
REF
Offset Error 2.5V ≤REF
+
≤V
CC
, REF
–
= GND, ●520 µV
GND ≤IN
+
= IN
–
≤V
CC
(Note 14)
Offset Error Drift 2.5V ≤REF
+
≤V
CC
, REF
–
= GND, 50 nV/°C
GND ≤IN
+
= IN
–
≤V
CC
Positive Full-Scale Error 2.5V ≤REF
+
≤V
CC
, REF
–
= GND, ●10 20 ppm of V
REF
IN
+
= 0.75REF
+
, IN
–
= 0.25 • REF
+
Positive Full-Scale Error Drift 2.5V ≤REF
+
≤V
CC
, REF
–
= GND, 0.1 ppm of V
REF
/°C
IN
+
= 0.75REF
+
, IN
–
= 0.25 • REF
+
Negative Full-Scale Error 2.5V ≤REF
+
≤V
CC
, REF
–
= GND, ●10 20 ppm of V
REF
IN
+
= 0.25 • REF
+
, IN
–
= 0.75 • REF
+
Negative Full-Scale Error Drift 2.5V ≤REF
+
≤V
CC
, REF
–
= GND, 0.1 ppm of V
REF
/°C
IN
+
= 0.25 • REF
+
, IN
–
= 0.75 • REF
+
Total Unadjusted Error 4.5V ≤V
CC
≤5.5V, REF
+
= 2.5V, REF
–
= GND, V
INCM
= 1.25V 3 ppm of V
REF
5V ≤V
CC
≤5.5V, REF
+
= 5V, REF
–
= GND, V
INCM
= 2.5V 6 ppm of V
REF
REF
+
= 2.5V, REF
–
= GND, V
INCM
= 1.25V 15 ppm of V
REF
Output Noise 5V ≤V
CC
≤5.5V, REF
+
= 5V, V
REF
– = GND, 2.8 µV
RMS
GND ≤IN
–
= IN
+
≤5V, (Note 13)
The ●denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. (Notes 3, 4)
ELECTRICAL CHARACTERISTICS
T
JMAX
= 125°C, θ
JA
= 110°C/W

LTC2430/LTC2431
3
24301f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IN
+
Absolute/Common Mode IN
+
Voltage ●GND – 0.3V V
CC
+ 0.3V V
IN
–
Absolute/Common Mode IN
–
Voltage ●GND – 0.3V V
CC
+ 0.3V V
V
IN
Input Differential Voltage Range ●–V
REF
/2 V
REF
/2 V
(IN
+
– IN
–
)
REF
+
Absolute/Common Mode REF
+
Voltage ●0.1 V
CC
V
REF
–
Absolute/Common Mode REF
–
Voltage ●GND V
CC
– 0.1V V
V
REF
Reference Differential Voltage Range ●0.1 V
CC
V
(REF
+
– REF
–
)
C
S
(IN
+
)IN
+
Sampling Capacitance 1.5 pF
C
S
(IN
–
)IN
–
Sampling Capacitance 1.5 pF
C
S
(REF
+
)REF
+
Sampling Capacitance 1.5 pF
C
S
(REF
–
)REF
–
Sampling Capacitance 1.5 pF
I
DC_LEAK
(IN
+
)IN
+
DC Leakage Current CS = V
CC
, IN
+
= GND ●–10 1 10 nA
I
DC_LEAK
(IN
–
)IN
–
DC Leakage Current CS = V
CC
, IN
–
= V
CC
●–10 1 10 nA
I
DC_LEAK
(REF
+
)REF
+
DC Leakage Current CS = V
CC
, REF
+
= V
CC
●–10 1 10 nA
I
DC_LEAK
(REF
–
)REF
–
DC Leakage Current CS = V
CC
, REF
–
= GND ●–10 1 10 nA
The ●denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Common Mode Rejection DC 2.5V ≤REF
+
≤V
CC
, REF
–
= GND, ●110 120 dB
GND ≤IN
–
= IN
+
≤5V (Note 5)
Input Common Mode Rejection 2.5V ≤REF
+
≤V
CC
, REF
–
= GND, ●140 dB
60Hz ±2% GND ≤IN
–
= IN
+
≤5V, (Notes 5, 7)
Input Common Mode Rejection 2.5V ≤REF
+
≤V
CC
, REF
–
= GND, ●140 dB
50Hz ±2% GND ≤IN
–
= IN
+
≤5V, (Notes 5, 8)
Input Normal Mode Rejection (Notes 5, 7) ●110 140 dB
60Hz ±2%
Input Normal Mode Rejection (Notes 5, 8) ●110 140 dB
50Hz ±2%
Reference Common Mode 2.5V ≤REF
+
≤V
CC
, GND ≤REF
–
≤2.5V, ●130 140 dB
Rejection DC V
REF
= 2.5V, IN
–
= IN
+
= GND (Note 5)
Power Supply Rejection, DC REF
+
= 2.5V, REF
–
= GND, IN
–
= IN
+
= GND 110 dB
Power Supply Rejection, 60Hz ±2% REF
+
= 2.5V, REF
–
= GND, IN
–
= IN
+
= GND, (Note 7) 120 dB
Power Supply Rejection, 50Hz ±2% REF
+
= 2.5V, REF
–
= GND, IN
–
= IN
+
= GND, (Note 8) 120 dB
The ●denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. (Notes 3, 4)
CO VERTER CHARACTERISTICS
U
A ALOG I PUT A D REFERE CE
UU
U
U

LTC2430/LTC2431
4
24301f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
Supply Voltage ●2.7 5.5 V
I
CC
Supply Current
Conversion Mode CS = 0V (Note 12) ●200 300 µA
Sleep Mode CS = V
CC
(Note 12) ●410 µA
Sleep Mode CS = V
CC
, 2.7V ≤V
CC
≤3.3V 2 µA
(Note 12)
The ●denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA= 25°C. (Note 3)
The ●denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA= 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
IH
High Level Input Voltage 2.7V ≤V
CC
≤5.5V ●2.5 V
CS, F
O
2.7V ≤V
CC
≤3.3V 2.0 V
V
IL
Low Level Input Voltage 4.5V ≤V
CC
≤5.5V ●0.8 V
CS, F
O
2.7V ≤V
CC
≤5.5V 0.6 V
V
IH
High Level Input Voltage 2.7V ≤V
CC
≤5.5V (Note 9) ●2.5 V
SCK 2.7V ≤V
CC
≤3.3V (Note 9) 2.0 V
V
IL
Low Level Input Voltage 4.5V ≤V
CC
≤5.5V (Note 9) ●0.8 V
SCK 2.7V ≤V
CC
≤5.5V (Note 9) 0.6 V
I
IN
Digital Input Current 0V ≤V
IN
≤V
CC
●–10 10 µA
CS, F
O
I
IN
Digital Input Current 0V ≤V
IN
≤V
CC
(Note 9) ●–10 10 µA
SCK
C
IN
Digital Input Capacitance 10 pF
CS, F
O
C
IN
Digital Input Capacitance (Note 9) 10 pF
SCK
V
OH
High Level Output Voltage I
O
= –800µA●V
CC
– 0.5V V
SDO
V
OL
Low Level Output Voltage I
O
= 1.6mA ●0.4 V
SDO
V
OH
High Level Output Voltage I
O
= –800µA (Note 10) ●V
CC
– 0.5V V
SCK
V
OL
Low Level Output Voltage I
O
= 1.6mA (Note 10) ●0.4 V
SCK
I
OZ
Hi-Z Output Leakage ●–10 10 µA
SDO
DIGITAL I PUTS A D DIGITAL OUTPUTS
UU
POWER REQUIRE E TS
WU

LTC2430/LTC2431
5
24301f
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF+– REF–, VREFCM = (REF++ REF–)/2;
VIN = IN+– IN–, VINCM = (IN++ IN–)/2.
Note 4: FOpin tied to GND or to VCC or to external conversion clock
source with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is calculated as the measured code minus the
expected value.
Note 7: FO= 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
Note 8: FO= VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FOpin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO= 0V or FO= VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
f
EOSC
External Oscillator Frequency Range ●5 2000 kHz
t
HEO
External Oscillator High Period ●0.25 200 µs
t
LEO
External Oscillator Low Period ●0.25 200 µs
t
CONV
Conversion Time F
O
= 0V ●130.86 133.53 136.20 ms
F
O
= V
CC
●157.03 160.23 163.44 ms
External Oscillator (Note 11) ●20510/f
EOSC
(in kHz) ms
f
ISCK
Internal SCK Frequency Internal Oscillator (Note 10) 19.2 kHz
External Oscillator (Notes 10, 11) f
EOSC
/8 kHz
D
ISCK
Internal SCK Duty Cycle (Note 10) ●45 55 %
f
ESCK
External SCK Frequency Range (Note 9) ●2000 kHz
t
LESCK
External SCK Low Period (Note 9) ●250 ns
t
HESCK
External SCK High Period (Note 9) ●250 ns
t
DOUT_ISCK
Internal SCK 24-Bit Data Output Time Internal Oscillator (Notes 10, 12) ●1.22 1.25 1.28 ms
External Oscillator (Notes 10, 11) ●192/f
EOSC
(in kHz) ms
t
DOUT_ESCK
External SCK 24-Bit Data Output Time (Note 9) ●24/f
ESCK
(in kHz) ms
t
1
CS ↓to SDO Low Z ●0 200 ns
t
2
CS ↑to SDO High Z ●0 200 ns
t
3
CS ↓to SCK ↓(Note 10) ●0 200 ns
t
4
CS ↓to SCK ↑(Note 9) ●50 ns
t
KQMAX
SCK ↓to SDO Valid ●220 ns
t
KQMIN
SDO Hold After SCK ↓(Note 5) ●15 ns
t
5
SCK Set-Up Before CS ↓●50 ns
t
6
SCK Hold After CS ↓●50 ns
The ●denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA= 25°C. (Note 3)
TI I G CHARACTERISTICS
UW

LTC2430/LTC2431
6
24301f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
INPUT VOLTAGE (V)
–2.5
TUE (ppm OF V
REF
)
1
3
5
1.5
24301 G01
–1
–3
0
2
4
–2
–4
–5 –1.5–2 –0.5–1 0.5 1 2
02.5
V
CC
= 5V
V
REF
= 5V
V
INCM
= V
INCM
= 2.5V
F
O
= GND
85°C25°C
–45°C
INPUT VOLTAGE (V)
–1.25
TUE (ppm OF V
REF
)
1
3
5
0.75
24301 G02
–1
–3
0
2
4
–2
–4
–5 –0.75–1 –0.25–0.5 0.25 0.5 1
01.25
V
CC
= 5V
V
REF
= 2.5V
V
INCM
= V
INCM
= 1.25V
F
O
= GND
85°C
–45°C
25°C
INPUT VOLTAGE (V)
–1.25
TUE (ppm OF V
REF
)
20
15
10
5
0
–5
–10
–15
–20
0.75
24301 G03
0.25 1.250.5–1 0 1
V
CC
= 2.7V
V
REF
= 2.5V
V
INCM
= V
INCM
= 1.25V
F
O
= GND
85°C
–45°C
25°C
–0.75 –0.25–0.5
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
INPUT VOLTAGE (V)
–2.5
INL (ppm OF V
REF
)
1
3
5
1.5
24301 G04
–1
–3
0
2
4
–2
–4
–5 –1.5–2 –0.5–1 0.5 1 2
02.5
V
CC
= 5V
V
REF
= 5V
V
INCM
= V
INCM
= 2.5V
F
O
= GND
85°C
25°C
–45°C
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
INPUT VOLTAGE (V)
–1.25
INL (ppm OF V
REF
)
1
3
5
0.75
24301 G05
–1
–3
0
2
4
–2
–4
–5 –1 0.25 0.5 1
01.25
V
CC
= 5V
V
REF
= 2.5V
V
INCM
= V
INCM
= 1.25V
F
O
= GND
85°C
–45°C
25°C
–0.75 –0.25–0.5
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
INPUT VOLTAGE (V)
–1.25
INL (ppm OF V
REF
)
20
15
10
5
0
–5
–10
–15
–20
0.75
24301 G06
0.25 1.250.5–1 0 1
V
CC
= 2.7V
V
REF
= 2.5V
V
INCM
= V
INCM
= 1.25V
F
O
= GND
85°C
–45°C
25°C
–0.75 –0.25–0.5
Noise Histogram (Output Rate =
7.5Hz, VCC = 5V, VREF = 5V)
OUTPUT CODE (ppm OF VREF)
–2.5
NUMBER OF READINGS (%)
40
35
30
25
20
15
10
5
0
1.5
24301 G07
–1.5 –0.5 0.5 2.51–2 –1 0 2
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
VINCM = 2.5V
FO= GND
TA= 25°C
GAUSSIAN
DISTRIBUTION
m = –0.25ppm
σ= 0.550ppm
Noise Histogram (Output Rate =
7.5Hz, VCC = 2.7V, VREF = 2.5V)
OUTPUT CODE (ppm OF V
REF
)
–4
NUMBER OF READINGS (%)
12
16
20
4
24301 G08
8
4
10
14
18
6
2
0–2–3 0–1 23 5
16
10,000 CONSECUTIVE
READINGS
V
CC
= 2.7V
V
REF
= 2.5V
V
IN
= 0V
V
INCM
= 2.5V
F
O
= GND
T
A
= 25°C
GAUSSIAN
DISTRIBUTION
m = –1.07ppm
σ= 1.06ppm
RMS Noise
vs Input Differential Voltage
INPUT DIFFERENTIAL VOLTAGE (V)
–2.5
RMS NOISE (ppm OF V
REF
)
0.6
0.8
1.0
1.5
24301 G10
0.4
0.2
0.5
0.7
0.9
0.3
0.1
0–1.5–2 –0.5–1 0.5 1 2
02.5
V
CC
= 5V
V
REF
= 5V
V
INCM
= 2.5V
F
O
= GND
T
A
= 25°C

LTC2430/LTC2431
7
24301f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
RMS Noise vs VINCM RMS Noise vs Temperature (TA)
V
INCM
(V)
–1 0
2.4
RMS NOISE (µV)
2.8
3.4
134
24301 G11
2.6
3.2
3.0
256
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
V
IN
= 0V
V
INCM
= GND
F
O
= GND
T
A
= 25°C
TEMPERATURE (°C)
–50
2.4
RMS NOISE (µV)
2.6
2.8
3.0
3.2
3.4
–25 02550
24301 G12
75 100
VCC = 5V
VREF = 5V
VIN = 0V
VINCM = GND
FO= GND
RMS Noise vs VCC
V
CC
(V)
2.7 3.1
2.4
RMS NOISE (µV)
2.8
3.4
3.5 4.3 4.7
24301 G13
2.6
3.2
3.0
3.9 5.1 5.5
REF
+
= 2.5V
REF
–
= GND
V
IN
= 0V
V
INCM
= GND
F
O
= GND
T
A
= 25°C
RMS Noise vs VREF
V
REF
(V)
0
RMS NOISE (µV)
3.0
3.2
3.4
4
24301 G14
2.8
2.6
2.4 1235
V
CC
= 5V
REF
–
= GND
V
IN
= 0V
V
INCM
= GND
F
O
= GND
T
A
= 25°C
Offset Error vs VINCM
V
INCM
(V)
–1
–1.0
OFFSET ERROR (ppm OF V
REF
)
–0.8
–0.4
–0.2
0
1.0
0.4
134
24301 G15
–0.6
0.6
0.8
0.2
0256
V
CC
= 5V
REF
+
= 5V
REF
–
= GND
V
IN
= 0V
F
O
= GND
T
A
= 25°C
Offset Error vs Temperature
Offset Error vs VREF
TEMPERATURE (°C)
–45
–1.0
OFFSET ERROR (ppm OF V
REF
)
–0.8
–0.4
–0.2
0
1.0
0.4
–15 15 30 90
24301 G16
–0.6
0.6
0.8
0.2
–30 0 45 60 75
V
CC
= 5V
V
REF
=5V
V
IN
= 0V
V
INCM
= GND
F
O
= GND
Offset Error vs VCC
V
CC
(V)
2.7
–1.0
OFFSET ERROR (ppm OF V
REF
)
–0.8
–0.4
–0.2
0
1.0
0.4
3.5 4.3 4.7
24301 G17
–0.6
0.6
0.8
0.2
3.1 3.9 5.1 5.5
REF
+
= V
CC
REF
–
= GND
V
IN
= 0V
V
INCM
= GND
F
O
= GND
T
A
= 25°C
V
REF
(V)
0
OFFSET ERROR (ppm OF V
REF
)
1
3
5
4
24301 G18
–1
–3
0
2
4
–2
–4
–5 1235
V
CC
= 5V
REF
–
= GND
V
IN
= 0V
V
INCM
= GND
F
O
= GND
T
A
= 25°C
Full-Scale Error vs Temperature
TEMPERATURE (°C)
–45
–20
FULL-SCALE ERROR (ppm OF V
REF
)
–10
0
10
20
–30 –15 0 15
24301 G19
30 45 60 75 90
+FS ERROR
–FS ERROR
V
CC
= 5V
V
REF
= 5V
F
O
= GND
V
INCM
= 2.5V

LTC2430/LTC2431
8
24301f
TYPICAL PERFOR A CE CHARACTERISTICS
UW
PSRR vs Frequency at VCC
Conversion Current vs Temperature
Full-Scale Error vs VREF
VREF (V)
0
FULL-SCALE ERROR (ppm OF VREF)
20
15
10
5
0
–5
–10
–15
–20
4
24301 G20
123 53.50.5 1.5 2.5 4.5
+FS ERROR
–FS ERROR
VCC = 5V
REF–= GND
FO= GND
VINCM = 0.5VREF
TA= 25°C
Full-Scale Error vs VCC
V
CC
(V)
2.7
–5
FULL-SCALE ERROR (ppm OF V
REF
)
–4
–2
–1
0
5
2
3.5 4.3 4.7
24301 G21
–3
3
4
1
3.1 3.9 5.1 5.5
+FS ERROR
–FS ERROR
V
REF
= 2.5V
REF
–
= GND
F
O
= GND
V
INCM
= 0.5V
REF
T
A
= 25°C
FREQUENCY AT V
CC
(Hz)
0
–140
REJECTION (dB)
–120
–80
–60
–40
0
20 100 140
24301 G22
–100
–20
80 180 220200
40 60 120 160
V
CC
= 4.1V
DC
±1.4V
REF
+
= 2.5V
REF
–
= GND
IN
+
= GND
IN
–
= GND
F
O
= GND
T
A
= 25°C
PSRR vs Frequency at VCC PSRR vs Frequency at VCC
FREQUENCY AT V
CC
(Hz)
15170
–60
–40
0
15320
24301 G24
–80
–100
15220 15270 15370
–120
–140
–20
REJECTION (dB)
V
CC
= 4.1V
DC
±0.7V
REF
+
= 2.5V
REF
–
= GND
IN
+
= GND
IN
–
= GND
F
O
= GND
T
A
= 25°C
TEMPERATURE (°C)
–45
CONVERSION CURRENT (µA)
200
210
220
75
24301 G25
190
180
160 –15 15 45–30 9003060
170
240
230 V
CC
= 5.5V
V
CC
= 2.7V
V
CC
= 5V
V
CC
= 3V
F
O
= GND
CS = GND
SCK = NC
SDO = NC
Conversion Current
vs Output Data Rate
OUTPUT DATA RATE (READINGS/SEC)
0
100
SUPPLY CURRENT (µA)
200
400
500
600
60 70 80 90
1000
24301 G26
300
10 20 30 40 50 100
700
800
900 V
CC
= 5V
V
CC
= 3V
V
REF
= V
CC
IN
+
= GND
IN
–
= GND
SCK = NC
SDO = NC
SDI = GND
CS = GND
F
O
= EXT OSC
T
A
= 25°C
Sleep Mode Current
vs Temperature
TEMPERATURE (°C)
–45
0
SLEEP MODE CURRENT (µA)
1
3
4
5
–15 15 30 90
24301 G27
2
–30 0 45 60 75
6
V
CC
= 5.5V
V
CC
= 2.7V
V
CC
= 5V
V
CC
= 3V
F
O
= GND
CS = V
CC
SCK = NC
SDO = NC
FREQUENCY AT V
CC
(Hz)
1
0
–20
–40
–60
–80
–100
–120
–140 1k 100k
24301 G23
10 100 10k 1M
REJECTION (dB)
V
CC
= 4.1V
DC
REF
+
= 2.5V
REF
–
= GND
IN
+
= GND
IN
–
= GND
F
O
= GND
T
A
= 25°C

LTC2430/LTC2431
9
24301f
V
CC
(Pin 1): Positive Supply Voltage. Bypass to GND
(Pin␣ 6) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
REF
+
(Pin 2), REF
–
(Pin 3): Differential Reference Input.
The voltage on these pins can have any value between GND
and V
CC
as long as the reference positive input, REF
+
, is
maintained more positive than the reference negative
input, REF
–
, by at least 0.1V.
IN
+
(Pin 4), IN
–
(Pin 5): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and V
CC
+ 0.3V. Within these limits, the
converter bipolar input range (V
IN
= IN
+
– IN
–
) extends
from –0.5 • (V
REF
) to 0.5 • (V
REF
). Outside this input
range, the converter produces unique overrange and
underrange output codes.
GND (Pin 6): Ground. Connect this pin to a ground plane
through a low impedance connection.
CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
UU
U
PI FU CTIO S
GND (Pins 1, 7, 8, 9, 10, 15, 16): Ground. Multiple ground
pins internally connected for optimum ground current flow
and V
CC
decoupling. Connect each one of these pins to a
ground plane through a low impedance connection. All seven
pins must be connected to ground for proper operation.
V
CC
(Pin 2): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with 0.1µF ceramic
capacitor as close to the part as possible.
REF
+
(Pin 3), REF
–
(Pin 4): Differential Reference Input.
The voltage on these pins can have any value between GND
and V
CC
as long as the reference positive input, REF
+
, is
maintained more positive than the reference negative
input, REF
–
, by at least 0.1V.
IN
+
(Pin 5), IN
–
(Pin 6): Differential Analog Input. The
voltage on these pins can have any value between
GND – 0.3V and V
CC
+ 0.3V. Within these limits the
converter bipolar input range (V
IN
= IN
+
– IN
–
) extends
from –0.5 • (V
REF
) to 0.5 • (V
REF
). Outside this input range
the converter produces unique overrange and underrange
output codes.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = V
CC
) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output.
The conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as digital input for the external serial interface
clock during the Data Output period. A weak internal pull-
up is automatically activated in Internal Serial Clock Op-
eration mode. The Serial Clock Operation mode is deter-
mined by the logic level applied to the SCK pin at power up
or during the most recent falling edge of CS.
F
O
(Pin 14): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the F
O
pin is connected to V
CC
(F
O
= V
CC
), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the F
O
pin is connected
to GND (F
O
= OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When F
O
is driven by an external clock signal with a frequency f
EOSC
,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency f
EOSC
/2560.
(LTC2430)
(LTC2431)

LTC2430/LTC2431
10
24301f
Figure 1
UU
W
FU CTIO AL BLOCK DIAGRA
AUTOCALIBRATION
AND CONTROL
DAC
DECIMATING FIR
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
ADC
∑
∫∫∫
GND
V
CC
IN
+
IN
–
SDO
SCK
REF
+
REF
–
CS
F
O
(INT/EXT)
2431 FD
+
–
TEST CIRCUITS
1.69k
SDO
2431 TA03
Hi-Z TO V
OH
V
OL
TO V
OH
V
OH
TO Hi-Z
C
LOAD
= 20pF
1.69k
SDO
2431 TA04
Hi-Z TO V
OL
V
OH
TO V
OL
V
OL
TO Hi-Z
C
LOAD
= 20pF
V
CC
SDO (Pin 8): Three-State Digital Output. During the Data
Output period, this pin is used as the serial data output.
When the chip select CS is HIGH (CS = V
CC
), the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods, this pin is used as the conversion status
output. The conversion status can be observed by pulling
CS LOW.
SCK (Pin 9): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as the digital
output for the internal serial interface clock during the Data
Output period. In External Serial Clock Operation mode,
SCK is used as the digital input for the external serial
interface clock during the Data Output period. A weak
internal pull-up is automatically activated in Internal Serial
Clock Operation mode. The Serial Clock Operation mode is
determined by the logic level applied to the SCK pin at
power up or during the most recent falling edge of CS.
F
O
(Pin 10): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the F
O
pin is connected to V
CC
(F
O
= V
CC
), the
converter uses its internal oscillator and the digital filter
first null is located at 50Hz. When the F
O
pin is connected
to GND (F
O
= OV), the converter uses its internal oscillator
and the digital filter first null is located at 60Hz. When F
O
is driven by an external clock signal with a frequency f
EOSC
,
the converter uses this signal as its system clock and the
digital filter first null is located at a frequency f
EOSC
/2560.
UU
U
PI FU CTIO S
(LTC2431)

LTC2430/LTC2431
11
24301f
CONVERTER OPERATION
Converter Operation Cycle
The LTC2430/LTC2431 are low power, delta-sigma analog-
to-digital converters with an easy-to-use 3-wire serial inter-
face(seeFigure1).Theiroperationismadeupofthreestates.
The converters’ operating cycle begins with the conversion,
followed by the low power sleep state and ends with the data
output (see Figure 2). The 3-wire interface consists of serial
data output (SDO), serial clock (SCK) and chip select (CS).
Initially, the LTC2430/LTC2431 perform a conversion.
Once the conversion is complete, the device enters the
sleep state. The part remains in the sleep state as long as
CS is HIGH. While in this sleep state, power consumption
is reduced by nearly two orders of magnitude. The conver-
sion result is held indefinitely in a static shift register while
the converter is in the sleep state.
OnceCS is pulled LOW,thedevice exits thelowpower mode
and enters the data output state. If CS is pulled HIGH be-
fore the first rising edge of SCK, the device returns to the
lowpower sleepmode and theconversion result is still held
in the internal static shift register. If CS remains LOW after
the first rising edge of SCK, the device begins outputting
the conversion result. Taking CS high at this point will
terminate the data output state and start a new conversion.
There is no latency in the conversion result. The data out-
put corresponds to the conversion just performed. This
result is shifted out on the serial data out pin (SDO) under
the control of the serial clock (SCK). Data is updated on the
falling edge of SCK allowing the user to reliably latch data
on the rising edge of SCK (see Figure 3). The data output
state is concluded once 24 bits are read out of the ADC or
whenCS is brought HIGH.Thedevice automatically initiates
a new conversion and the cycle repeats.
Through timing control of the CS and SCK pins, the
LTC2430/LTC2431 offer several flexible modes of
operation (internal or external SCK and free-running
conversion modes). These various modes do not require
programming configuration registers; moreover, they do
not disturb the cyclic operation described above. These
modes of operation are described in detail in the Serial
Interface Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz or
60Hz plus their harmonics. The filter rejection perfor-
mance is directly related to the accuracy of the converter
system clock. The LTC2430/LTC2431 incorporate a highly
accurate on-chip oscillator. This eliminates the need for
external frequency setting components such as crystals or
oscillators.Clocked bythe on-chip oscillator,the LTC2430/
LTC2431 achieve a minimum of 110dB rejection at the line
frequency (50Hz or 60Hz ±2%).
Ease of Use
The LTC2430/LTC2431 data output has no latency, filter
settling delay or redundant data associated with the
conversion cycle. There is a one-to-one correspondence
between the conversion and the output data. Therefore,
multiplexing multiple analog inputs is easy.
The LTC2430/LTC2431 perform offset and full-scale cali-
brationsin every conversioncycle. This calibrationis trans-
parent to the user and has no effect on the cyclic operation
described above. The advantage of continuous calibration
is extreme stability of offset and full-scale readings with
respect to time, supply voltage change and temperature
drift.
Figure 2. LTC2430/LTC2431 State Transition Diagram
CONVERT
SLEEP
DATA OUTPUT
2431 F02
TRUE
FALSE CS = LOW
AND
SCK
APPLICATIO S I FOR ATIO
WUUU

LTC2430/LTC2431
12
24301f
Power-Up Sequence
The LTC2430/LTC2431 automatically enter an internal
reset state when the power supply voltage V
CC
drops
below approximately 2V. This feature guarantees the
integrity of the conversion result and of the serial interface
mode selection. (See the 2-wire I/O sections in the Serial
Interface Timing Modes section.)
When the VCC voltage rises above this critical threshold,
the LTC2430 or LTC2431 creates an internal power-on-
reset (POR) signal with a duration of approximately 1ms.
The POR signal clears all internal registers. Following the
POR signal, the converter starts a normal conversion
cycle and follows the succession of states described
above. The first conversion result following POR is accu-
rate within the specifications of the device if the power
supply voltage is restored within the operating range
(2.7V to 5.5V) before the end of the POR time interval.
Reference Voltage Range
The LTC2430/LTC2431 accept a differential external refer-
ence voltage. The absolute/common mode voltage speci-
fication for the REF
+
and REF
–
pins covers the entire range
from GND to V
CC
. For correct converter operation, the
REF
+
pin must always be more positive than the REF
–
pin.
The LTC2430/LTC2431 can accept a differential reference
voltage from 0.1V to V
CC
. The converter (LTC2430 or
LTC2431) output noise is determined by the thermal noise
of the front-end circuits, and, as such, its value in micro-
volts is nearly constant with reference voltage. A decrease
in reference voltage will not significantly improve the
converter’s effective resolution. On the other hand, a re-
duced reference voltage will improve the converter’s over-
all INL performance. A reduced reference voltage will also
improve the converter performance when operated with
an external conversion clock (external F
O
signal) at sub-
stantially higher output data rates.
Input Voltage Range
The analog input is truly differential with an absolute/com-
mon mode range for the IN
+
and IN
–
input pins extending
from GND – 0.3V to V
CC
+ 0.3V. Outside these limits, the
ESD protection devices begin to turn on and the errors due
to input leakage current increase rapidly. Within these lim-
its, the LTC2430 or LTC2431 converts the bipolar differen-
tial input signal, V
IN
= IN
+
– IN
–
, from –FS = –0.5 • V
REF
to +FS = 0.5 • V
REF
where V
REF
= REF
+
– REF
–
. Outside this
range the converter indicates the overrange or the
underrange condition using distinct output codes.
Input signals applied to IN
+
and IN
–
pins may extend by
300mV below ground and above V
CC
. In order to limit any
fault current, resistors of up to 5k may be added in series
withthe IN
+
and IN
–
pins withoutaffecting the performance
of the device. In the physical layout, it is important to main-
tain the parasitic capacitance of the connection between
these series resistors and the corresponding pins as low
as possible; therefore, the resistors should be located as
close as practical to the pins. In addition, series resistors
will introduce a temperature dependent offset error due to
the input leakage current. A 1nA input leakage current will
develop a 1ppm offset error on a 5k resistor if V
REF
= 5V.
This error has a very strong temperature dependency.
Output Data Format
The LTC2430/LTC2431 serial output data stream is 24 bits
long. The first 3 bits represent status information indicat-
ing the sign and conversion state. The next 21 bits are the
conversion result, MSB first. The third and fourth bits to-
gether are also used to indicate an underrange condition
(thedifferential input voltage is below–FS) or anoverrange
condition (the differential input voltage is above +FS).
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW.
Bit 20 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 21 also
provides the underrange or overrange indication. If both
Bit 21 and Bit 20 are HIGH, the differential input voltage is
APPLICATIO S I FOR ATIO
WUUU

LTC2430/LTC2431
13
24301f
above +FS. If both Bit 21 and Bit 20 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2430/LTC2431 Status Bits
Bit 23 Bit 22 Bit 21 Bit 20
Input Range EOC DMY SIG MSB
V
IN
≥0.5 • V
REF
0011
0V ≤V
IN
< 0.5 • V
REF
0010
–0.5 • V
REF
≤V
IN
< 0V 0 0 0 1
V
IN
< – 0.5 • V
REF
0000
Bits 20-0 are the 21-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 23 (EOC) can be captured on the first rising
edge of SCK. Bit 22 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 23rd SCK and may be latched on
the rising edge of the 24th SCK pulse. On the falling edge
of the 24th SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 22) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the IN
+
and IN
–
pins is maintained
within the –0.3V to (V
CC
+ 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage V
IN
from –FS = –0.5 • V
REF
to
+FS = 0.5 • V
REF
. For differential input voltages greater than
Table 2. LTC2430/LTC2431 Output Data Format
Differential Input Voltage Bit 23 Bit 22 Bit 21 Bit 20 Bit 19 Bit 18 Bit 17 … Bit 0
V
IN
* EOC DMY SIG MSB LSB
V
IN
* ≥0.5 • V
REF
** 00110 0 0…0
0.5 • V
REF
**–1LSB 00101 1 1…1
0.25 • V
REF
** 00101 0 0…0
0.25 • V
REF
**–1LSB 00100 1 1…1
0 00100 0 0…0
–1LSB 0 0011 1 1…1
–0.25 • V
REF
** 00011 0 0…0
–0.25 • V
REF
**–1LSB 00010 1 1…1
–0.5 • V
REF
** 00010 0 0…0
V
IN
* < –0.5 • V
REF
** 00001 1 1…1
*The differential input voltage V
IN
= IN
+
– IN
–
.
**The differential reference voltage V
REF
= REF
+
– REF
–
.
Figure 3. Output Data Timing
MSBSIG“0”
1234524
BIT 0
LSB
BIT 19BIT 20BIT 21BIT 22
SDO
SCK
CS
EOC
BIT 23
SLEEP DATA OUTPUT CONVERSION
2431 F03
Hi-Z
APPLICATIO S I FOR ATIO
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LTC2430/LTC2431
14
24301f
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Frequency Rejection Selection (F
O
)
The LTC2430/LTC2431 internal oscillator provides better
than 110dB normal mode rejection at the line frequency
and all its harmonics for 50Hz ±2% or 60Hz ±2%. For
60Hz rejection, F
O
should be connected to GND while for
50Hz rejection the F
O
pin should be connected to V
CC
.
The selection of 50Hz or 60Hz rejection can also be made
by driving F
O
to an appropriate logic level. A selection
change during the sleep or data output states will not
disturb the converter operation. If the selection is made
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected.
When a fundamental rejection frequency different from
50Hz or 60Hz is required or when the converter must be
synchronized with an outside source, the LTC2430 or
LTC2431 can operate with an external conversion clock.
The converter automatically detects the presence of an
external clock signal at the F
O
pin and turns off the internal
oscillator. The frequency f
EOSC
of the external signal must
be at least 5kHz to be detected. The external clock signal
duty cycle is not significant as long as the minimum and
maximum specifications for the high and low periods t
HEO
and t
LEO
are observed.
While operating with an external conversion clock of a
frequency f
EOSC
, the LTC2430 or LTC2431 provides better
than 110dB normal mode rejection in a frequency range
f
EOSC
/2560 ±4% and its harmonics. The normal mode
rejection as a function of the input frequency deviation
from f
EOSC
/2560 is shown in Figure 4.
Whenever an external clock is not present at the F
O
pin, the
converter (LTC2430 or LTC2431) automatically activates
its internal oscillator and enters the Internal Conversion
Clock mode. Its operation will not be disturbed if the
change of conversion clock source occurs during the
sleep state or during the data output state while the con-
verter uses an external serial clock. If the change occurs
during the conversion state, the result of the conversion in
progress may be outside specifications but the following
conversions will not be affected. If the change occurs
during the data output state and the converter is in the
Internal SCK mode, the serial clock duty cycle may be
affected but the serial data stream will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of F
O
.
SERIAL INTERFACE PINS
The LTC2430/LTC2431 transmit the conversion results
and receives the start of conversion command through a
synchronous 3-wire interface. During the conversion and
sleep states, this interface can be used to assess the
converter status and during the data output state it is used
to read the conversion result.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK is used to synchro-
nize the data transfer. Each bit of data is shifted out the
SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the converter (LTC2430 or LTC2431) creates
itsown serial clockbydividing the internalconversion clock
by 8. In the External SCK mode of operation, the SCK pin
is used as input. The internal or external SCK mode is
selected on power-up and then reselected every time a
HIGH-to-LOW transition is detected at the CS pin. If SCK
Figure 4. LTC2430/LTC2431 Normal Mode Rejection When
Using an External Oscillator of Frequency fEOSC
APPLICATIO S I FOR ATIO
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DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY f
EOSC
/2560(%)
–12–8–404812
NORMAL MODE REJECTION (dB)
2431 F04
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140

LTC2430/LTC2431
15
24301f
Table 3. LTC2430/LTC2431 State Duration
State Operating Mode Duration
CONVERT Internal Oscillator F
O
= LOW 133ms, Output Data Rate ≤7.5 Readings/s
(60Hz Rejection)
F
O
= HIGH 160ms, Output Data Rate ≤6.2 Readings/s
(50Hz Rejection)
External Oscillator F
O
= External Oscillator 20510/f
EOSC
s, Output Data Rate ≤f
EOSC
/20510 Readings/s
with Frequency f
EOSC
kHz
(f
EOSC
/2560 Rejection)
SLEEP As Long As CS = HIGH
DATA OUTPUT Internal Serial Clock F
O
= LOW/HIGH As Long As CS = LOW But Not Longer Than 1.25ms
(Internal Oscillator) (24 SCK cycles)
F
O
= External Oscillator with As Long As CS = LOW But Not Longer Than 192/f
EOSC
ms
Frequency f
EOSC
kHz (24 SCK cycles)
External Serial Clock with As Long As CS = LOW But Not Longer Than 24/f
SCK
ms
Frequency f
SCK
kHz (24 SCK cycles)
isHIGH orfloating at power-upor during thistransition, the
converter enters the internal SCK mode. If SCK is LOW at
power-up or during this transition, the converter enters the
external SCK mode.
Serial Data Output (SDO)
The serial data output pin, SDO, provides the result of the
last conversion as a serial bit stream (MSB first) during the
data output state. In addition, the SDO pin is used as an end
of conversion indicator during the conversion and sleep
states.
When CS is HIGH, the SDO driver is switched to a high
impedance state. This allows sharing the serial interface
with other devices. If CS is LOW during the convert or
sleep state, SDO will output EOC. If CS is LOW during the
conversion phase, the EOC bit appears HIGH on the SDO
pin. Once the conversion is complete, EOC goes LOW.
Chip Select Input (CS)
The active LOW chip select, CS, is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The converter (LTC2430 or LTC2431)
will abort any serial data transfer in progress and start a
new conversion cycle anytime a LOW-to-HIGH transition
is detected at the CS pin after the converter has entered the
data output state (i.e., after the first rising edge of SCK
occurs with CS␣ =␣ LOW).
Finally, CS can be used to control the free-running modes
of operation, see Serial Interface Timing Modes section.
Grounding CS will force the ADC to continuously convert
at the maximum output rate selected by FO.
SERIAL INTERFACE TIMING MODES
The LTC2430/LTC2431’s 3-wire interface is SPI and
MICROWIRE compatible. This interface offers several
flexible modes of operation. These include internal/exter-
nal serial clock, 2- or 3-wire I/O, single cycle conversion.
The following sections describe each of these serial inter-
face timing modes in detail. In all these cases, the
converter can use the internal oscillator (F
O
= LOW or F
O
= HIGH) or an external oscillator connected to the F
O
pin.
Refer to Table␣ 4 for a summary.
External Serial Clock, Single Cycle Operation
(SPI/MICROWIRE Compatible)
This timing mode uses an external serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 5.
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LTC2430/LTC2431
16
24301f
EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
TEST EOC
LSBMSBSIG
BIT 0BIT 19 BIT 18BIT 20BIT 21BIT 22
SLEEP SLEEP
TEST EOC
DATA OUTPUT CONVERSION
2431 F05
CONVERSION
Hi-ZHi-ZHi-Z
TEST EOC
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
1µF
2.7V TO 5.5V
LTC2430/
LTC2431
3-WIRE
SPI INTERFACE
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
TEST EOC
Table 4. LTC2430/LTC2431 Interface Timing Modes
Conversion Data Connection
SCK Cycle Output and
Configuration Source Control Control Waveforms
External SCK, Single Cycle Conversion External CS and SCK CS and SCK Figures 5, 6
External SCK, 2-Wire I/O External SCK SCK Figure 7
Internal SCK, Single Cycle Conversion Internal CS ↓CS ↓Figures 8, 9
Internal SCK, 2-Wire I/O, Continuous Conversion Internal Continuous Internal Figure 10
The serial clock mode is selected on the falling edge of CS.
To select the external serial clock mode, the serial clock pin
(SCK) must be LOW during each CS falling edge.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC␣ =␣ 1 while a conversion is in progress and EOC = 0 if
the conversion is over. With CS HIGH, the device auto-
matically enters the low power sleep state once the con-
version is complete.
When CS is low, the device enters the data output mode.
The result is held in the internal static shift register until
the first SCK rising edge is seen while CS is LOW. Data is
shifted out the SDO pin on each falling edge of SCK. This
enables external circuitry to latch the output on the rising
edge of SCK. EOC can be latched on the first rising edge
of SCK and the last bit of the conversion result can be
latched on the 24th rising edge of SCK. On the 24th falling
edge of SCK, the device begins a new conversion. SDO
goesHIGH (EOC =1) indicating aconversionis in progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the 24th
falling edge of SCK, see Figure 6. On the rising edge of CS,
APPLICATIO S I FOR ATIO
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Figure 5. External Serial Clock, Single Cycle Operation

LTC2430/LTC2431
17
24301f
EOC␣ =␣ 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. Data is shifted out the SDO pin on each
falling edge of SCK enabling external circuitry to latch data
on the rising edge of SCK. EOC can be latched on the first
rising edge of SCK. On the 24th falling edge of SCK, SDO
goes HIGH (EOC␣ =␣ 1) indicating a new conversion has
begun.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and
control the state of the conversion cycle, see Figure 8.
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be floating (Hi-Z) or pulled
HIGH prior to the falling edge of CS. The device will not
enter the internal serial clock mode if SCK is driven LOW
on the falling edge of CS. An internal weak pull-up resistor
is active on the SCK pin during the falling edge of CS;
therefore, the internal serial clock timing mode is auto-
matically selected if SCK is not externally driven.
Figure 6. External Serial Clock, Reduced Data Output Length
APPLICATIO S I FOR ATIO
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SDO
SCK
(EXTERNAL)
CS
DATA
OUTPUT
CONVERSION
SLEEP
SLEEP
SLEEP
TEST EOC
(OPTIONAL)
TEST EOC
DATA OUTPUT
Hi-Z Hi-ZHi-Z
CONVERSION
2431 F06
MSBSIG
BIT 8BIT 19 BIT 9BIT 20BIT 21BIT 22
EOC
BIT 23BIT 0
EOC
Hi-Z
TEST EOC
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
1µF
2.7V TO 5.5V
LTC2430/
LTC2431
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
the device aborts the data output state and immediately
initiates a new conversion. This is useful for systems not
requiring all 24 bits of output data, aborting an invalid con-
version cycle or synchronizing the start of a conversion.
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an exter-
nally generated serial clock (SCK) signal, see Figure 7. CS
may be permanently tied to ground, simplifying the user
interface or isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V
CC
exceeds 2V. The level applied
to SCK at this time determines if SCK is internal or external.
SCK must be driven LOW prior to the end of POR in order
to enter the external serial clock timing mode.
Since CS is tied LOW, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the convert
and sleep states. EOC may be used as an interrupt to an
external controller indicating the conversion result is
ready. EOC = 1 while the conversion is in progress and

LTC2430/LTC2431
18
24301f
Figure 7. External Serial Clock, CS = 0 Operation
Figure 8. Internal Serial Clock, Single Cycle Operation
APPLICATIO S I FOR ATIO
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EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
MSBSIG
BIT 0
LSB
BIT 19 BIT 18BIT 20BIT 21BIT 22
DATA OUTPUT CONVERSION
2431 F07
CONVERSION
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
2-WIRE I/O
1µF
2.7V TO 5.5V
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
LTC2430/
LTC2431
SDO
SCK
(INTERNAL)
CS
MSBSIG
BIT 0
LSB
TEST EOC
BIT 19 BIT 18BIT 20BIT 21BIT 22
EOC
BIT 23
SLEEP
SLEEP
TEST EOC
(OPTIONAL)
DATA OUTPUT CONVERSIONCONVERSION
2431 F08
<tEOCtest
VCC
10k
Hi-Z Hi-Z Hi-Z Hi-Z
VCC FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
3-WIRE
SPI INTERFACE
1µF
2.7V TO 5.5V
LTC2430/
LTC2431
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
TEST EOC

LTC2430/LTC2431
19
24301f
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
Once CS is pulled LOW, SCK goes LOW and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the sleep state and enter the data output
state if CS remains LOW. In order to allow the device to
return to the low power sleep state, CS must be pulled
HIGH before the first rising edge of SCK. In the internal
SCK timing mode, SCK goes HIGH and the device begins
outputting data at time t
EOCtest
after the falling edge of CS
(if EOC = 0) or t
EOCtest
after EOC goes LOW (if CS is LOW
during the falling edge of EOC). The value of t
EOCtest
is 23µs
if the device is using its internal oscillator (F
O
= logic LOW
or HIGH). If F
O
is driven by an external oscillator of
frequency f
EOSC
, then t
EOCtest
is 3.6/f
EOSC
. If CS is pulled
HIGH before time t
EOCtest
, the device returns to the sleep
state. The conversion result is held in the internal static
shift register.
If CS remains LOW longer than t
EOCtest
, the first rising
edge of SCK will occur and the conversion result is serially
shifted out of the SDO pin. The data output cycle begins on
this first rising edge of SCK and concludes after the 24th
rising edge. Data is shifted out the SDO pin on each falling
edge of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of the
conversion result on the 24th rising edge of SCK. After the
24th rising edge, SDO goes HIGH (EOC = 1), SCK stays
HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first and 24th rising edge of
SCK, see Figure 9. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
new conversion. This is useful for systems not requiring
all 24 bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion. If CS is
pulled HIGH while the converter is driving SCK LOW, the
Figure 9. Internal Serial Clock, Reduced Data Output Length
APPLICATIO S I FOR ATIO
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SDO
SCK
(INTERNAL)
CS
>t
EOCtest
MSBSIG
BIT 8
TEST EOC BIT 19 BIT 18BIT 20BIT 21BIT 22
EOC
BIT 23
EOC
BIT 0
SLEEP
TEST EOC
(OPTIONAL)
SLEEP
DATA OUTPUT
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
DATA
OUTPUT
CONVERSION
CONVERSION
SLEEP
2431 F09
<t
EOCtest
V
CC
10k
TEST EOC
V
CC
F
O
REF
+
REF
–
SCK
IN
+
IN
–
SDO
GND
CS
REFERENCE
VOLTAGE
0.1V TO V
CC
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
3-WIRE
SPI INTERFACE
1µF
2.7V TO 5.5V
LTC2430/
LTC2431
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC