Digital Equipment MS11-BC User manual

PDP-11/45
MS11 semiconductor
memory systems
maintenance manual

C; un MJ r- 13-0 ( IJ ro r 5:. , f.f(JJc/(b oL m
PDp .. 11/45
MS11 semiconductor
memory systems
maintenance manual
DEC-II-HMSB-D
digital equipment corporation · maynard. massachusetts

1st Edition April 1972
2nd Printing (Rev) August 1972
3rd Printing January 1973
Copyright © 1972, 1973 by Digital Equipment Corporation
The material in this manual is for information-
al purposes and is subject to change without
notice.
The following are trademarks of Digital Equipment
Corporation, Maynard, Massachusetts:
DEC
FLIP CHIP
DIGITAL
PDP
FOCAL
COMPUTER LAB

CONTENTS
CHAPTER 1 SYSTEM DESCRIPTION
1.1 Introduction
. . . . . . .......
1.2 M8111 Bipolar Memory Matrix Module
1.3 G401
MaS Memory Matrix Module
1.4
M8ll0 Semiconductor Memory Control Module
1.4.1 Memory Address Multiplexing
1.4.2 Write and Read Data Registers
1.4.3 Timing and Control
1.4.4 Refresh Logic
1.4.5 Parity Control
1.4.6 Diagnostic Logic
1.5 System Specifications
1.6 Semiconductor Memory System Configurations
CHAPTER 2 MEMORY SYSTEM INTERFACE OPERATIONS
2.1
2.2
2.2.1
2.2.2
2.2.3
2~2.4
2.3
2.3.1
2.3.2
2.4
2.4.1
2.4.2
2.5
2.6
2.6.1
2.6.2
2.6.3
2.6.4
Introduction
Basic Memory Access Operations
Data In (DATI) Cycle . . . .
Data In, Pause (DATIP) Cycle
Data
Out (DATa) Operation
Data Out, Byte (DATOB) Cycle
Fastbus Interface
..
Fastbus DATa Cycle
Fastbus DATI Cycle
Unibus Interface
Unibus
DATa Cycle
Unibus DATI Cycle
Memory Bus
Semiconductor Memory Addressing
Address Decoding
at the M8ll 0 Control
Address Mapping
at the M8ll 0 Control
MaS Memory Matrix Module Address Decoding
Bipolar Memory Matrix Module Address Decoding
CHAPTER 3 LOGIC DESCRIPTION
3.1
3.2
3.2.1
3.2.2
3.3
3.3.1
3.3.1.1
Introduction ............. .
G40l MaS Memory Matrix Module Logic
MaS Memory Writing . . . . . . . . . .
MOS :Memorj Reading
M8lll Bipolar Memory Matrix Module Logic
Memory Matrix Control
Address Buffer
iii
Page
1-1
1-2
1-2
1-3
1-3
1-3
1-4
1-4
1-4
1-5
1-5
1-6
2-1
2-1
2-2
2-2
2-4
2-4
2-4
2-5
2-7
2-7
2-8
2-8
2-8
2-10
2-11
2-11
2-12
2-12
3-1
3-1
3-2
3-4
3-4
3-4
3-4

3.3.1.2
3.3.1.3
3.3.2
3.4
3.4.1
3.4.2
3.4.3
3.4.3.1
3.4.3.2
3.4.3.3
3.4.4
3.4.5
3.4.6
3.4.7
3.4.7.1
3.4.7.2
3.4.7.3
3.4.8
3.4.8.1
3.4.8.2
3.4.8.3
CONTENTS (Cont)
Data Inversion and Write Pulse Fanout Logic
Address Examination Logic . . . . . . . . .
Bipolar Matrix .............. .
M8110 Semiconductor Memory Control Module
Memory Selection Logic
Unibus Interface (SMeH) .,
Address Multiplexing (SMCC)
Unibus Address Multiplexing
Fastbus Address Multiplexing
Refresh Address Multiplexing
Data Multiplexing (SMCD)
Data Output (SMCE)
M8ll0 Control Logic .. .
Diagnostic Logic
Diagnostic Address Decoding
Diagnostic Parity Registers
Diagnostic Parity Register Functions
Refresh Logic . . . . . . . . . . . .
Normal Refresh Cycle ...... .
Refresh Cycle Intervention During Single-Step Mode
Refresh Cycle During Power-Down Periods
CHAPTER 4 CALIBRATION AND MAINTENANCE
4.1
4.2
4.2.1
4.2.2
4.2.3
4.3
4.3.1
4.3.1.1
4.3.2
4.3.2.1
4.4
4.5
4.5.1
Introduction
Semiconductor Memory System Precalibration Procedures
Memory Cycling Program
Test Equipment Required
Calibration Setup ....
Memory System Calibration
MOS Memory System Calibration
Address Set Up, Precharge, CENABLE, and Access Ready Timing
Adjustments
Bipolar Memory System Calibration
Address Set Up, Precharge, and Access Ready Timing Adjustments
Semiconductor Memory System Diagnostics
Memory Matrix Module Structure .....
Isolation of Malfunctions to Module Component .'
APPENDIX A APPLICATION OF MOSFETS IN IC RANDOM ACCESS MEMORIES
A.1
A.2
A.3
Introduction
The MOSFET
The MOSFET as a Memory
iv
Page
3-6
3-6
3-7
3-8
3-11
3-14
3-16
3-17
3-17
3-18
3-18
3-18
3-19
3-19
3-44
3-44
3-45
3-47
3-47
3-49
3-50
4-1
4-1
4-1
4-2
4-2
4-2
4-2
4-3
4-4
4-4
4-4
4-5
4-5
A-I
A-I
A-2

f"",
CONTENTS (Cont)
Page
APPENDIX B INTEGRATED CIRCUIT DESCRIPTIONS
Figure No.
1-1
1-2
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
4-1
1103 Random Access 1024-Bit Memory .....
3207 Quad 3-Input NAND TTL/MaS Lever Shifter
3404 High Speed Hex Latch
74200 Bipolar 256-Bit Random Access Memory
75107/7 51 08 Dual-Line Receivers ..... .
8242 Exclusive-NOR 4-Bit Digital Comparator .
ILLUSTRATIONS
Title
MS 11 Semiconductor Memory System, Block Diagram
MS 11 Semiconductor Memory Control Module, Block Diagram
Semiconductor Memory Configuration within PDP-l 1/45 Systems
Semiconductor Memory System Interfaces
Fastbus Interface
................... .
Unibus Interface
B-3
B-5
B-7
B-9
B-ll
B-13
Page
1-1
1-3
2-2
2-3
2-6
2-9
Semiconductor Memory Bus, Simplified Block Diagram 2-10
Semiconductor Memory Address Examination 2-11
Semiconductor Memory Address Mapping 2-12
MaS Memory Matrix Address Examination 2-13
Bipolar Memory Matrix Addressing . 2-14
MaS Memory Matrix, Block Diagram . . . 3-3
Bipolar Memory Matrix
.. . . . . . . . . 3-5
M8110 Semiconductor Memory Control Module, Block Diagram 3-9
Simplified Memory Address Decode (SMCF)
........ 3-13
Fastbus Address Multiplexing
<14: 11> Required E67 Jumpers 3-15
MAD Multiplexing, Required E86 Jumpers . . . . . . . . . 3-15
Unibus Address Multiplexing
04: 11> Required E78 Jumpers 3-15
Unibus
DATa Logic Flow 3-20
Fastbus DATa Logic Flow 3-27
Unibus DATI Logic Flow . 3-34
Fastbus DATI Logic Flow 3-37
Unibus
DATa Timing (MOS Memory) 3-39
Fastbus
DATa Timing (MaS Memory) 3-40
Unibus DATI Timing (MOS Memory) 3-41
Fastbus DATI Timing
(MaS Memory) 3-42
Diagnostic Logic Parity Checking and Control 3-43
Nonnal MOS Refresh Cycle Ti.111ing . . . . . . 3-48
M8110 Timing and Termination Delay Adjustment for MaS Memory
(Logic Drawing SMCA)
........................ 4-4
v

4-2
4-3
4-4
A-I
A-2
A-3
Table No.
1-1
1-2
2-1
2-2
2-3
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
4-1
ILLUSTRATIONS (Cont)
M8110 Timing and Termination Delay Adjustment for Bipolar
Memory (Logic Drawing SMCA)
.............. .
G401YA MOS Memory Matrix Module-Relationship ofICs to Bits
M8111 Bipolar Memory Matrix
Module-Relationship of ICs to Bits
Physical Structure of a MOSFET .
Drain Characteristics
of a MOSFET
Basic Dynamic MOS Storage Cell .
TABLES
Title
MOS Memory System Configuration
Bipolar Memory System Configuration '"
Fastbus/M8110 Interface and Control Signals
Fastbus and Unibus Control Bit States
Unibus/M8110 Interface Information and Control Signals
MOS Matrix Selected Address Configuration (4 of 16K)
MOS Matrix Control Level Generation and Selected Memory Address
Block
(1 of 4K) ............... .
Expanded M811l Memory Address Allocation ..... .
Address
Bit to MAD BitTranslation
Bipolar Matrix Selected Address Configuration
(I of 16K)
Address Decoding for Memory Circuit Enabling
Fastbus/Unibus Memory Address (Assign and Decode)
MOS/Bipo1ar Module Addressing ..... .
MOS/Bipolar Memory Addressing .... .
MUltiplexed Address Inputs to MAD (SMCC)
Diagnostic Parity Register A and B Control States
Parity Diagnostic Register Bit Identity and Function
Semiconductor Memory Adjustments
vi
Page
4-5
4-7
4-9
A-I
A-2
A-3
Page
1-6
1-6
2-4
2-5
2-7
3-2
3-2
3-5
3-6
3-7
3-8
3-12
3-13
3-13
3-17
3-45
. 3-45
4-2
/.J

(
INTRODUCTION
This manual describes the MSll options that constitute the PDP-ll/45 Semiconductor Memory System. Its pri-
mary purpose is to provide information for DEC Field Service representatives and customer personnel, with simi-
lar PDP-l1/45 training, to perform on-site maintenance of the MSll options. The information is presented in
four chapters.
Chapter 1 describes the
MS 11 Semiconductor Memory System structure. It also provides module specifications
and system configuration information.
Chapter 2 describes semiconductor memory system access operations, interfacing, and addressing.
Chapter 3 provides a detailed analysis
of semiconductor memory logic operation.
Chapter 4 presents the procedures required for semiconductor memory calibration and maintenance.
All descriptions assume that the reader is familiar with basic digital computer theory and the operating character-
istics
of bipolar and metal-oxide semiconductor (MaS) digital integrated circuits. Because of the many recent ad-
vances in MaS technology concerning memory system applications, Appendix A contains a description of MaS
memory circuit theory.
Data, address, and control signals relevant to semiconductor memory operation are transmitted on the Unibus or
the
PDP-ll/45 Fastbus. This manual references the data, address, and control lines that interface the semicon-
ductor memory system with otherPDP-l1/45 units, according to the conventions established for Unibus and
PDP-l 1/45 signal mnemonics. For example, SAPJ PA (17:06) H refers to the 12 physical-address (PA) inputs,
named PA17 through PA06, which are generated
as shown on drawing SAPJ. The prefix SAPJ indicates sheet J
of the SAP module schematic. Complete details on data, address, and control signal origin and derivation are pro-
vided in the following related manuals:
PDP-l 1/45 System Maintenance Manual
KB 11 Central Processor Maintenance Manual
KT 11 Memory Management Unit Maintenance Manual
PDP-II Unibus Interface Manual (Second Edition)
vii
DEC-II-H45B-D
DEC-II-HKBB-D
DEC-II-HKTB-D
DEC-II-HIAB-D

;...

(
CHAPTER 1
SYSTEM DESCRIPTION
1.1 INTRODUCTION
Digital Equipment Corporation's MSl1 Semiconductor Memory Systems for the PDP-I 1/45 System are high-
speed random-access memories available in two basic solid-state types: bipolar (TTL) and metal-oxide semi-
conductor (MOS). The distinction between bipolar and MOS memory systems is made in the specific MSI com-
ponents used to form the memory storage matrices. Both forms
of semiconductor memory matrices operate
under the control of the M8lI 0 Semiconductor Memory Control module. The M811 0 can control either four
1024-word M8111 Bipolar Memory Matrix modules or four 4096-word G40l MOS Memory Matrix modules
(Figure 1-1). One bipolar memory system provides storage for 4096 16-bit words, and one MOS memory sys-
tem provides storage for 16,384 16-bit words. Both forms of semiconductor memory are available with or with-
out byte parity.
SEM ICONDUCTOR
MEMORY
CONTROL
Me110
CPU
FAST BUS
DIRECT ACCESS
DEVICES
UNIBUS B
11-1316
Figure 1-1 MS 11 Semiconductor Memory System, Block Diagram
1-1

The bipolar and MOS semiconductor memories can be jointly or separately operated from either the KB 11
Fastbus or the PDP-II Unibus, or from both, depending on the specific PDP-l 1/45 System configuration. When
operated from the Unibus, each semiconductor memory system functions
as a PDP-II compatible peripheral
and can serve
as the basic memory in a large-scale system. Operation underjoint control of the Fastbus and
Unibus provides direct high-speed memory access through the Fastbus for the
KB 11 Processor, while maintain-
ing the processor/peripheral relationships characteristic
of the Unibus. Whether operating jointly or separately
with the Unibus and/or Fastbus, a semiconductor memory always assumes the role
of a "slave" device to the
processor. Under Unibus control, the memory also
is "slave" to any peripheral (direct access) device currently
designated "master".
Because readout from semiconductor memories is non-destructive, the write-after-read-cycle time associated with
ferrite-core memories
is eliminated. In addition, the switching speed for semiconductor memories is characteris-
tically much faster than
that for the ferrite-core memory. The extremely high switching speeds characteristic
of bipolar memory cells permit memory cycle times of 300 ns for an operating bipolar memory system. MOS
semiconductor memory systems have slower cycle times of 450 ns.
1.2 M8111 BIPOLAR MEMORY MATRIX MODULE
The M8111 Bipolar Memory Matrix module is an 8-1/2 in .. X 15 in. multilayer glass hex board, configured to
either store or not store byte parity. The M811I
YA parity-equipped modules contain seventy-two 256 X I-bit
TTL
MSI memory circuits, interconnected to form a 1024 X IS-bit memory matrix. Each IS-bit word in this
matrix
is formed by two S-bit bytes and two parity bits, one per byte. This module also contains appropriate
address decoding and driving logic, IS write-data inversion stages, and control-signal decoding logic. All decod-
ing inversion and driving logic
is formed by TTL integrated circuits. Address lines <14: II> at each MSlll matrix
module are jumper-connected so
that in a given bipolar memory system each matrix module can be configured
to decode a unique address. The MS111 Bipolar Memory Matrix module
is identical to the M8111YA in all
respects, except that the MSl11 contains sixty-four 256 X I-bit
MSI memory circuits, interconnected to form
a 1024 X 16-bit memory matrix without byte parity.
1.3 G401 MOS MEMORY MATRIX MODULE
The G401 MOS Memory Matrix module is an S-1/2 in. X 15 in. double-sided, multilayer glass hex circuit board;
also configured to either store or
not store byte parity. The G401YA parity-equipped module contains seventy-
two 1024 X I-bit
MOS MSI circuits, interconnected to form a 4096 X IS-bit memory. The IS-bit word configu-
ration
is exactly the same as the bipolar matrix, i.e., two S-bit bytes and two parity bits, one per byte. This mod-
ule also contains appropriate logic to level-shift addresses, data, and control signals from TTL to
MOS and MOS
to TTL voltage levels; and 16 or IS intergrated-circuit sense amplifiers, depending on whether parity is specified,
one for each
of the read-sense lines. The states of memory address (MAD) register bits (02:01) and <14: 13) are
decoded at this module to select the specific module and the group
of 1024 words addressed within the selected
module. Addtess bits
MAD <I 4: 13) are jumper-connected so that each 4096-word matrix can be selected and
wired for a unique address assignment. The G401
MOS Memory Matrix module is identical in all respects to the
G40lY A, except that the G401 contains sixty-four 1024 X I-bit MSI memory circuits, interconnected to form
a 4096 X 16-bit memory matrix without byte parity.
Operation
of the MOS memory matrix is substantially different from the bipolar matrix in two respects. First,
because
of the nature of the dynamicMOS storage cell (Appendix A), each memory access must include a time
interval for precharging the addressed cells prior
to the actual access. Second, all memory locations in an MOS
system must be periodically refreshed, usually every 1 ms, to assure data validity during any extended standby
intervals.
1-2

1.4 M8110 SEMICONDUCTOR MEMORY CONTROL MODULE
The M811 0 Semiconductor Memory Control module is a fully integratedtwo-port memory controller capable
of controlling either four M81ll or four G40l matrix modules. A simplified block diagram of the M8ll 0 con-
trol
is shown in Figure 1-2. The M8ll0 control multiplexes memory access addresses and associated data be-
tween the PDP-l 1/45 Fastbus and a Unibus, and directs logic and timing sequences necessary for the storage or
retrieval of each data word or byte associated with a given access cycle. Each of the M8ll 0 control functions is
described briefly in the following paragraphs.
FAST BUS
r ~'~M;O;; C-;T;L- - -- -- - - _ ....... ~:~~ -- -- -,
I MEMORY /.;111.,.,;1;....-._-,
I REFRESH
LOG IC ADDRESS ~
(MOS MEMORY ONLY) MULTIPLEXER
TIMING
I AND I
,....-------+\ CONTROL 1-- _____ ---.
I I
I I
I DIAGNOsl~g LOGIC I-----t- DATA (A I
i PARITY CONTROL REGISTERS", i
L _______ ~~-- r----I- _J
v
UNIBUS B
~v '-/
16K MOS MEMORY
OR
4K BIPOLAR MEMORY
Figure 1-2 MSll Semiconductor Memory Control Module, Block Diagram
1.4.1 Memory Address Multiplexing
y
11-1317
The memory address multiplexing function involves two sequential actions under direct control of the M811 0
timing and control logic. First, based on priority, arbitration of memory access requests performed by the tim-
ing and control logic, Fastbus, Unibus, or refresh addresses (for MOS memory systems only) are multiplexed into
the memory address (MAD) register. Second, through a parallel bit-to-bit connection scheme, Fastbus or Unibus
addresses are mapped into the MAD register. Once mapped into the MAD register, and address is strobed into the
associated bipolar
or MOS memory matrix module selected by that address through action of the M811 0 timing
and control function.
1.4.2 Write and Read Data Registers
The M8110 contains two data registers: the write-data (DATO) register, and the read-data (DATI) register. The
DATO register multiplexes a 16-bit data word (or two 8-bit data bytes), from either the Fastbus or Unibus, and
stores
that data until strobed into the associated bipolar or MOS memory matrix module by the M811 O. The
18-bit DATO register stores parity for the lower and upper data bytes in the most significant DATO register
stages. These parity bits are generated
as part of word or byte storage in the DATO register. Data from the
1-3

Unibus is received at the M811aUnibus interface for storage in the DATO register. Fastbus data to be written
is received directly at the DATO register because of the proximity of the M8110 to the KB 11 Processor. At the
appropriate time, the data accompanying a DATO cycle is strobed into the memory location designated by the
associated address.
The M8110 DATI register receives and stores data from the location addressed in the memory matrix as a direct
result of a Unibus or Fastbus DATI cycle. At the end of a DATI cycle, data is strobed jointly onto the M8110
Unibus interface, and to the Fastbus for retrieval by the requesting bus. Fastbus data lines are unidirectional,
Unibus data lines are bidirectional.
1.4.3 Timing and Control
The M8110 timing and control interprets control signals from the Fastbus or Unibus and derives the internal
multiplexing priorities, timing, and the nature of the operation to be subsequently performed (DATO or DATI).
In addition, specific portions of the address contained in the MAD register are decoded by the selection logic
to identify the physical memory selected, the memory section to be addressed (one out of four l024-word sec-
tions or one out of four 4096-word sections), the required byte configuration, and to determine if data words
are to be interleaved. If the operation to be performed is a DATO, the timing and control logic develops the
strobe levels necessary to load multiplex addresses and data, according to the priority of the request, into perti-
nent registers. The timing and control logic also enables the designated memory section for writing and performs
the DATO operation.
Because readout from semiconductor memories is non-destructive, the timing and control logic strobes the ad-
dressed data onto the output lines which connect to both buses. In this case, the bus that initiated the read
operation receives the data at the bus input as the data requested.
1.4.4 Refresh Logic
The nature of the dynamic MOS MSI circuits forming the G401 MOS Memory Matrix module requires that each
storage cell, which is the circuit equivalent of a capacitive node, be periodically charged above the threshold of
the data stored. Refreshing the data contained in each integrated-circuit memory requires that all states of the
row address for that circuit be cycled each 1 ms. The M8110 refresh logic performs this function automatically
by generating 32 sequential row addresses during each I-ms period. These sequential addresses are then input to
the address multiplexer. Coincident control levels from the refresh logic serve to enable the address priority por-
tion of the timing and control logic to permit input of refresh addresses at the assigned priority level.
Each DATO or DATI operation (with the exception of the write portion of a write-after-read operation) also in-
cludes the precharging or refreshing of each address written into or read. When the M81! 0 is used with bipolar
memory matrix modules, this refresh logic is inhibited and the precharge interval is ignored.
1.4.5 Parity Control
Data to be written is transferred to the M81l 0 over 16 data lines. If the operation is a DATO cycle, parity is gen-
erated and stored in bit 16 for the low-order byte and in bit 17 for the high-order byte. If the operation is a
DATOB, parity is generated only for the byte written and stored in the corresponding parity.
During DATI operations, parity is checked after each 16 bits of data read are transferred to the M81l 0 output
data register. If a parity error is detected, the respondent bus is notified.
1-4

(
(
1.4.6 Diagnostic Logic
M8ll0 memory control diagnostic logic allows writing of data from the Unibus with parity selected as odd or
even in any memory address, and to check the parity generated for odd or even, regardless of the manner gener-
ated. Part
of the M8110 memory control diagnostic logic structure decodes specific Unibus addre'Sses that are
jumper-connected
at each M8l1 0 so that each half of the total semiconductor memory has a unique address.
Each control also contains two diagnostic parity registers that are selected by M81!0 interpretation of Unibus
control signals
to select one of these two registers for loading of Unibus data within a DATO cycle. The data
loaded is
then interpreted to determine the specific section of memory designated for diagnostic parity exercising.
In this manner, diagnostic software can selectively exercise designated semiconductor memory areas for parity,
while protecting those memory areas occupied
by the diagnostic programs. Each M8ll 0 diagnostic parity regis-
ter can also be selectively read through execution of a Unibus DATI cycle. Parity error indication, when enabled,
is transmitted directly to the processor through the Pastbus.
1.5 SYSTEM SPECIFICATIONS
M8110 M811 G401
Characteristics Semiconductor Bipolar Memory
MOS Memory
Memory
Control Module Matrix Module Matrix Module
Storage Capacity NA 1024 I8-bit words
4096 18-bit words
Maximum Access Time:
DATO cycle NA NA NA
DATI cycle NA
200 ns 350 ns
Maximum Cycle Time NA
300 ns 450 ns
Operating Voltages:
VCC +5V, -15V +5V ±5V
VBB +23.7V
VDD +0.7V
VSS +19.7V
Over-Voltage Regulation
±5%
±5% ±5%
*Maximum Power Consumption:
active 19.65W 50W 39.35W
inactive 19.65W 50W 16.01W
Environmental conditions:
temperature 32°
to 1200p 32°
to 1200p 32°
to 1200p
(0° to 48°C) (0°
to 48°C) (0°
to 48°C)
humidity 10%
to 80% 10%
to 80%
10% to 80%
Mechanical Parameters:
height 15 in. (38.1 cm)
15 in. (38.1 cm)
15 in. (38.1 cm)
width
8.5 in. (21.59 cm) 8.5 in. (21.59 cm) 8.5 in. (21.59 cm)
depth
1/2 in. (1.27 cm) 1/2 in. (1.27 cm) 1/2 in. (1.27 cm)
Construction fiberglass/ fiberglass/ fiberg1ass/
multilayer multilayer multilayer
Co
0 li.l1g
internal fan
internal fan
internal fan
Mounting dedicated plug-in dedicated plug-in dedicated plug-in
slot in CPU slot in CPU slot in CPU
*Maximum power per module of each type.
1-5

1.6 SEMICONDUCTOR MEMORY SYSTEM CONFIGURATIONS
Tables 1-1 and 1-2 list the quantity of options that are required as a result of the selected memory type (MaS or
bipolar) and size. The module complement that comprises the corresponding option is also shown. If, for example,
a 24K capacity
MaS memory without parity is desired, the required configuration will consists of one MS II-BC
option (composed of one M8110 module, one H746A module, and one H744A module), one MSII-BD option,
and six
MS Il-BM options (G401 memory matrices). The additional M8II 0 Controller (MS II-BD option) is nec-
essary for the 8K
of memory in excess of the 16K controlled by the MS II-Be option.
Table
1-1
MOS Memory System Configuration
Memory Option
Type Number
Capacity MSII-BC MSl1-BD MSII-BM MSII-BP
Option Module Complement
(l)M8110
With Without
(l)H746A
(l)M8110
(1)G401 (1) G401YA
Parity Parity (1)H744A
4K I 1
4K 1 1
8K 1 2
8K 1 2
12K I 3
12K 1 3
16K 1 4
16K 1 4
20K 1 1 5
20K I 1 5
24K 1 1 6
24K I 1 6
28K 1 1 7
28K 1 1 7
32K I I 8
32K 1 1 8
Table 1-2
Bipolar Memory System Configuration
Memory Option Type Number
Capacity MSII-CC MSII-CM MSII-CP
Option Module Complement
With Without
(l)M8110
(1)M8111
(l)M8111YA
Parity Parity (2)H744A
lK
I 1
IK
1 1
2K 1 2
2K 1 2
3K 1 3
3K 1 3 (continued
on next page)
1-6

Table 1-2 (Cont)
Bipolar Memory System Configuration
Memory Option
Type Number
Capacity MSII-CC MSII-CM MSII-CP
Option Module Complement
With Without (1)M8110 (1)M8111 (1)M8111YA
Parity Parity (1)H744A
4K 1 4
4K 1 4
5K 2 5
5K 2 5
6K 2 6
6K 2 6
7K 2 7
7K 2 7
8K 2 8
8K 2 8
(
1-7

(,
2.1 INTRODUCTION
CHAPTER 2
MEMORY SYSTEM
INTERFACE OPERATIONS
A PDP-I 1/45 System can be equipped with one or two MSIIO Semiconductor Memory Control modules. Each
MSIIO module, in turn, can exercise control of up to four MSIII Bipolar Memory Matrix modules, or up to four
G401 MOS Memory Matrix modules. Since the memory capacity of these two matrix module types is different
(the
MSlll provides IK and the G401 4K of memory) the total memory capacity available to the user is deter-
mined by the selected configuration. A typical
two-MSll 0 module arrangement can consist of up to SK of bi-
polar memory in IK increments
or up to 32K of MOS memory in 4K increments. The two-controller configuration
might also have one
of the controllers directing bipolar matrices while the other is connected to MOS matrices.
However, memory matrices
of different types can not be connected to the same MSll 0 control. As indicated in
Tables
1-1 and 1-2, the memory capacity determines the number of MSII 0 modules required (the maximum
configuration
is 4K of bipolar or 16K of MOS memory per module). Figure 2-1 illustrates the memory system,
bus, and processor relationship. Within a PDP-l 1/45 computer system, the CPU communicates with associated
semiconductor memory controls through an extremely high-speed information
path which is internal to the CPU
and under control of the CPU Fastbus. One Unibus in the system, normally Unibus A, also communicates with
the two
MS11 0 controls.
Each
MSll 0 control, in turn, communicates with up to four bipolar or four MOS memory matrix modules. There-
fore, an operating
MSII 0 Semiconductor Memory Control has three active interfaces: the Fastbus interface, the
Unibus interface, and the memory bus. The relationship of a typical PDP-l 1/45 Semiconductor Memory System
to these interfaces
is shown in Figure 2-2. Because the MSII 0 control and associated memory matrix modules
are physically located in
the PDP-l 1/45 processor, connection to the Fastbus is by direct-wiring the control and
matrix module connectors
to the PDP-I 1/45 CPU backplane. However, the potentially remote location of a
second Unibus, with respect
to the MSII 0 control, requires a defined Unibus interface on the control to drive
and receive information and control signals
to and from that Unibus. Like the Fastbus connection, memory bus
connection between an
MSII 0 control and associated MSl11 bipolar or G40I MOS memory modules involves
physically adjacent connectors, so
that control-matrix module information and signals are direct-wire connected.
Discussion
of semiconductor memory system interfaces will involve a description of memory access operation, a
definition
of each interface in terms of information and signals exchanged, and an explanation of the conventions
used
to address semiconductor memories.
2.2 BASIC MEMORY ACCESS OPERATIONS
MS 11 Serr>Jconductor M:emory Systems operate in four accessing modes: read, write, optional byte handling, and
pause for a write following a read. These operations are designated
as follows:
2-1

a. Read Data(DATI)
b. Read data and pause (DATIP)
c. Write data (DATO)
d. Write data bytes (DATOB)
Each of these modes are briefly discussed in the following paragraphs.
I
I
I
I
I
I
I
I
I
(UNIBUSAI
AND UNIBUS B
NORMALLY I
CONNECTED) I
I I
I I
I I
I I
I I
I I
I I
I
UNIBUS A
PDP-11/45
CPU
4K
BI-POLAR
OR
16K
MOS
4K
BI-POLAR
OR
16K
MOS
UNI BUS B
Figure 2-1 Semiconductor Memory Configuration within PDP-ll/45 Systems
2.2.1 Data
In (DATI) Cycle
11-0833
During a DATI cycle, data in the locations addressed at the memory matrix module is loaded into the M8ll0 out-
put data latch for retrieval by the initiating bus (Unibus or Fastbus). Readout of semiconductor memories is non-
destructive; thus, the restore portion
of the conventional core memory read cycle is not required.
2.2.2 Data In, Pause (DATIP) Cycle
The purpose
of this reading mode is to hold memory secure after data is read from a set of memory addresses un-
til
that data can be revised and then written again. PDP-II convention requires that execution of a DATIP is al-
ways followed by execution of a DATO or DATOB operation. A DATIP is a duplicate of a DATI operation ex-
cept for a pause for initiation
of the impending DATO or DATOB.
2-2

(
MBlll
BI-POLAR
OR
G40l
MOS MEMORY
MATR IX
MODULE
MBlll
BI-POLAR
OR
G40l
MOS MEMORY
MATRIX
MODULE
M8ll0 MEMORY BUS
M8lll
BI-POLAR
OR
G40l
MOS MEMORY
MATR IX
MODULE
M8ll1
BI-POL.A.R
OR
G40l
MOS MEMORY
MATRIX
MODULE
~------------------------------------~ ~------------------------------------~
FAST BUS INTERFACE
FAST BUS INTERFACE
M8ll0*
SEMICONDUCTOR
MEMORY
CONTROL
M8ll0*
SEM ICONDUCTOR
MEMORY
CONTROL
UNIBUS INTERFACE
UNIBUS INTERFACE
M8ll0 MEMORY BUS
M8lll
BI-POLAR
OR
G40l
MOS MEMORY
MATRIX
MODULE
M8lll
BI-POLAR
OR
G40l
MOS MEMORY
MATRIX
MODULE
* A SINGLE M8llO CAN DIRECT EITHER FOUR G40l MODULES OR
FOUR M8lll MODULES BUT NOT A MIXTURE OF THE TWO
MODULE TYPES.
M8lll
BI-POLAR
OR
G40l
MOS MEMORY
MATRIX
MODULE
Figure 2-2 Semiconductor Memory System Interfaces
2-3
M8ll1
BI-POLAR
OR
G401
MOS MEMORY
MATRIX
MODULE
11-0826