Linear Technology LTM4649EY Quick setup guide

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dc1856a-bf
DEMO MANUAL DC1856A-B
DESCRIPTION
LTM4649EY
10A Step-Down µModule
Regulator
Demonstration circuit 1856A-B features the LT M
®
4649EY
µModule
®
regulator, a high performance, high efficiency
step-down regulator. The LTM4649EY has an operating
input voltage range of 4.5V to 16V and is able to provide
an output current of up to 10A. The output voltage is pro-
grammable from 0.6V to 5V and can be remotely sensed
with the internal differential remote sensing amplifier. The
LTM4649EY is a complete DC/DCpoint-of-load regulator in
a thermally enhanced 15mm ×9mm ×5.01mm BGA pack-
age requiring onlya few input andoutput capacitors. Output
L, LT, LTC, LTM, µModule, Burst Mode, Linear Technology and the Linear logo are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
PERFORMANCE SUMMARY
BOARD PHOTO
voltage tracking is available through the TRACK/SS pin for
supply rail sequencing. External clock synchronization is
also available through the CLKIN pin. The LTM4649 data
sheet must be read in conjunction with this demo manual
prior to working on or modifying demo circuit 1856A-B.
Design files for this circuit board are available at
http://www.linear.com/demo
(TA= 25°C)
PARAMETER CONDITIONS/NOTES VALUE
Input Voltage Range 4.5V to 16V
Output Voltage VOUT Jumper Selectable 1.0VDC, 1.2VDC, 1.5VDC, 1.8VDC, 2.5VDC, 3.3VDC
Maximum Continuous Output Current Derating is Necessary for Certain Operating
Conditions. See Data Sheet for Details
10ADC
Default Operating Frequency 450kHz
External Clock Synchronous Frequency Range 250kHz to 780kHz
Efficiency VIN = 12V, VOUT = 1.8V, IOUT = 10A 89% See Figure 2

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DEMO MANUAL DC1856A-B
QUICK START PROCEDURE
Figure 1. Test Setup of DC1856A-B
Demonstration circuit 1856A-B is an easy way to evaluate
the performance of the LTM4649EY. Please refer to Figure 1
for test setup connections and follow the procedure below.
1. With power off, place the jumpers in the following
positions for a typical 1.8VOUT application:
JP8 JP7 JP9 JP2
TRACK/SS RUN MODE VOUT Select
SS ON CCM 1.8V
2. Before connecting input supply, load and meters, preset
the input voltage supply to be between 4.5V to 16V.
Preset the load current to 0A.
3. With power off, connect the load, input voltage supply
and meters as shown in Figure 1.
4. Turn on input power supply. The output voltage meter
should display the selected output voltage ±2%.
5. Once the proper output voltage is established, adjust
the load current within the 0A to 10A range and observe
the load regulation, efficiency, and other parameters.
Output voltage ripple should be measured at J6 with a
BNC cable and oscilloscope.
6. To observe increased light load efficiency place the
Mode pin jumper (JP9) in the Burst Mode
®
position. To
observe increased light load efficiency with a reduced
output ripple ascompared to BurstMode operation place
the Mode pin jumper in the pulse-skipping position.
7. For optional load transient testing apply an adjustable
positive pulse signal between IOSTEP CLK and GND
pins. The pulse amplitude sets the load step current
amplitude. The pulse width should be short (<1ms)
and pulse duty cycle should be low (<15%) to limit the
thermal stress on the load transient circuit. The load
step current can be monitored with a BNC connected
to J5 (10mV/A).
Note: To evaluate PGOOD pin operation for the LTM4649,
insert a 100k resistor between PGOOD and INTVCC. Do
not stuff R15.
V
+
–
A
–
+
A–
+
LOAD
0A TO 10A
VIN
+ –
V+
–
+
–

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DEMO MANUAL DC1856A-B
QUICK START PROCEDURE
Figure 2. Measured Supply Efficiency at5VIN and 12VIN
VIN (V) VOUT (V) COUT CERAMIC
12 1.5 2 ×220µF/4V Ceramic
Figure 3. Measured Load Transient Response
(5A to 10A Load Step)
VIN (V) VOUT (V) IOUT (A) AIRFLOW AMBIENT (ºC)
12 1.5 10 Natural Convection 29.7
Figure 4. Measured Thermal Capture
VOUT = 100mV/DIV
IOUT STEP = 5A/DIV

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DEMO MANUAL DC1856A-B
PARTS LIST
ITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
Required Circuit Components
1 2 CO4, CO5 CAP, 100µF 20% 6.3V X5R 1210 AVX 12106D107MAT2A
2 1 CO2 CAP, 22µF 20% 6.3V X5R 1210 AVX 12106D226MAT2A
3 1 CIN1 CAP, 22µF 20% 16V X7R 1210 MURATA, GRM32ER71C226KE18L
4 1 CIN3 CAP, 150µF 10% 25V OS-CON SANYO, 25HVH150MT
5 2 CIN4, CIN5 CAP, 22µF 20% 16V X5R 1206 TAIYO YUDEN, EMK316BJ226ML-T
6 2 R22, R23 RES, 0603 10Ω 5% 1/10W VISHAY CRCW060310R0JNEA
7 1 R19 RES, 0603 1% 1/10W OPTION
8 1 C1 CAP, 0.1µF 20% 25V X7R 0603 AVX 06033C104MAT2A
9 1 C3 CAP, 2.2µF 20% 10V X5R 0603 TAIYO YUDEN LMK107BJ225MA-T
10 1 U1 I.C., LOW VOLTAGE POWER MODULE LINEAR TECH. LTM4649
Additional Demo Board Circuit Components
1 0 CO7 CAP, OPTION POSCAP 7343 OPTION
2 0 CO1, CO3, CO6 CAP, OPTION 1210 OPTION
3 1 C2 CAP, 1µF 20% 10V X5R 0603 TAIYO YUDEN LMK107BJ105MA-T
4 0 C4, C5, CTHP, CP, CFF CAP, OPTION 0603 OPTION
5 1 R11 RES, 2512 0.01Ω 5% 1W PANASONIC ERJ-M1WSF10MU
6 2 R10, RS, R14 RES, 0603 10k 1% 1/10W VISHAY CRCW060310K0FKEA
7 1 R16 RES, 0603 20k 5% 1/10W VISHAY CRCW060320K0JNEA
8 2 R17, R18 RES, 0603 51Ω 5% 1/10W VISHAY CRCW060351R0JNEA
9 1 R15 RES, 0603 OPTION OPTION
10 1 R1 RES, 0603 4.99k 1% 1/10W VISHAY CRCW06034K99FKEA
11 1 R2 RES, 0603 6.65k 1% 1/10W VISHAY CRCW06036K65FKEA
12 1 R3 RES, 0603 3.16k 1% 1/10W VISHAY CRCW06033K16FKEA
13 1 R4 RES, 0603 2.21k 1% 1/10W VISHAY CRCW06032K21FKEA
14 0 R5, R7, R8, R9, R12, R13, R20, R21, R24 RES, 0603 OPTION OPTION
15 2 R6,R25 RES, 0603 0Ω JUMPER VISHAY CRCW06030000Z0EA
16 1 Q14 XSTR, SUD50N03-09P MOSFET SILICONIX SUD50N03-09P-GE3
Hardware
1 10 E1-E10 TESTPOINT TURRET 0.094" MILL MAX 2501-2-00-80-00-00-07-0
2 6 JP1, JP2, JP3, JP4, JP5, JP6 HEADER, 2-PIN, 2mm SAMTEC TMM 102-02-L-S
3 2 JP7, JP8 HEADER, 3-PIN, 2mm SAMTEC TMM-103-02-L-S
4 1 JP9 HEADER, 3X2 2mm SAMTEC TMM-103-02-L-D
5 4 J1, J2, J3, J4 JACK, BANANA KEYSTONE 575-4
6 2 J5, J6 CONN, BNC, 5 PINS CONNEX 112404
7 4 XJP1, XJP7, XJP8, XJP9 SHUNT, 2mm SAMTEC 2SN-BK-G
8 4 STANDOFF, SNAP ON KEYSTONE_8834

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DEMO MANUAL DC1856A-B
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
SCHEMATIC DIAGRAM

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DEMO MANUAL DC1856A-B
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
[phone] ●FAX: [phone] ●www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2013
LT 0413 • PRINTED IN USA
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