Linear Technology LTC3729 User manual

1
LTC3729
sn3729 3729fas
550kHz, PolyPhase,
High Efficiency, Synchronous
Step-Down Switching Regulator
, LTC and LT are registered trademarks of Linear Technology Corporation.
OPTI-LOOP is a registered trademark of Linear Technology Corporation.
PolyPhase is a trademark of Linear Technology Corporation.
The LTC
®
3729 is a multiple phase, synchronous step-
down current mode switching regulator controller that
drives N-channel external power MOSFET stages in a
phase-lockablefixedfrequencyarchitecture.ThePolyPhase
controller drives its two output stages out of phase at
frequencies up to 550kHz to minimize the RMS ripple
currents in both input and output capacitors. The output
clock signal allows expansion for up to 12 evenly phased
controllers for systems requiring 15A to 200A of output
current. The multiple phase technique effectively multi-
plies the fundamental frequency by the number of chan-
nels used, improving transient response while operating
each channel at an optimum frequency for efficiency.
Thermal design is also simplified.
An internal differential amplifier provides true remote
sensing of the regulated supply’s positive and negative
output terminals as required for high current applications.
A RUN/SS pin provides both soft-start and optional timed,
short-circuit shutdown. Current foldback limits MOSFET
dissipation during short-circuit conditions when the
overcurrent latchoff is disabled. OPTI-LOOP compensa-
tion allows the transient response to be optimized over a
wide range of output capacitance and ESR values. The
LTC3729 includes a power good output pin that indicates
whentheoutputiswithin±7.5%ofthedesignedsetpoint.
Figure 1. High Current Dual Phase Step-Down Converter
■
Desktop Computers/Servers
■
Large Memory Arrays
■
DC Power Distribution Systems
■
Wide V
IN
Range: 4V to 36V Operation
■
Reduces Required Input Capacitance and Power
Supply Induced Noise
■
± 1% Output Voltage Accuracy
■
Phase-Lockable Fixed Frequency: 250kHz to 550kHz
■
True Remote Sensing Differential Amplifier
■
PolyPhase
TM
Extends from Two to Twelve Phases
■
Reduces the Size and Value of Inductors
■
Current Mode Control Ensures Current Sharing
■
1.1MHz Effective Switching Frequency (2-Phase)
■
OPTI-LOOP
®
Compensation Reduces C
OUT
■
Power Good Output Voltage Indicator
■
Very Low Dropout Operation: 99% Duty Cycle
■
Adjustable Soft-Start Current Ramping
■
Internal Current Foldback Plus Shutdown Timer
■
Overvoltage Soft-Latch Eliminates Nuisance Trips
■
Available in 5mm ×5mm QFN
and 28-Lead SSOP Packages
3729 TA01
TG1
BOOST1
SW1
BG1
PGND
SENSE1
+
SENSE1
–
TG2
BOOST2
SW2
BG2
INTV
CC
SENSE2
+
SENSE2
–
V
IN
RUN/SS
EAIN
I
TH
V
DIFFOUT
V
OS–
V
OS+
LTC3729
SGND
0.1µF
PGOOD
0.1µF
16k
1000pF
S
S
S
S
S
S
S
S
10Ω
3.3k
16k
+
10µF
35V
CERAMIC
×4
+
C
OUT
1000µF ×2
4V
L1, L2: CEPH149-IROMCC
OUT
: T510E108K004AS
D1, D2: UP5840 M1, M3: IRF7811W M2, M4: IRF7822
V
OUT
1.6V/40A
L1
0.8µH
0.002Ω
V
IN
5V TO 28V
L2
0.8µH
D2
D1
M1
M2
×2
M3
M4
×2
0.47µF
S
0.47µF
10µF
0.002Ω
APPLICATIO S
U
FEATURES
TYPICAL APPLICATIO
U
DESCRIPTIO
U

2
LTC3729
sn3729 3729fas
ORDER PART
NUMBER
LTC3729EG
ABSOLUTE AXI U RATI GS
W
WW
U
PACKAGE/ORDER I FOR ATIO
UUW
T
JMAX
= 125°C, θ
JA
= 95°C/W
(Note 1)
Input Supply Voltage (V
IN
).........................36V to –0.3V
Topside Driver Voltages (BOOST1,2).........42V to –0.3V
Switch Voltage (SW1, 2) .............................36V to –5 V
SENSE1
+
, SENSE2
+
, SENSE1
–
,
SENSE2
–
Voltages........................(1.1)INTV
CC
to –0.3V
EAIN, V
OS+
, V
OS–
, EXTV
CC
, INTV
CC
,
RUN/SS, PGOOD Voltages...........................7V to –0.3V
Boosted Driver Voltage (BOOST-SW) ..........7V to –0.3V
PLLFLTR, PLLIN, CLKOUT, PHASMD,
V
DIFFOUT
Voltages ................................ INTV
CC
to –0.3V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
TOP VIEW
G PACKAGE
28-LEAD PLASTIC SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RUN/SS
SENSE1
+
SENSE1
–
EAIN
PLLFLTR
PLLIN
PHASMD
I
TH
SGND
V
DIFFOUT
V
OS–
V
OS+
SENSE2
–
SENSE2
+
CLKOUT
TG1
SW1
BOOST1
V
IN
BG1
EXTV
CC
INTV
CC
PGND
BG2
BOOST2
SW2
TG2
PGOOD
I
TH
Voltage................................................2.7V to –0.3V
Peak Output Current <1µs(TGL1,2, BG1,2)................ 5A
INTV
CC
RMS Output Current................................ 50mA
Operating Ambient Temperature
Range (Note 6) ................................... –40°C to 85°C
Junction Temperature (Note 2)............................. 125°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)
(G Package Only) .................................................. 300°C
32 31 30 29 28 27 26 25
9 10 11 12 13
TOP VIEW
UH PACKAGE
32-LEAD 5mm ×5mm PLASTIC QFN
14 15 16
17
18
19
20
21
22
23
24
8
7
6
5
4
3
2
1EAIN
PLLFLTR
PLLIN
PHASMD
I
TH
SGND
V
DIFFOUT
V
OS–
BOOST1
V
IN
BG1
EXTV
CC
INTV
CC
PGND
BG2
BOOST2
NC SENSE1
–
SENSE1
+
NC RUN/SS CLKOUT TG1 SW1
V
OS+
NC
SENSE2
–
SENSE2
+
PGOOD
TG2
SW2
NC
ORDER PART
NUMBER
LTC3729EUH
ELECTRICAL CHARACTERISTICS
The ●denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. VIN = 15V, VRUN/SS = 5V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Main Control Loop
V
EAIN
Regulated Feedback Voltage (Note 3); I
TH
Voltage = 1.2V ●0.792 0.800 0.808 V
V
SENSEMAX
Maximum Current Sense Threshold V
SENSE–
= 5V ●62 75 88 mV
V
SENSE1, 2
= 5V 65 75 85 mV
I
INEAIN
Feedback Current (Note 3) –5 –50 nA
V
LOADREG
Output Voltage Load Regulation (Note 3)
Measured in Servo Loop; I
TH
Voltage = 0.7V ●0.1 0.5 %
Measured in Servo Loop; I
TH
Voltage = 2V ●–0.1 –0.5 %
Consult LTC Marketing for parts specified with wider operating temperature ranges.
θ
JA
= 34°C/W
EXPOSED PAD IS SGND
(MUST BE SOLDERED TO PCB)
UH PART
MARKING
3729

3
LTC3729
sn3729 3729fas
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ELECTRICAL CHARACTERISTICS
The ●denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. VIN = 15V, VRUN/SS = 5V unless otherwise noted.
V
REFLNREG
Reference Voltage Line Regulation V
IN
= 3.6V to 30V (Note 3) 0.002 0.02 %/V
V
OVL
Output Overvoltage Threshold Measured at V
EAIN
●0.84 0.86 0.88 V
UVLO Undervoltage Lockout V
IN
Ramping Down 3 3.5 4 V
g
m
Transconductance Amplifier g
m
I
TH
= 1.2V; Sink/Source 5µA; (Note 3) 3 mmho
g
mOL
Transconductance Amplifier Gain I
TH
= 1.2V; (g
m
xZ
L
; No Ext Load); (Note 3) 1.5 V/mV
I
Q
Input DC Supply Current (Note 4)
Normal Mode EXTV
CC
Tied to V
OUT
; V
OUT
= 5V 580 µA
Shutdown V
RUN/SS
= 0V 20 40 µA
I
RUN/SS
Soft-Start Charge Current V
RUN/SS
= 1.9V –0.5 –1.2 µA
V
RUN/SS
RUN/SS Pin ON Threshold V
RUN/SS
Rising 1.0 1.5 1.9 V
V
RUN/SSLO
RUN/SS Pin Latchoff Arming V
RUN/SS
Rising from 3V 3.8 4.5 V
I
SCL
RUN/SS Discharge Current Soft Short Condition V
EAIN
= 0.5V; V
RUN/SS
= 4.5V 0.5 2 4 µA
I
SDLDO
Shutdown Latch Disable Current V
EAIN
= 0.5V 1.6 5 µA
I
SENSE
Total Sense Pins Source Current Each Channel; V
SENSE1
–
, 2
– = V
SENSE1
+
, 2
+ = 0V –85 –60 µA
DF
MAX
Maximum Duty Factor In Dropout 98 99.5 %
Top Gate Transition Time:
TG1, 2 t
r
Rise Time C
LOAD
= 3300pF 30 90 ns
TG1, 2 t
f
Fall Time C
LOAD
= 3300pF 40 90 ns
Bottom Gate Transition Time:
BG1, 2 t
r
Rise Time C
LOAD
= 3300pF 30 90 ns
BG1, 2 t
f
Fall Time C
LOAD
= 3300pF 20 90 ns
TG/BG t
1D
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time C
LOAD
= 3300pF Each Driver 90 ns
BG/TG t
2D
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time C
LOAD
= 3300pF Each Driver 90 ns
t
ON(MIN)
Minimum On-Time Tested with a Square Wave (Note 5) 100 ns
Internal V
CC
Regulator
V
INTVCC
Internal V
CC
Voltage 6V < V
IN
< 30V; V
EXTVCC
= 4V 4.8 5.0 5.2 V
V
LDO
INT INTV
CC
Load Regulation I
CC
= 0 to 20mA; V
EXTVCC
= 4V 0.2 1.0 %
V
LDO
EXT EXTV
CC
Voltage Drop I
CC
= 20mA; V
EXTVCC
= 5V 80 160 mV
V
EXTVCC
EXTV
CC
Switchover Voltage I
CC
= 20mA, EXTV
CC
Ramping Positive ●4.5 4.7 V
V
LDOHYS
EXTV
CC
Switchover Hysteresis I
CC
= 20mA, EXTV
CC
Ramping Negative 0.2 V
Oscillator and Phase-Locked Loop
f
NOM
Nominal Frequency V
PLLFLTR
= 1.2V 360 400 440 kHz
f
LOW
Lowest Frequency V
PLLFLTR
= 0V 230 260 290 kHz
f
HIGH
Highest Frequency V
PLLFLTR
≥2.4V 480 550 590 kHz
R
PLLIN
PLLIN Input Resistance 50 kΩ
I
PLLFLTR
Phase Detector Output Current
Sinking Capability f
PLLIN
< f
OSC
–15 µA
Sourcing Capability f
PLLIN
> f
OSC
15 µA
R
RELPHS
Controller 2-Controller 1 Phase V
PHASMD
= 0V, Open 180 Deg
V
PHASMD
= 5V 240 Deg

4
LTC3729
sn3729 3729fas
ELECTRICAL CHARACTERISTICS
The ●denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA= 25°C. VIN = 15V, VRUN/SS = 5V unless otherwise noted.
Note 4: Dynamic supply current is higher due to the gate charge being
delivered at the switching frequency. See Applications Information.
Note 5: The minimum on-time condition corresponds to the on inductor
peak-to-peak ripple current ≥40% of I
MAX
(see Minimum On-Time
Considerations in the Applications Information section).
Note 6: The LTC3729E is guaranteed to meet performance specifications
from 0°C to 70°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 1: Absolute Maximum Ratings are those values beyond which the
life of a device may be impaired.
Note 2: T
J
is calculated from the ambient temperature T
A
and power
dissipation P
D
according to the following formulas:
LTC3729EG: T
J
= T
A
+ (P
D
• 95°C/W)
LTC3729EUH: T
J
= T
A
+ (P
D
• 34°C/W)
Note 3: The LTC3729 is tested in a feedback loop that servos V
ITH
to a
specified voltage and measures the resultant V
EAIN
.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Efficiency vs Output Current
(Figure 12) Efficiency vs Output Current (Figure 12) Efficiency vs Input Voltage (Figure 12)
OUTPUT CURRENT (A)
0.1
EFFICIENCY (%)
100
80
60
40
20
0
3729 G01
1 10 100
V
OUT
= 3.3V
V
EXTVCC
= 5V
I
OUT
= 20A
f = 250kHz
V
IN
= 5V
V
IN
= 8V
V
IN
= 12V
V
IN
= 20V
OUTPUT CURRENT (A)
1
EFFICIENCY (%)
70
80
3729 G02
60
50 10 100
100
90
V
EXTVCC
= 0V
V
OUT
= 3.3V
f = 250kHz
V
EXTVCC
= 5V
V
IN
(V)
5
EFFICIENCY (%)
100
90
80
70
3729 G03
10 15 20
V
OUT
= 3.3V
V
EXTVCC
= 5V
I
OUT
= 20A
f = 250kHz
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
CLKOUT Phase (Relative to Controller 1) V
PHASMD
= 0V 60 Deg
V
PHASMD
= Open 90 Deg
V
PHASMD
= 5V 120 Deg
CLK
HIGH
Clock High Output Voltage 4 V
CLK
LOW
Clock Low Output Voltage 0.2 V
PGOOD Output
V
PGL
PGOOD Voltage Low I
PGOOD
= 2mA 0.1 0.3 V
I
PGOOD
PGOOD Leakage Current V
PGOOD
= 5V ±1µA
V
PG
PGOOD Trip Level, Either Controller V
EAIN
with Respect to Set Output Voltage
V
EAIN
Ramping Negative –6 –7.5 –9.5 %
V
EAIN
Ramping Positive 6 7.5 9.5 %
Differential Amplifier
A
DA
Gain 0.995 1 1.005 V/V
CMRR
DA
Common Mode Rejection Ratio 0V < V
CM
< 5V 46 55 dB
R
IN
Input Resistance Measured at V
OS
+ Input 80 kΩ

5
LTC3729
sn3729 3729fas
Internal 5V LDO Line Reg Maximum Current Sense Threshold vs Duty Factor
Maximum Current Sense Threshold
vs Percent of Nominal Output
Voltage (Foldback)
Maximum Current Sense Threshold
vs VRUN/SS (Soft-Start) Maximum Current Sense Threshold vs Sense Common Mode Voltage Current Sense Threshold
vs ITH Voltage
INTVCC and EXTVCC Switch
Voltage vs Temperature
Supply Current vs Input Voltage
and Mode EXTVCC Voltage Drop
TYPICAL PERFOR A CE CHARACTERISTICS
UW
INPUT VOLTAGE (V)
05
0
SUPPLY CURRENT (µA)
400
1000
10 20 25
3729 G04
200
800
600
15 30 35
ON
SHUTDOWN
CURRENT (mA)
0
EXTV
CC
VOLTAGE DROP (mV)
150
200
250
40
3729 G05
100
50
010 20 30 50
TEMPERATURE (°C)
–50
INTV
CC
AND EXTV
CC
SWITCH VOLTAGE (V)
4.95
5.00
5.05
25 75
3729 G06
4.90
4.85
–25 0 50 100 125
4.80
4.70
4.75
INTV
CC
VOLTAGE
EXTV
CC
SWITCHOVER THRESHOLD
INPUT VOLTAGE (V)
0
4.8
4.9
5.1
15 25
3729 G07
4.7
4.6
510 20 30 35
4.5
4.4
5.0
INTV
CC
VOLTAGE (V)
I
LOAD
= 1mA
DUTY FACTOR (%)
0
0
V
SENSE
(mV)
25
50
75
20 40 60 80
3729 G08
100
PERCENT ON NOMINAL OUTPUT VOLTAGE (%)
0
V
SENSE
(mV)
40
50
60
100
3729 G09
30
20
025 50 75
10
80
70
V
RUN/SS
(V)
0
0
V
SENSE
(mV)
20
40
60
80
1234
3729 G10
56
V
SENSE(CM)
= 1.6V
COMMON MODE VOLTAGE (V)
0
V
SENSE
(mV)
72
76
80
4
3729 G11
68
64
60 1235
V
ITH
(V)
0
V
SENSE
(mV)
30
50
70
90
2
3729 G12
10
–10
20
40
60
80
0
–20
–30 0.5 11.5 2.5

6
LTC3729
sn3729 3729fas
Load Regulation VITH vs VRUN/SS SENSE Pins Total Source Current
Maximum Current Sense
Threshold vs Temperature
Soft-Start Up (Figure 12)
V
ITH
1V/DIV
V
OUT
2V/DIV
V
RUNSS
2V/DIV
100ms/DIV 3729 G20
Load Step (Figure 12)
I
OUT
O/30A
V
ITH
1V/DIV
10µs/DIV 3729 G21
RUN/SS Current vs Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
UW
LOAD CURRENT (A)
0
NORMALIZED V
OUT
(%)
–0.2
–0.1
4
3729 G13
–0.3
–0.4 1235
0.0 FCB = 0V
V
IN
= 15V
FIGURE 1
V
RUN/SS
(V)
0
0
V
ITH
(V)
0.5
1.0
1.5
2.0
2.5
1234
3729 G14
56
V
OSENSE
= 0.7V
V
SENSE
COMMON MODE VOLTAGE (V)
0
I
SENSE
(µA)
0
3729 G15
–50
–100 24
50
100
6
TEMPERATURE (°C)
–50 –25
70
V
SENSE
(mV)
74
80
050 75
3729 G17
72
78
76
25 100 125
TEMPERATURE (°C)
–50 –25
0
RUN/SS CURRENT (µA)
0.2
0.6
0.8
1.0
75 10050
1.8
3729 G19
0.4
0 25 125
1.2
1.4
1.6
V
OUT
200mV/DIV

7
LTC3729
sn3729 3729fas
RUN/SS (Pin 1/Pin 28): Combination of Soft-Start, Run
ControlInputand Short-Circuit DetectionTimer.Acapaci-
tor to ground at this pin sets the ramp time to full current
output. Forcing this pin below 0.8V causes the IC to shut
down all internal circuitry. All functions are disabled in
shutdown.
SENSE1
+
, SENSE2
+
(Pins 2,14/Pins 30, 12): The (+)
Input to the Differential Current Comparators. The I
TH
pin
voltage and built-in offsets between SENSE
–
and SENSE
+
pinsin conjunctionwith R
SENSE
set thecurrent tripthresh-
old.
SENSE1
–
, SENSE2
–
(Pins 3, 13/Pins 31, 11): The (–)
Input to the Differential Current Comparators.
EAIN (Pin 4/Pin 1): Input to the Error Amplifier that
compares the feedback voltage to the internal 0.8V refer-
ence voltage. This pin is normally connected to a resistive
divider from the output of the differential amplifier
(DIFFOUT).
PI FU CTIO S
UUU
Current Sense Pin Input Current
vs Temperature EXTVCC Switch Resistance vs Temperature Oscillator Frequency vs Temperature
Undervoltage Lockout
vs Temperature Shutdown Latch Thresholds vs Temperature
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TEMPERATURE (°C)
–50 –25
0
SHUTDOWN LATCH THRESHOLDS (V)
0.5
1.5
2.0
2.5
75 10050
4.5
3729 G27
1.0
0 25 125
3.0
3.5
4.0 LATCH ARMING
LATCHOFF
THRESHOLD
TEMPERATURE (°C)
–50
UNDERVOLTAGE LOCKOUT (V)
3.40
3.45
3.50
25 75
3729 G26
3.35
3.30
–25 0 50 100 125
3.25
3.20
TEMPERATURE (°C)
–50
400
500
700
25 75
3729 G25
300
200
–25 0 50 100 125
100
0
600
FREQUENCY (kHz)
V
PLLFLTR
= 2.4V
V
PLLFLTR
= 1.2V
V
PLLFLTR
= 0V
TEMPERATURE (°C)
–50 –25
0
EXTV
CC
SWITCH RESISTANCE (Ω)
4
10
050 75
3729 G24
2
8
6
25 100 125
TEMPERATURE (°C)
–50 –25
25
CURRENT SENSE INPUT CURRENT (µA)
29
35
050 75
3729 G23
27
33
31
25 100 125
V
OUT
= 5V
G Package/UH Package

8
LTC3729
sn3729 3729fas
PI FU CTIO S
UUU
PLLFLTR (Pin 5/Pin 2): The Phase-Locked Loop’s Low
Pass Filter is tied to this pin. Alternatively, this pin can be
driven with an AC or DC voltage source to vary the
frequency of the internal oscillator.
PLLIN (Pin 6/Pin 3): External Synchronization Input to
Phase Detector. This pin is internally terminated to SGND
with 50kΩ. The phase-locked loop will force the rising top
gate signal of controller 1 to be synchronized with the
rising edge of the PLLIN signal.
PHASMD (Pin 7/Pin 4): Control Input to Phase Selector
which determines the phase relationships between con-
troller 1, controller 2 and the CLKOUT signal.
I
TH
(Pin 8/Pin 5): Error Amplifier Output and Switching
RegulatorCompensationPoint.Bothcurrentcomparator’s
thresholds increase with this control voltage. The normal
voltage range of this pin is from 0V to 2.4V.
SGND (Pin 9/Pin 6): Signal Ground, common to both
controllers, must be routed separately from the input
switched current ground path to the common (–)
terminal(s) of the C
OUT
capacitor(s).
V
DIFFOUT
(Pin 10/Pin 7): Output of a Differential Amplifier
that provides true remote output voltage sensing. This pin
normally drives an external resistive divider that sets the
output voltage.
V
OS–
, V
OS+
(Pins 11, 12/Pins 8, 9): Inputs to an Opera-
tional Amplifier. Internal precision resistors capable of
being electronically switched in or out can configure it as
a differential amplifier or an uncommitted Op Amp.
PGOOD(Pin15/Pin13):Open-DrainLogicOutput.PGOOD
is pulled to ground when the voltage on the EAIN pin is not
within ±7.5% of its set point.
TG2, TG1 (Pins 16, 27/Pins 14, 26): High Current Gate
Drives for Top N-Channel MOSFETS. These are the out-
puts of floating drivers with a voltage swing equal to
INTV
CC
superimposed on the switch node voltage SW.
SW2, SW1 (Pins 17, 26/Pins 15, 25): Switch Node
Connections to Inductors. Voltage swing at these pins is
from a Schottky diode (external) voltage drop below
ground to V
IN
.
BOOST2,BOOST1(Pins18,25/Pins17,24): Bootstrapped
Supplies to the Topside Floating Drivers. Capacitors are
connectedbetweentheBoostandSwitchpins and Schot-
tky diodes are tied between the Boost and INTVCC pins.
Voltage swing at the Boost pins is from INTVCC to
(VIN + INTVCC).
BG2, BG1 (Pins 19, 23/Pins 18, 22): High Current Gate
Drives for Bottom Synchronous N-Channel MOSFETS.
Voltage swing at these pins is from ground to INTV
CC
.
PGND (Pin 20/Pin 19): Driver Power Ground. Connect to
sourcesofbottomN-channelMOSFETSandthe(–)termi-
nals of C
IN
.
INTV
CC
(Pin 21/Pin 20): Output of the Internal 5V Linear
LowDropoutRegulator andtheEXTV
CC
Switch.The driver
and control circuits are powered from this voltage source.
Decouple to power ground with a 1µF ceramic capacitor
placed directly adjacent to the IC and minimum of 4.7µF
additional tantalum or other low ESR capacitor.
EXTV
CC
(Pin 22/Pin 21): External Power Input to an
Internal Switch . This switch closes and supplies INTV
CC,
bypassing the internal low dropout regulator whenever
EXTV
CC
ishigher than 4.7V.SeeEXTV
CC
Connectionin the
Applications Information section. Do not exceed 7V on
this pin and ensure V
EXTVCC
≤V
INTVCC
.
V
IN
(Pin 24/Pin 23): Main Supply Pin. Should be closely
decoupled to the IC’s signal ground pin.
CLKOUT (Pin 28/Pin 27): Output Clock Signal available to
daisychain other controller ICs for additional MOSFET
driver stages/phases.
G Package/UH Package

9
LTC3729
sn3729 3729fas
FU CTIO AL DIAGRA
UU
W
SWITCH
LOGIC
0.80V
4.7V
5V
V
IN
V
IN
CLK2
CLK1
+
–
–
+
V
REF
PHASE LOGIC
INTERNAL
SUPPLY
PHASMD
±2µA
EXTV
CC
INTV
CC
SGND
+
5V
LDO
REG
SW
SHDN
TOP
BOOST
TG C
B
C
IN
D
B
PGND
BOT BG
INTV
CC
INTV
CC
V
IN
+
V
OUT
3729 FBD
R1
EAIN
DROP
OUT
DET
RUN
SOFT
START
BOT FCB
FORCE BOT
S
R
Q
Q
OSCILLATOR
PLLLPF
50k
EA
0.86V
0.80V
OV
1.2µA
6V
R2
–
+
R
C
4(V
FB
)
RST
SHDN
RUN/SS
I
TH
C
C
C
SS
4(V
FB
)
0.86V
SLOPE
COMP
+
–
SENSE
–
SENSE
+
INTV
CC
30k
45k
2.4V
45k
30k
I1
PHASE DET
PLLIN
CLKOUT
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
+–
R
SENSE
L
C
OUT
+
F
IN
R
LP
C
LP
0.74V
0.86V
A1
+
–
DIFFOUT
V
OS+
V
OS–
40k 40k
40k 40k
+
–
+
–
EAIN
PGOOD

10
LTC3729
sn3729 3729fas
OPERATIO
U
(Refer to Functional Diagram)
Main Control Loop
The LTC3729 uses a constant frequency, current mode
step-down architecture. During normal operation, the top
MOSFET is turned on each cycle when the oscillator sets
the RS latch, and turned off when the main current
comparator, I1, resets the RS latch. The peak inductor
current at which I1 resets the RS latch is controlled by the
voltage on the I
TH
pin, which is the output of the error
amplifier EA. The differential amplifier, A1, produces a
signal equal to the differential voltage sensed across the
output capacitor but re-references it to the internal signal
ground(SGND)reference.The EAIN pin receives a portion
of this voltage feedback signal at the DIFFOUT pin which
is compared to the internal reference voltage by the EA.
When the load current increases, it causes a slight de-
crease in the EAIN pin voltage relative to the 0.8V refer-
ence, which in turn causes the I
TH
voltage to increase until
the average inductor current matches the new load cur-
rent. After the top MOSFET has turned off, the bottom
MOSFET is turned on for the rest of the period.
The top MOSFET drivers are biased from floating boot-
strap capacitor C
B
, which normally is recharged during
each off cycle through an external Schottky diode. When
V
IN
decreasestoavoltageclosetoV
OUT
,however,theloop
may enter dropout and attempt to turn on the top MOSFET
continuously. A dropout detector detects this condition
and forces the top MOSFET to turn off for about 400ns
every 10th cycle to recharge the bootstrap capacitor.
The main control loop is shut down by pulling Pin 1 (RUN/
SS) low. Releasing RUN/SS allows an internal 1.2µA
current source to charge soft-start capacitor C
SS
. When
C
SS
reaches1.5V,themaincontrolloopisenabledwiththe
I
TH
voltageclampedatapproximately30%ofitsmaximum
value. As C
SS
continues to charge, I
TH
is gradually re-
leased allowing normal operation to resume. When the
RUN/SS pin is low, all LTC3729 functions are shut down.
IfV
OUT
hasnotreached70%ofits nominalvaluewhenC
SS
has charged to 4.1V, an overcurrent latchoff can be
invoked as described in the Applications Information
section.
Low Current Operation
The LTC3729 operates in a continuous, PWM control
mode. The resulting operation at low output currents
optimizestransientresponseattheexpenseof substantial
negative inductor current during the latter part of the
period. The level of ripple current is determined by the
inductor value, input voltage, output voltage, and fre-
quency of operation.
Frequency Synchronization
The phase-locked loop allows the internal oscillator to be
synchronized to an external source via the PLLIN pin. The
output of the phase detector at the PLLFLTR pin is also the
DC frequency control input of the oscillator that operates
over a 250kHz to 550kHz range corresponding to a DC
voltageinputfrom0Vto2.4V.Whenlocked,thePLLaligns
the turn on of the top MOSFET to the rising edge of the
synchronizingsignal.WhenPLLINisleftopen,thePLLFLTR
pingoeslow,forcingtheoscillatortominimumfrequency.
The internal master oscillator runs at a frequency twelve
times that of each controller’s frequency. The PHASMD
pin determines the relative phases between the internal
controllers as well as the CLKOUT signal as shown in
Table␣ 1. The phases tabulated are relative to zero phase
being defined as the rising edge of the top gate (TG1)
driver output of controller 1.
Table 1.
V
PHASMD
GND OPEN INTV
CC
Controller 2 180°180°240°
CLKOUT 60°90°120°
The CLKOUT signal can be used to synchronize additional
power stages in a multiphase power supply solution
feeding a single, high current output or separate outputs.
InputcapacitanceESR requirements and efficiency losses
are substantially reduced because the peak current drawn
from the input capacitor is effectively divided by the
number of phases used and power loss is proportional to
the RMS current squared. A two stage, single output
voltage implementation can reduce input path power loss
by 75% and radically reduce the required RMS current
rating of the input capacitor(s).

11
LTC3729
sn3729 3729fas
OPERATIO
U
(Refer to Functional Diagram)
INTV
CC
/EXTV
CC
Power
Power for the top and bottom MOSFET drivers and most
of the IC circuitry is derived from INTV
CC
. When the
EXTV
CC
pin is left open, an internal 5V low dropout
regulator supplies INTV
CC
power. If the EXTV
CC
pin is
taken above 4.7V, the 5V regulator is turned off and an
internalswitchis turned on connecting EXTV
CC
toINTV
CC
.
This allows the INTV
CC
power to be derived from a high
efficiency external source such as the output of the regu-
lator itself or a secondary winding, as described in the
Applications Information section. An external Schottky
diode can be used to minimize the voltage drop from
EXTV
CC
to INTV
CC
in applications requiring greater than
the specified INTV
CC
current. Voltages up to 7V can be
applied to EXTV
CC
for additional gate drive capability.
Differential Amplifier
This amplifier provides true differential output voltage
sensing. Sensing both V
OUT+
and V
OUT–
benefits regula-
tion in high current applications and/or applications hav-
ing electrical interconnection losses.
Power Good (PGOOD)
The PGOOD pin is connected to the drain of an internal
MOSFET. The MOSFET turns on when the output is not
within ±7.5% of its nominal output level as determined by
the feedback divider. When the output is within ±7.5% of
its nominal value, the MOSFET is turned off within 10µs
and the PGOOD pin should be pulled up by an external
resistor to a source of up to 7V.
Short-Circuit Detection
The RUN/SS capacitor is used initially to limit the inrush
current from the input power source. Once the controllers
have been given time, as determined by the capacitor on
the RUN/SS pin, to charge up the output capacitors and
provide full load current, the RUN/SS capacitor is then
usedasashort-circuittimeoutcircuit.Iftheoutputvoltage
falls to less than 70% of its nominal output voltage the
RUN/SS capacitor begins discharging assuming that the
output is in a severe overcurrent and/or short-circuit
condition. If the condition lasts for a long enough period
as determined by the size of the RUN/SS capacitor, the
controller will be shut down until the RUN/SS pin voltage
is recycled. This built-in latchoff can be overidden by
providing a >5µA pull-up current at a compliance of 5V to
the RUN/SS pin. This current shortens the soft-start
period but also prevents net discharge of the RUN/SS
capacitor during a severe overcurrent and/or short-circuit
condition. Foldback current limiting is activated when the
outputvoltagefallsbelow70%ofitsnominallevelwhether
or not the short-circuit latchoff circuit is enabled.
APPLICATIO S I FOR ATIO
WUUU
Thebasic LTC3729applicationcircuit isshownin Figure␣ 1
on the first page. External component selection is driven
by the load requirement, and begins with the selection of
R
SENSE1, 2
. Once R
SENSE1, 2
are known, L1 and L2 can be
chosen. Next, the power MOSFETs and D1 and D2 are
selected. The operating frequency and the inductor are
chosen based mainly on the amount of ripple current.
Finally, C
IN
is selected for its ability to handle the input
ripple current (that PolyPhase operation minimizes) and
C
OUT
is chosen with low enough ESR to meet the output
ripplevoltageandloadstepspecifications(alsominimized
with PolyPhase). The circuit shown in Figure␣ 1 can be
configured for operation up to an input voltage of 28V
(limited by the external MOSFETs).
R
SENSE
Selection For Output Current
R
SENSE1, 2
are chosen based on the required output
current. The LTC3729 current comparator has a maxi-
mum threshold of 75mV/R
SENSE
and an input common
mode range of SGND to 1.1( INTV
CC
). The current com-
parator threshold sets the peak inductor current, yielding
a maximum average output current I
MAX
equal to the peak
value less half the peak-to-peak ripple current, ∆I
L
.
Allowing a margin for variations in the LTC3729 and
external component values yields:
R
SENSE
= (50mV/I
MAX
)N
where N = number of stages.

12
LTC3729
sn3729 3729fas
APPLICATIO S I FOR ATIO
WUUU
When using the controller in very low dropout conditions,
the maximum output current level will be reduced due to
internal slope compensation required to meet stability
criterionforbuckregulatorsoperatingatgreaterthan50%
duty factor. A curve is provided to estimate this reduction
in peak output current level depending upon the operating
duty factor.
Operating Frequency
The LTC3729 uses a constant frequency, phase-lockable
architecture with the frequency determined by an internal
capacitor.Thiscapacitorischargedbyafixedcurrentplus
an additional current which is proportional to the voltage
applied to the PLLFLTR pin. Refer to Phase-Locked Loop
and Frequency Synchronization in the Applications Infor-
mation section for additional information.
A graph for the voltage applied to the PLLFLTR pin vs
frequency is given in Figure␣ 2. As the operating frequency
isincreasedthegatechargelosseswillbehigher,reducing
efficiency (see Efficiency Considerations). The maximum
switching frequency is approximately 550kHz.
anyone ever choose to operate at lower frequencies with
larger components? The answer is efficiency. A higher
frequency generally results in lower efficiency because of
MOSFET gate charge and transition losses. In addition to
this basic tradeoff, the effect of inductor value on ripple
current and low current operation must also be consid-
ered. The PolyPhase approach reduces both input and
output ripple currents while optimizing individual output
stagestorunatalowerfundamentalfrequency,enhancing
efficiency.
Theinductorvaluehasa directeffectonripplecurrent.The
inductor ripple current ∆I
L
per individual section, N,
decreases with higher inductance or frequency and in-
creases with higher V
IN
or V
OUT
:
∆IV
fL
V
V
LOUT OUT
IN
=−





1
where f is the individual output stage operating frequency.
InaPolyPhaseconverter,thenetripplecurrentseenbythe
output capacitor is much smaller than the individual
inductor ripple currents due to the ripple cancellation. The
details on how to calculate the net output ripple current
can be found in Application Note 77.
Figure 3 shows the net ripple current seen by the output
capacitors for the different phase configurations. The
outputripplecurrentisplottedforafixedoutputvoltageas
the duty factor is varied between 10% and 90% on the
x-axis. The output ripple current is normalized against the
inductor ripple current at zero duty factor. The graph can
be used in place of tedious calculations. As shown in
Figure␣ 3, the zero output ripple current is obtained when:
V
V
k
N
OUT
IN
=
where k = 1, 2, …, N – 1
Sothe number ofphasesused canbeselected tominimize
the output ripple current and therefore the output ripple
voltage at the given input and output voltages. In applica-
tions having a highly varying input voltage, additional
phases will produce the best results.
Figure 2. Operating Frequency vs VPLLFLTR
OPERATING FREQUENCY (kHz)
200 250 300 350 550400 450 500
PLLFLTR PIN VOLTAGE (V)
3729 F02
2.5
2.0
1.5
1.0
0.5
0
Inductor Value Calculation and Output Ripple Current
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. So why would

13
LTC3729
sn3729 3729fas
inductor ripple current and consequent output voltage
ripple. Do not allow the core to saturate!
Molypermalloy (from Magnetics, Inc.) is a very good, low
losscorematerialfortoroids, butitismoreexpensivethan
ferrite. A reasonable compromise from the same manu-
facturer is Kool Mµ. Toroids are very space efficient,
especially when you can use several layers of wire. Be-
cause they lack a bobbin, mounting is more difficult.
However, designs for surface mount are available which
do not increase the height significantly.
Power MOSFET, D1 and D2 Selection
Two external power MOSFETs must be selected for each
controller with the LTC3729: One N-channel MOSFET for
the top (main) switch, and one N-channel MOSFET for the
bottom (synchronous) switch.
The peak-to-peak drive levels are set by the INTV
CC
volt-
age. This voltage is typically 5V during start-up (see
EXTV
CC
PinConnection).Consequently,logic-levelthresh-
old MOSFETs must be used in most applications. The only
exception is if low input voltage is expected (V
IN
< 5V);
then, sublogic-level threshold MOSFETs (V
GS(TH)
< 3V)
should be used. Pay close attention to the BV
DSS
specifi-
cation for the MOSFETs as well; most of the logic-level
MOSFETs are limited to 30V or less.
SelectioncriteriaforthepowerMOSFETs includethe “ON”
resistance R
DS(ON)
, reverse transfer capacitance C
RSS
,
input voltage, and maximum output current. When the
LTC3729is operating incontinuousmode the dutyfactors
for the top and bottom MOSFETs of each output stage are
given by:
Main SwitchDuty Cycle V
V
OUT
IN
=
Synchronous SwitchDuty Cycle VV
V
IN OUT
IN
=




–
The MOSFET power dissipations at maximum output
current are given by:
Kool Mµis a registered trademark of Magnetics, Inc.
APPLICATIO S I FOR ATIO
WUUU
Figure 3. Normalized Peak Output Current vs
Duty Factor [IRMS ≈0.3 (∆IO(P–P))]
DUTY FACTOR (V
OUT
/V
IN
)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
3729 F03
6-PHASE
4-PHASE
3-PHASE
2-PHASE
1-PHASE
∆I
O(P-P)
V
O
/fL
Accepting larger values of ∆I
L
allows the use of low
inductances,butcan resultinhigheroutput voltage ripple.
A reasonable starting point for setting ripple current is
∆I
L
= 0.4(I
OUT
)/N, where N is the number of channels and
I
OUT
is the total load current. Remember, the maximum
∆I
L
occurs at the maximum input voltage. The individual
inductor ripple currents are constant determined by the
inductor, input and output voltages.
Inductor Core Selection
Once the values for L1 and L2 are known, the type of
inductor must be selected. High efficiency converters
generally cannot afford the core loss found in low cost
powdered iron cores, forcing the use of more expensive
ferrite, molypermalloy, or Kool Mµ
®
cores. Actual core
loss is independent of core size for a fixed inductor value,
but it is very dependent on inductance selected. As induc-
tance increases, core losses go down. Unfortunately,
increased inductance requires more turns of wire and
therefore copper losses will increase.
Ferrite designs have very low core loss and are preferred
at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design cur-
rent is exceeded. This results in an abrupt increase in

14
LTC3729
sn3729 3729fas
PV
V
I
NR
kV I
NCf
MAIN OUT
IN
MAX DS ON
IN MAX RSS
=



+
()
+
()





()()
2
2
1δ()
PVV
V
I
NR
SYNC IN OUT
IN
MAX DS ON
=



+
()
–
()
2
1δ
where δis the temperature dependency of R
DS(ON)
, k is a
constant inversely related to the gate drive current and N
is the number of stages.
Both MOSFETs have I
2
R losses but the topside N-channel
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V
IN
< 20V the
high current efficiency generally improves with larger
MOSFETs, while for V
IN
> 20V the transition losses rapidly
increasetothepointthattheuseofahigherR
DS(ON)
device
with lower C
RSS
actual provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during a
short-circuit when the synchronous switch is on close to
100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs. Temperature curve, but
δ= 0.005/°C can be used as an approximation for
low voltage MOSFETs. C
RSS
is usually specified in the
MOSFET characteristics. The constant k = 1.7 can be used
to estimate the contributions of the two terms in the main
switch dissipation equation.
TheSchottkydiodes,D1andD2showninFigure1conduct
during the dead-time between the conduction of the two
large power MOSFETs. This helps prevent the body diode
of the bottom MOSFET from turning on, storing charge
during the dead-time, and requiring a reverse recovery
periodwhichwouldreduceefficiency.A1Ato3A(depend-
ing on output current) Schottky diode is generally a good
compromise for both regions of operation due to the
relatively small average current. Larger diodes result in
additional transition losses due to their larger junction
capacitance.
C
IN
and C
OUT
Selection
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V
OUT
/
V
IN
. A low ESR input capacitor sized for the maximum
RMS current must be used. The details of a close form
equation can be found in Application Note 77. Figure 4
shows the input capacitor ripple current for different
phase configurations with the output voltage fixed and
inputvoltage varied.Theinput ripplecurrentis normalized
against the DC output current. The graph can be used in
place of tedious calculations. The minimum input ripple
current can be achieved when the product of phase num-
berandoutput voltage, N(V
OUT
),isapproximately equal to
the input voltage V
IN
or:
V
V
k
N
OUT
IN =
where k = 1, 2, …, N – 1
So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages.
In the graph of Figure 4, the local maximum input RMS
capacitor currents are reached when:
V
V
k
N
OUT
IN
=−21
2
where k = 1, 2, …, N
APPLICATIO S I FOR ATIO
WUUU
Figure 4. Normalized Input RMS Ripple Current vs
Duty Factor for 1 to 6 Output Stages
DUTY FACTOR (V
OUT
/V
IN
)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
0.6
0.5
0.4
0.3
0.2
0.1
0
3729 F04
RMS INPUT RIPPLE CURRNET
DC LOAD CURRENT
6-PHASE
4-PHASE
3-PHASE
2-PHASE
1-PHASE
These worst-case conditions are commonly used for
design because even significant deviations do not offer
much relief. Note that capacitor manufacturer’s ripple
current ratings are often based on only 2000 hours of life.

15
LTC3729
sn3729 3729fas
This makes it advisable to further derate the capacitor, or
to choose a capacitor rated at a higher temperature than
required. Several capacitors may also be paralleled to
meet size or height requirements in the design. Always
consult the capacitor manufacturer if there is any
question.
The graph shows that the peak RMS input current is
reduced linearly, inversely proportional to the number, N
of stages used. It is important to note that the efficiency
loss is proportional to the input RMS current squared and
therefore a 2-stage implementation results in 75% less
power loss when compared to a single phase design.
Battery/input protection fuse resistance (if used), PC
board trace and connector resistance losses are also
reduced by the reduction of the input ripple current in a
PolyPhase system. The required amount of input capaci-
tance is further reduced by the factor, N, due to the
effective increase in the frequency of the current pulses.
The selection of C
OUT
is driven by the required effective
series resistance (ESR). Typically once the ESR require-
ment has been met, the RMS current rating generally far
exceeds the I
RIPPLE(P-P)
requirements. The steady state
output ripple (∆V
OUT
) is determined by:
∆∆V I ESR NfC
OUT RIPPLE OUT
≈+





1
8
Where f = operating frequency of each stage, N is the
number of phases, C
OUT
= output capacitance, and
∆I
RIPPLE
= combined inductor ripple currents.
The output ripple varies with input voltage since ∆I
L
is a
functionofinputvoltage.Theoutputripplewillbelessthan
50mV at max V
IN
with ∆I
L
= 0.4I
OUT(MAX)
/N assuming:
C
OUT
required ESR < 2N(R
SENSE
) and
C
OUT
> 1/(8Nf)(R
SENSE
)
The emergence of very low ESR capacitors in small,
surface mount packages makes very physically small
implementations possible. The ability to externally
compensate the switching regulator loop using the I
TH
pin(OPTI-LOOP compensation) allows a much wider
selection of output capacitor types. OPTI-LOOP compen-
sationeffectively removesconstraints onoutput capacitor
ESR. The impedance characteristics of each capacitor
type are significantly different than an ideal capacitor and
therefore require accurate modeling or bench evaluation
during design.
Manufacturers such as Nichicon, United Chemicon and
Sanyoshouldbeconsideredforhighperformancethrough-
hole capacitors. The OS-CON semiconductor dielectric
capacitor available from Sanyo and the Panasonic SP
surface mount types have the lowest (ESR)(size) product
of any aluminum electrolytic at a somewhat higher price.
An additional ceramic capacitor in parallel with OS-CON
type capacitors is recommended to reduce the inductance
effects.
In surface mount applications, multiple capacitors may
have to be paralleled to meet the ESR or RMS current
handling requirements of the application. Aluminum
electrolytic and dry tantalum capacitors are both available
in surface mount configurations. New special polymer
surfacemountcapacitors offer very low ESRalsobuthave
muchlower capacitive densityperunit volume. Inthecase
oftantalum,itiscriticalthatthecapacitorsaresurgetested
for use in switching power supplies. Several excellent
choices are the AVX TPS, AVX TPSV or the KEMET T510
seriesofsurfacemounttantalums,availableincaseheights
ranging from 2mm to 4mm. Other capacitor types include
Sanyo OS-CON, Nichicon PL series and Sprague 595D
series.Consultthe manufacturer for otherspecificrecom-
mendations. A combination of capacitors will often result
in maximizing performance and minimizing overall cost
and size.
INTV
CC
Regulator
An internal P-channel low dropout regulator produces 5V
at the INTV
CC
pin from the V
IN
supply pin. The INTV
CC
regulator powers the drivers and internal circuitry of the
LTC3729.TheINTV
CC
pinregulatorcansupplyupto50mA
peak and must be bypassed to power ground with a
minimum of 4.7µF tantalum or electrolytic capacitor. An
additional 1µF ceramic capacitor placed very close to the
IC is recommended due to the extremely high instanta-
neous currents required by the MOSFET gate drivers.
High input voltage applications in which large MOSFETs
are being driven at high frequencies may cause the
APPLICATIO S I FOR ATIO
WUUU

16
LTC3729
sn3729 3729fas
maximum junction temperature rating for the LTC3729 to
be exceeded. The supply current is dominated by the gate
charge supply current, in addition to the current drawn
from the differential amplifier output. The gate charge is
dependent on operating frequency as discussed in the
Efficiency Considerations section. The supply current can
either be supplied by the internal 5V regulator or via the
EXTV
CC
pin. When the voltage applied to the EXTV
CC
pin
is less than 4.7V, all of the INTV
CC
load current is supplied
by the internal 5V linear regulator. Power dissipation for
the IC is higher in this case by (I
IN
)(V
IN
– INTV
CC
) and
efficiency is lowered. The junction temperature can be
estimated by using the equations given in Note 1 of the
Electrical Characteristics. For example, the LTC3729 V
IN
current is limited to less than 24mA from a 24V supply:
T
J
= 70°C + (24mA)(24V)(95°C/W) = 125°C
Use of the EXTV
CC
pin reduces the junction temperature
to:
T
J
= 70°C + (24mA)(5V)(95°C/W) = 81.4°C
The input supply current should be measured while the
controller is operating in continuous mode at maximum
V
IN
and the power dissipation calculated in order to pre-
vent the maximum junction temperature from being ex-
ceeded.
EXTV
CC
Connection
The LTC3729 contains an internal P-channel MOSFET
switch connected between the EXTV
CC
and INTV
CC
pins.
When the voltage applied to EXTV
CC
rises above 4.7V, the
internal regulator is turned off and the switch closes,
connecting the EXTV
CC
pin to the INTV
CC
pin thereby
supplying internal and MOSFET gate driving power. The
switch remains closed as long as the voltage applied to
EXTV
CC
remains above 4.5V. This allows the MOSFET
driver and control power to be derived from the output
during normal operation (4.7V < V
EXTVCC
< 7V) and from
the internal regulator when the output is out of regulation
(start-up, short-circuit). Do not apply greater than 7V to
the EXTV
CC
pin and ensure that EXTV
CC
< V
IN
+ 0.3V when
using the application circuits shown. If an external voltage
source is applied to the EXTV
CC
pin when the V
IN
supply is
not present, a diode can be placed in series with the
LTC3729’s V
IN
pin and a Schottky diode between the
EXTV
CC
andtheV
IN
pin,topreventcurrentfrombackfeeding
V
IN
.
Significant efficiency gains can be realized by powering
INTV
CC
from the output, since the V
IN
current resulting
from the driver and control currents will be scaled by the
ratio: (Duty Factor)/(Efficiency). For 5V regulators this
means connecting the EXTV
CC
pin directly to V
OUT
. How-
ever, for 3.3V and other lower voltage regulators, addi-
tionalcircuitryisrequiredtoderiveINTV
CC
powerfromthe
output.
The following list summarizes the four possible connec-
tions for EXTV
CC:
1. EXTV
CC
left open (or grounded). This will cause INTV
CC
to be powered from the internal 5V regulator resulting in
a significant efficiency penalty at high input voltages.
2. EXTV
CC
connected directly to V
OUT
. This is the normal
connection for a 5V regulator and provides the highest
efficiency.
3. EXTV
CC
connected to an external supply. If an external
supply is available in the 5V to 7V range, it may be used to
powerEXTV
CC
providing it iscompatiblewith the MOSFET
gatedriverequirements.V
IN
mustbegreaterthanorequal
to the voltage applied to the EXTV
CC
pin.
4. EXTV
CC
connected to an output-derived boost network.
For3.3Vandotherlow voltage regulators, efficiency gains
can still be realized by connecting EXTV
CC
to an output-
derived voltage which has been boosted to greater than
4.7V but less than 7V. This can be done with either the
inductive boost winding as shown in Figure 5a or the
capacitive charge pump shown in Figure 5b. The charge
pump has the advantage of simple magnetics.
Topside MOSFET Driver Supply (C
B
,D
B
) (Refer to
Functional Diagram)
External bootstrap capacitors C
B1
and C
B2
connected to
the BOOST1 and BOOST2 pins supply the gate drive
voltages for the topside MOSFETs. Capacitor C
B
in the
Functional Diagram is charged though diode D
B
from
INTV
CC
whentheSWpinislow.WhenthetopsideMOSFET
turns on, the driver places the C
B
voltage across the
gate-source of the desired MOSFET. This enhances the
MOSFETandturnsonthe topside switch. The switch node
APPLICATIO S I FOR ATIO
WUUU

17
LTC3729
sn3729 3729fas
voltage, SW, rises to V
IN
and the BOOST pin rises to V
IN
+
V
INTVCC
. The value of the boost capacitor C
B
needs to be
30 to 100 times that of the total input capacitance of the
topsideMOSFET(s).ThereversebreakdownofD
B
mustbe
greater than V
IN(MAX).
The final arbiter when defining the best gate drive ampli-
tude level will be the input supply current. If a change is
made that decreases input current, the efficiency has
improved. If the input current does not change then the
efficiency has not changed either.
Differential Amplifier/Output Voltage
The LTC3729 has a true remote voltage sense capablity.
Thesensingconnectionsshouldbereturnedfromthe load
back to the differential amplifier’s inputs through a com-
mon, tightly coupled pair of PC traces. The differential
amplifier rejects common mode signals capacitively or
inductively radiated into the feedback PC traces as well as
ground loop disturbances. The differential amplifier
output signal is divided down and compared with the
internal precision 0.8V voltage reference by the error
amplifier.
The differential amplifier utilizes a set of internal precision
resistors to enable precision instrumentation-type mea-
surement of the output voltage. The output is an NPN
emitter follower without any internal pull-down current. A
DC resistive load to ground is required in order to sink
current. The output will swing from 0V to 10V. (V
IN
≥
V
DIFFOUT
␣ +␣ 2V.) The output voltage is set by an external
resistive divider according to the following formula:
VV
R
R
OUT =+





08 1 2
1
.
where R1 and R2 are defined in Figure 2.
Soft-Start/Run Function
The RUN/SS pin provides three functions: 1) Run/Shut-
down,2)soft-startand3)adefeatableshort-circuitlatchoff
timer. Soft-start reduces the input power sources’ surge
currents by gradually increasing the controller’s current
limit I
TH(MAX)
. The latchoff timer prevents very short,
extreme load transients from tripping the overcurrent
latch. A small pull-up current (>5µA) supplied to the RUN/
SS pin will prevent the overcurrent latch from operating.
The following explanation describes how the functions
operate.
An internal 1.2µA current source charges up the C
SS
capacitor
.
When the voltage on RUN/SS reaches 1.5V, the
controlleris permitted tostartoperating. Asthevoltage on
RUN/SS increases from 1.5V to 3.0V, the internal current
limit is increased from 25mV/R
SENSE
to 75mV/R
SENSE
.
The output current limit ramps up slowly, taking an
additional 1.4µs/µF to reach full current. The output
current thus ramps up slowly, reducing the starting surge
current required from the input power supply. If RUN/SS
hasbeenpulledallthewaytogroundthereisadelaybefore
starting of approximately:
tV
ACsFC
DELAY SS SS
=µ=µ
()
15
12 125
.
../
APPLICATIO S I FOR ATIO
WUUU
Figure 5a. Secondary Output Loop and EXTVCC Connection Figure 5b. Capacitive Charge Pump for EXTVCC
3729 F05a
V
IN
TG1
N-CH
1N4148
N-CH
BG1
PGND
LTC3729
SW1
EXTV
CC
OPTIONAL EXTV
CC
CONNECTION
5V < V
SEC
< 7V
T1
R
SENSE
V
SEC
6.8V
V
OUT
V
IN
+
C
IN
+
1µF
+
C
OUT
3729 F05b
V
IN
TG1
N-CH
N-CH
BG1
PGND
LTC3729
SW1
EXTV
CC
L1
R
SENSE
BAT85
BAT85
BAT85 0.22µF
V
OUT
V
IN
+
C
IN
+
1µF
+
C
OUT
VN2222LL

18
LTC3729
sn3729 3729fas
The time for the output current to ramp up is then:
tVV
ACsFC
RAMP SS SS
=−µ=µ
()
315
12 125
.
../
By pulling the RUN/SS pin below 0.8V the LTC3729 is put
into low current shutdown (I
Q
< 40µA). RUN/SS can be
driven directly from logic as shown in Figure 6. Diode D1
in Figure 6 reduces the start delay but allows C
SS
to ramp
up slowly providing the soft-start function. The RUN/SS
pin has an internal 6V zener clamp (see Functional Dia-
gram).
Fault Conditions: Overcurrent Latchoff
The RUN/SS pin also provides the ability to latch off the
controllerswhenanovercurrentconditionisdetected.The
RUN/SS capacitor, C
SS
, is used initially to limit the inrush
currentofbothcontrollers. After the controllers have been
started and been given adequate time to charge up the
output capacitors and provide full load current, the RUN/
SS capacitor is used for a short-circuit timer. If the output
voltagefallsto less than70%of its nominalvalueafterC
SS
reaches 4.1V, C
SS
begins discharging on the assumption
that the output is in an overcurrent condition. If the
condition lasts for a long enough period as determined by
the size of C
SS
, the controller will be shut down until the
RUN/SS pin voltage is recycled. If the overload occurs
during start-up, the time can be approximated by:
t
LO1
≈(C
SS
• 0.6V)/(1.2µA) = 5 • 10
5
(C
SS
)
Iftheoverloadoccursafterstart-up,thevoltageonC
SS
will
continue charging and will provide additional time before
latching off:
t
LO2
≈(C
SS
• 3V)/(1.2µA) = 2.5 • 10
6
(C
SS
)
This built-in overcurrent latchoff can be overridden by
providing a pull-up resistor, R
SS
, to the RUN/SS pin as
shown in Figure 6. This resistance shortens the soft-start
period and prevents the discharge of the RUN/SS capaci-
tor during a severe overcurrent and/or short-circuit
condition. When deriving the 5µA current from V
IN
as in
the figure, current latchoff is always defeated. Diode-
connecting this pull-up resistor to INTV
CC
, as in Figure␣ 6,
eliminates any extra supply current during shutdown
while eliminating the INTV
CC
loading from preventing
controller start-up.
Why should you defeat current latchoff? During the
prototypingstageofadesign,theremaybeaproblemwith
noise pickup or poor layout causing the protection circuit
to latch off the controller. Defeating this feature allows
troubleshooting of the circuit and PC layout. The internal
short-circuit and foldback current limiting still remains
active, thereby protecting the power supply system from
failure. A decision can be made after the design is com-
plete whether to rely solely on foldback current limiting or
to enable the latchoff feature by removing the pull-up
resistor.
The value of the soft-start capacitor C
SS
may need to be
scaled with output voltage, output capacitance and load
current characteristics. The minimum soft-start capaci-
tance is given by:
C
SS
> (C
OUT
)(V
OUT
)(10
-4
)(R
SENSE
)
The minimum recommended soft-start capacitor of C
SS
=
0.1µF will be sufficient for most applications.
Phase-Locked Loop and Frequency Synchronization
The LTC3729 has a phase-locked loop comprised of an
internal voltage controlled oscillator and phase detector.
This allows the top MOSFET turn-on to be locked to the
rising edge of an external source. The frequency range of
the voltage controlled oscillator is ±50% around the
center frequency f
O
. A voltage applied to the PLLFLTR pin
of 1.2V corresponds to a frequency of approximately
400kHz. The nominal operating frequency range of the
LTC3729 is 250kHz to 550kHz.
APPLICATIO S I FOR ATIO
WUUU
Figure 6. RUN/SS Pin Interfacing
3.3V OR 5V RUN/SS
V
IN
INTV
CC
RUN/SS
D1
D1*
C
SS
R
SS
*
C
SS
R
SS
*
3729 F06
*OPTIONAL TO DEFEAT OVERCURRENT LATCHOFF

19
LTC3729
sn3729 3729fas
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the
external and internal oscillators. This type of phase detec-
tor will not lock up on input frequencies close to the
harmonics of the VCO center frequency. The PLL hold-in
range, ∆f
H
, is equal to the capture range, ∆f
C:
∆f
H
= ∆f
C
= ±0.5 f
O
(250kHz-550kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
filter network on the PLLFLTR pin. A simplified block
diagram is shown in Figure 7.
APPLICATIO S I FOR ATIO
WUUU
Figure 7. Phase-Locked Loop Block Diagram
EXTERNAL
OSC
2.4V R
LP
10k
C
LP
OSC
DIGITAL
PHASE/
FREQUENCY
DETECTOR
PHASE
DETECTOR
PLLIN
3729 F07
PLLFLTR
50k
If the external frequency (f
PLLIN
) is greater than the oscil-
lator frequency f
0SC
, current is sourced continuously,
pulling up the PLLFLTR pin. When the external frequency
is less than f
0SC
, current is sunk continuously, pulling
down the PLLFLTR pin. If the external and internal
frequencies are the same but exhibit a phase difference,
the current sources turn on for an amount of time corre-
sponding to the phase difference. Thus the voltage on the
PLLFLTR pin is adjusted until the phase and frequency of
the external and internal oscillators are identical. At this
stable operating point the phase comparator output is
open and the filter capacitor C
LP
holds the voltage. The
LTC3729 PLLIN pin must be driven from a low impedance
source such as a logic gate located close to the pin. When
using multiple LTC3729’s for a phase-locked system, the
PLLFLTR pin of the master oscillator should be biased at
a voltage that will guarantee the slave oscillator(s) ability
to lock onto the master’s frequency. A DC voltage of 0.7V
to 1.7V applied to the master oscillator’s PLLFLTR pin is
recommended in order to meet this requirement. The
resultantoperatingfrequencywillbeapproximately500kHz.
The loop filter components (C
LP
, R
LP
) smooth out the
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
components C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
=10kΩand C
LP
is 0.01µF to
0.1µF.
Minimum On-Time Considerations
Minimum on-time t
ON(MIN)
is the smallest time duration
thatthe LTC3729iscapableofturning onthe topMOSFET.
It is determined by internal timing delays and the gate
chargerequiredtoturnonthetopMOSFET.Lowdutycycle
applications may approach this minimum on-time limit
and care should be taken to ensure that:
tV
Vf
ON MIN OUT
IN
()
<
()
Ifthe duty cyclefallsbelow whatcanbe accommodatedby
the minimum on-time, the LTC3729 will begin to skip
cycles resulting in nonconstant frequency operation. The
output voltage will continue to be regulated, but the ripple
current and ripple voltage will increase.
The minimum on-time for the LTC3729 is approximately
100ns. However, as the peak sense voltage decreases the
minimum on-time gradually increases. This is of particu-
lar concern in forced continuous applications with low
ripple current at light loads. If the duty cycle drops below
the minimum on-time limit in this situation,
a significant amount of cycle skipping can occur with
correspondingly larger current and voltage ripple.
If an application can operate close to the minimum on-
time limit, an inductor must be chosen that has a low
enough inductance to provide sufficient ripple amplitude
to meet the minimum on-time requirement. As a general
rule, keep the inductor ripple current of each phase equal
to or greater than 15% of I
OUT(MAX)
/N at V
IN(MAX)
.

20
LTC3729
sn3729 3729fas
Voltage Positioning
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifications. Voltage positioning can easily be added to
the LTC3729 by loading the I
TH
pin with a resistive divider
having a Thevenin equivalent voltage source equal to the
midpoint operating voltage range of the error amplifier, or
1.2V (see Figure 8).
2) INTV
CC
regulator current, 3) I
2
R losses and 4) Topside
MOSFET transition losses.
1) The V
IN
current has two components: the first is the
DC supply current given in the Electrical Characteristics
table, which excludes MOSFET driver and control
currents; the second is the current drawn from the differ-
ential amplifier output. V
IN
current typically results in a
small (<0.1%) loss.
2) INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results from
switching the gate capacitance of the power MOSFETs.
Each time a MOSFET gate is switched from low to high to
low again, a packet of charge dQ moves from INTV
CC
to
ground. The resulting dQ/dt is a current out of INTV
CC
that
is typically much larger than the control circuit current. In
continuous mode, I
GATECHG
= (Q
T
+ Q
B
), where Q
T
and Q
B
are the gate charges of the topside and bottom side
MOSFETs.
SupplyingINTV
CC
powerthroughthe EXTV
CC
switchinput
from an output-derived source will scale the V
IN
current
required for the driver and control circuits by the ratio
(Duty Factor)/(Efficiency). For example, in a 20V to 5V
application, 10mA of INTV
CC
current results in approxi-
mately 3mA of V
IN
current. This reduces the mid-current
loss from 10% or more (if the driver was powered directly
from V
IN
) to only a few percent.
3) I
2
R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor,
and input and output capacitor ESR. In continuous mode
the average output current flows through L and R
SENSE
,
but is “chopped” between the topside MOSFET and the
synchronous MOSFET. If the two MOSFETs have approxi-
mately the same R
DS(ON)
, then the resistance of one
MOSFET can simply be summed with the resistances of L,
R
SENSE
and ESR to obtain I
2
R losses. For example, if each
R
DS(ON)
=10mΩ, R
L
=10mΩ, and R
SENSE
=5mΩ, then the
total resistance is 25mΩ. This results in losses ranging
from 2% to 8% as the output current increases from 3A to
15A per output stage for a 5V output, or a 3% to 12% loss
per output stage for a 3.3V output. Efficiency varies as
the inverse square of V
OUT
for the same external compo-
nents and output power level. The combined effects of
APPLICATIO S I FOR ATIO
WUUU
Figure 8. Active Voltage Positioning Applied to the LTC3729
I
TH
R
C
R
T1
INTV
CC
C
C
3729 F08
LTC3729
R
T2
The resistive load reduces the DC loop gain while main-
taining the linear control range of the error amplifier. The
maximum output voltage deviation can theoretically be
reduced to half or alternatively the amount of output
capacitance can be reduced for a particular application. A
complete explanation is included in Design Solutions 10.
(See www.linear-tech.com)
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can be
expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
whereL1, L2,etc.are theindividual lossesasa percentage
of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3729 circuits: 1) LTC3729 V
IN
current
(including loading on the differential amplifier output),