Linear 1335A-B User manual

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1335A-B
HIGH POWER, HIGH EFFICIENCY POE PD INTERFACE WITH INTEGRATED SWITCHING
REGULATOR
1
LTC4269IDKD-1
DESCRIPTION
Demonstration circuit 1335A-B is a high-power sup-
ply featuring the LTC®4269IDKD-1. This board acts
as an IEEE 802.3at compliant, high power Power-
over-Ethernet (PoE), Powered Device (PD) and con-
nects at the RJ45 to a compatible high power Power
Sourcing Equipment (PSE) device, such as the
DC1366.
The LTC4269IDKD-1 provides IEEE802.3at standard
(PoE+) PD interfacing and power supply control.
When the PD is fully powered, the PD interface
switches power over from the PSE to the switcher
through an internal, low resistance, high power
MOSFET. The highly integrated LTC4269IDKD-1 con-
trols a high-power, small-sized power supply that
utilizes a highly-efficient isolated flyback topology
with synchronous rectification. The DC1335A-B sup-
plies a 5V output at up to 5A.
DC1335A-B also demonstrates the use of an auxiliary
48V wall adapter. When present, the auxiliary supply
becomes the dominant supply over PoE to provide
power.
Design files for this circuit board are available.
Call the LTC factory.
,LTC and LT are registered trademarks of Linear Technology Corporation.
Table 1. Performance Summary (TA= 25°C)
PARAMETER CONDITION VALUE
Port Voltage (V
PORT
) At Ethernet port 37V – 57V
Auxiliary Voltage (V
AUX
) From Aux- to Aux+ terminals 44V – 57V
Output Voltage (V
OUT
) Initial Set-point V
PORT
= 37V to 57V, I
OUT
= 0A to 5A 5.0V ± 1%
Maximum Output Current V
PORT
= 42V 4.5A
Typical Output Voltage Ripple V
IN
= 50V, I
OUT
= 4.6A 40mV
P–P
(typ)
Output Regulation Over Entire Input Voltage and Output Current Range ±0.4% (typ)
Peak to Peak Deviation with Load Step of 2.5A to 5A ±240mV (< ±5%) (typ)
Load Transient Response
Settling Time (within 1% of V
OUT
) < 100us (typ)
Switching Frequency 250kHz (typ)
Efficiency VPORT = 50V, IOUT = 4A, not incl. diode bridge 91% (typ)
OPERATING PRINCIPLES
A compatible high power PSE board, such as the
DC1366, is connected to the DC1335A-B at the RJ45
connector J1 (see the schematic). As required by
IEEE802.3at, a diode bridge is used across the data
pairs and signal pairs. Schottky diodes (D2-9) are
used at the input to improve efficiency over standard
diode bridges. The LTC4269IDKD-1 provides an
IEEE802.3at standard PoE 25k signature resistance
and is set for a power class 4. When the PD is pow-
ered and voltage is above the PoE ‘‘On Voltage’’, the

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1335A-B
HIGH POWER, HIGH EFFICIENCY POE PD INTERFACE WITH INTEGRATED SWITCHING
REGULATOR
2
LTC4269IDKD-1 switches the port voltage over to the
power supply controller through its internal MOSFET
which lies between the V
PORTN
and V
NEG
pins. This volt-
age charges C18/19 through a trickle charge resistor,
R9 to power the bias pin, V
CC
, of the power supply
controller. Once the bias power gets to its V
CC(ON)
threshold, the IC begins a controlled soft-start of the
output. As the output voltage rises, bias power is
taken over by the bias supply made up of T1’s bias
winding and D11.
When the soft-start period is over, the output voltage
is regulated by observing the pulses across the bias
winding during the flyback time. The Primary Gate
drive (PG) and Synchronous Gate (SG) drive is then
Pulse Width Modulated (PWM) in order to keep the
output voltage constant. The synchronous gate drive
signal is transmitted to the secondary via the small
signal transformer, T2. The output of T2 then drives
a discrete gate drive buffer, R22 and Q6/7 in order to
achieve fast gate transition times, hence a higher effi-
ciency.
The two-stage input filter, C5, L2, and C6 and output
filter, C1/3, L1, and C10 are the reasons that this PoE
flyback supply has exceptionally low differential mode
conducted emissions.
QUICK START PROCEDURE
Demonstration circuit 1335A-B is easy to set up to
evaluate the performance of the LTC4269IDKD-1 in a
PoE+ PD application. Refer to Figure 1 for proper
equipment setup and follow the procedure below:
NOTE: When measuring the input or output voltage
ripple, care must be taken to avoid a long ground lead
on the oscilloscope probe. Measure the output (or
input) voltage ripple by touching the probe tip and
probe ground directly across the +VOUT and –VOUT
(or VPORT_P and VPORT_N) terminals. See Figure 2
for proper scope probe technique.
1. Place test equipment (voltmeter, ammeter, and
electronic load) across output.
2. Input supplies:
a. Connect a PoE+ capable PSE with a CAT-5 cable
to the RJ45 connector, J1. See Figure 1.
b. Or, connect a 37V to 57V capable power supply
(‘‘Power Supply’’ in Figure 1) across VPORT_P and
VPORT_N.
c. If evaluating the auxiliary power supply (‘‘Auxil-
iary Supply’’ in Figure 1) capability, connect a 44V
to 57V capable power supply across AUX+ to AUX-.
3. Check for the proper output voltage of 5V.
4. Once the proper output voltage is confirmed, adjust
the load within the operating range and observe the
output voltage regulation, ripple voltage, efficiency
and other parameters.

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1335A-B
HIGH POWER, HIGH EFFICIENCY POE PD INTERFACE WITH INTEGRATED SWITCHING
REGULATOR
3
Figure 1. Proper Measurement Equipment Setup
Figure 2. Measuring Input or Output Ripple

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1335A-B
HIGH POWER, HIGH EFFICIENCY POE PD INTERFACE WITH INTEGRATED SWITCHING
REGULATOR
4
MEASURED DATA
Figures 3 through 10 are measured data for a typical DC1335A-B.
72
74
76
78
80
82
84
86
88
90
92
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Current (A)
Efficiency(%)
42V
50V
57V
Figure 3. Efficiency (not including Diode Bridge)
Figure 4. Regulation
4.75
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
5.25
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Output Current (A)
Efficiency(%)
42V
50V
57V

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1335A-B
HIGH POWER, HIGH EFFICIENCY POE PD INTERFACE WITH INTEGRATED SWITCHING
REGULATOR
5
Figure 5. Input and Output Ripple (48Vport, 5A)
Figure 6. Load Transient Response (48Vport, 2.5A to 5A to 2.5A)

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1335A-B
HIGH POWER, HIGH EFFICIENCY POE PD INTERFACE WITH INTEGRATED SWITCHING
REGULATOR
6
Figure 7. Temp Data (37Vport, 5A, Top)
Figure 8. Temp Data (37Vport, 5A, Bottom)

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1335A-B
HIGH POWER, HIGH EFFICIENCY POE PD INTERFACE WITH INTEGRATED SWITCHING
REGULATOR
7
Figure 9. Stresses (57Vport, 5A)
Figure 10. Stresses (37Vport, 5A)

QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1335A-B
HIGH POWER, HIGH EFFICIENCY POE PD INTERFACE WITH INTEGRATED SWITCHING
REGULATOR
8