LSI LSI53C875A User manual

®
S14047
LSI53C875A
PCI to Ultra SCSI
Controller
TECHNICAL
MANUAL
December 2000
Version 2.0

ii
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Document DB14-000143-01, Second Edition (December 2000).
This document describes the LSI Logic LSI53C875A PCI to Ultra SCSI Controller
and will remain the official reference source for all revisions/releases of this
product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Ultra SCSI is the term used by the SCSI Trade Association (STA) to describe
Fast-20 SCSI, as documented in the SCSI-3 Fast-20 Parallel Interface standard,
X3,277-199X.
Copyright © 2000 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, TolerANT, and SCRIPTS are registered trademarks
or trademarks of LSI Logic Corporation. All other brand and product names may
be trademarks of their respective companies.
HH

Preface iii
Preface
This book is the primary reference and technical manual for the
LSI53C875A PCI to Ultra SCSI Controller. It contains a complete
functional description for the product and also includes complete physical
and electrical specifications.
Audience
This manual provides reference information on the LSI53C875A PCI to
Ultra SCSI Controller. It is intended for system designers and
programmers who are using this device to design an Ultra SCSI port for
PCI-based personal computers, workstations, servers or embedded
applications.
Organization
This document has the following chapters and appendixes:
•Chapter 1, General Description includes general information about
the LSI53C875A.
•Chapter 2, Functional Description describes the main functional
areas of the chip in more detail, including interfaces to the SCSI bus
and external memory.
•Chapter 3, Signal Descriptions contains pin diagrams and signal
descriptions.
•Chapter 4, Registers describes each bit in the operating registers,
and is organized by register address.
•Chapter 5, SCSI SCRIPTS Instruction Set defines all of the SCSI
SCRIPTS instructions that are supported by the LSI53C875A.

iv Preface
•Chapter 6, Electrical Specifications contains the electrical
characteristics and AC timing diagrams.
•Appendix A, Register Summary is a register summary.
•Appendix B, External Memory Interface Diagram Examples contains
several example interface drawings for connecting the LSI53C875A
to external ROMs.
Related Publications
For background information, please contact:
ANSI
11 West 42nd Street
New York, NY 10036
[phone]
Ask for document number X3.131-199X (SCSI-2)
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
Ask for document number X3.131-1994 (SCSI-2); X3.253 (SCSI-3
Parallel Interface)
ENDL Publications
14426 Black Walnut Court
Saratoga, CA 95070
[phone]
Document names: SCSI Bench Reference, SCSI Encyclopedia,
SCSI Tutor
Prentice Hall
113 Sylvan Avenue
Englewood Cliffs, NJ 07632
[phone]
Ask for document number ISBN 0-13-796855-8, SCSI: Understanding
the Small Computer System Interface
LSI Logic World Wide Web Home Page
www.lsilogic.com

Preface v
PCI Special Interest Group
2575 N.E. Katherine
Hillsboro, OR 97214
[phone]; [phone] (International); FAX [phone]
Conventions Used in This Manual
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive.
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.
Revision Record
Revision Date Remarks
Preliminary 5/00 Preliminary draft version of the manual.
1.0 6/00 Preliminary version of the manual.
2.0 12/00 Final version of the manual.

vi Preface

Contents vii
Contents
Chapter 1 General Description
1.1 New Features in the LSI53C875A 1-3
1.2 Benefits of Ultra SCSI 1-3
1.3 TolerANT®Technology 1-4
1.4 LSI53C875A Benefits Summary 1-4
1.4.1 SCSI Performance 1-5
1.4.2 PCI Performance 1-6
1.4.3 Integration 1-6
1.4.4 Ease of Use 1-6
1.4.5 Flexibility 1-7
1.4.6 Reliability 1-8
1.4.7 Testability 1-8
Chapter 2 Functional Description
2.1 PCI Functional Description 2-2
2.1.1 PCI Addressing 2-2
2.1.2 PCI Bus Commands and Functions Supported 2-3
2.1.3 PCI Cache Mode 2-9
2.2 SCSI Functional Description 2-16
2.2.1 SCRIPTS Processor 2-17
2.2.2 Internal SCRIPTS RAM 2-18
2.2.3 64-Bit Addressing in SCRIPTS 2-19
2.2.4 Hardware Control of SCSI Activity LED 2-19
2.2.5 Designing an Ultra SCSI System 2-20
2.2.6 Prefetching SCRIPTS Instructions 2-21
2.2.7 Opcode Fetch Burst Capability 2-22
2.2.8 Load and Store Instructions 2-22
2.2.9 JTAG Boundary Scan Testing 2-23
2.2.10 SCSI Loopback Mode 2-23

viii Contents
2.2.11 Parity Options 2-24
2.2.12 DMA FIFO 2-27
2.2.13 SCSI Bus Interface 2-32
2.2.14 Select/Reselect During Selection/Reselection 2-33
2.2.15 Synchronous Operation 2-34
2.2.16 Interrupt Handling 2-37
2.2.17 Chained Block Moves 2-44
2.3 Parallel ROM Interface 2-48
2.4 Serial EEPROM Interface 2-50
2.4.1 Default Download Mode 2-50
2.4.2 No Download Mode 2-51
2.5 Power Management 2-51
2.5.1 Power State D0 2-52
2.5.2 Power State D1 2-52
2.5.3 Power State D2 2-53
2.5.4 Power State D3 2-53
Chapter 3 Signal Descriptions
3.1 LSI53C875A Functional Signal Grouping 3-2
3.2 Signal Descriptions 3-3
3.2.1 Internal Pull-ups on LSI53C875A Signals 3-3
3.3 PCI Bus Interface Signals 3-4
3.3.1 System Signals 3-4
3.3.2 Address and Data Signals 3-5
3.3.3 Interface Control Signals 3-6
3.3.4 Arbitration Signals 3-7
3.3.5 Error Reporting Signals 3-7
3.3.6 Interrupt Signal 3-8
3.4 SCSI Bus Interface Signals 3-8
3.4.1 SCSI Bus Interface Signal 3-8
3.4.2 SCSI Signals 3-9
3.4.3 SCSI Control Signals 3-9
3.5 GPIO Signals 3-10
3.6 ROM Flash and Memory Interface Signals 3-11
3.7 Test Interface Signals 3-12
3.8 Power and Ground Signals 3-13
3.9 MAD Bus Programming 3-14

Contents ix
Chapter 4 Registers
4.1 PCI Configuration Registers 4-1
4.2 SCSI Registers 4-18
4.3 64-Bit SCRIPTS Selectors 4-99
4.4 Phase Mismatch Jump Registers 4-103
Chapter 5 SCSI SCRIPTS Instruction Set
5.1 Low Level Register Interface Mode 5-1
5.2 High Level SCSI SCRIPTS Mode 5-2
5.2.1 Sample Operation 5-3
5.3 Block Move Instruction 5-6
5.3.1 First Dword 5-6
5.3.2 Second Dword 5-13
5.4 I/O Instruction 5-13
5.4.1 First Dword 5-14
5.4.2 Second Dword 5-21
5.5 Read/Write Instructions 5-22
5.5.1 First Dword 5-22
5.5.2 Second Dword 5-23
5.5.3 Read-Modify-Write Cycles 5-23
5.5.4 Move To/From SFBR Cycles 5-24
5.6 Transfer Control Instructions 5-25
5.6.1 First Dword 5-26
5.6.2 Second Dword 5-32
5.7 Memory Move Instructions 5-32
5.7.1 First Dword 5-33
5.7.2 Read/Write System Memory from SCRIPTS 5-34
5.7.3 Second Dword 5-34
5.7.4 Third Dword 5-35
5.8 Load and Store Instructions 5-35
5.8.1 First Dword 5-36
5.8.2 Second Dword 5-37
Chapter 6 Electrical Specifications
6.1 DC Characteristics 6-1
6.2 TolerANT Technology Electrical Characteristics 6-5

xContents
6.3 AC Characteristics 6-9
6.4 PCI and External Memory Interface Timing Diagrams 6-11
6.4.1 Target Timing 6-13
6.4.2 Initiator Timing 6-19
6.4.3 External Memory Timing 6-35
6.5 SCSI Timing Diagrams 6-52
6.6 Package Diagrams 6-58
Appendix A Register Summary
Appendix B External Memory Interface Diagram Examples
Index
Customer Feedback
Figures 1.1 Typical LSI53C875A System Application 1-2
1.2 Typical LSI53C875A Board Application 1-2
2.1 LSI53C875A Block Diagram 2-2
2.2 Parity Checking/Generation 2-27
2.3 DMA FIFO Sections 2-28
2.4 LSI53C875A Host Interface SCSI Data Paths 2-29
2.5 Regulated Termination for Ultra SCSI 2-33
2.6 Determining the Synchronous Transfer Rate 2-35
2.7 Block Move and Chained Block Move Instructions 2-45
3.1 LSI53C875A Functional Signal Grouping 3-2
5.1 SCRIPTS Overview 5-5
6.1 Rise and Fall Time Test Condition 6-7
6.2 SCSI Input Filtering 6-7
6.3 Hysteresis of SCSI Receivers 6-7
6.4 Input Current as a Function of Input Voltage 6-8
6.5 Output Current as a Function of Output Voltage 6-8
6.6 External Clock 6-9
6.7 Reset Input 6-10
6.8 Interrupt Output 6-11

Contents xi
6.9 PCI Configuration Register Read 6-13
6.10 PCI Configuration Register Write 6-14
6.11 32-Bit Operating Register/SCRIPTS RAM Read 6-15
6.12 64-Bit Address Operating Register/SCRIPTS RAM Read 6-16
6.13 32-Bit Operating Register/SCRIPTS RAM Write 6-17
6.14 64-Bit Address Operating Register/SCRIPTS RAM Write 6-18
6.15 Nonburst Opcode Fetch, 32-Bit Address and Data 6-20
6.16 Burst Opcode Fetch, 32-Bit Address and Data 6-22
6.17 Back-to-Back Read, 32-Bit Address and Data 6-24
6.18 Back-to-Back Write, 32-Bit Address and Data 6-26
6.19 Burst Read, 32-Bit Address and Data 6-28
6.20 Burst Read, 64-Bit Address and Data 6-30
6.21 Burst Write, 32-Bit Address and Data 6-32
6.22 Burst Write, 64-Bit Address and 32-Bit Data 6-34
6.23 External Memory Read 6-36
6.24 External Memory Write 6-40
6.25 Normal/Fast Memory (≥128 Kbytes) Single Byte
Access Read Cycle 6-42
6.26 Normal/Fast Memory (≥128 Kbytes) Single Byte
Access Write Cycle 6-43
6.27 Normal/Fast Memory (≥128 Kbytes) Multiple Byte
Access Read Cycle 6-44
6.28 Normal/Fast Memory (≥128 Kbytes) Multiple Byte
Access Write Cycle 6-46
6.29 Slow Memory (≤128 Kbytes) Read Cycle 6-48
6.30 Slow Memory (≤128 Kbytes) Write Cycle 6-49
6.31 ≤64 Kbytes ROM Read Cycle 6-50
6.32 ≤64 Kbyte ROM Write Cycle 6-51
6.33 Initiator Asynchronous Send 6-52
6.34 Initiator Asynchronous Receive 6-53
6.35 Target Asynchronous Send 6-54
6.36 Target Asynchronous Receive 6-55
6.37 Initiator and Target Synchronous Transfer 6-57
6.38 LSI53C875A 160-Pin PQFP Mechanical Drawing 6-58
6.39 169-Pin BGA Mechanical Drawing 6-61
B.1 16KbyteInterfacewith200nsMemory B-1
B.2 64KbyteInterfacewith150nsMemory B-2

xii Contents
B.3 128 Kbytes, 256 Kbytes, 512 Kbytes, or 1 Mbyte
Interface with 150 ns Memory B-3
B.4 512 Kbyte Interface with 150 ns Memory B-4
Tables 2.1 PCI Bus Commands and Encoding Types for the
LSI53C875A 2-4
2.2 PCI Cache Mode Alignment 2-12
2.3 Bits Used for Parity Control and Generation 2-25
2.4 SCSI Parity Control 2-26
2.5 SCSI Parity Errors and Interrupts 2-26
2.6 Parallel ROM Support 2-49
2.7 Mode A Serial EEPROM Data Format 2-51
2.8 Power States 2-52
3.1 LSI53C875A Internal Pull-ups 3-3
3.2 System Signals 3-4
3.3 Address and Data Signals 3-5
3.4 Interface Control Signals 3-6
3.5 Arbitration Signals 3-7
3.6 Error Reporting Signals 3-7
3.7 Interrupt Signal 3-8
3.8 SCSI Bus Interface Signal 3-8
3.9 SCSI Signals 3-9
3.10 SCSI Control Signals 3-9
3.11 GPIO Signals 3-10
3.12 ROM Flash and Memory Interface Signals 3-11
3.13 Test Interface Signals 3-12
3.14 Power and Ground Signals 3-13
3.15 Decode of MAD Pins 3-14
4.1 PCI Configuration Register Map 4-2
4.2 SCSI Register Address Map 4-19
4.3 Examples of Synchronous Transfer Periods and Rates
for SCSI-1 4-32
4.4 Example Transfer Periods and Rates for Fast SCSI-2
and Ultra SCSI 4-33
4.5 Maximum Synchronous Offset 4-34
4.6 SCSI Synchronous Data FIFO Word Count 4-44
5.1 SCRIPTS Instructions 5-3

Contents xiii
5.2 SCSI Information Transfer Phase 5-12
5.3 Read/Write Instructions 5-24
5.4 Transfer Control Instructions 5-26
5.5 SCSI Phase Comparisons 5-29
6.1 Absolute Maximum Stress Ratings 6-2
6.2 Operating Conditions 6-2
6.3 Input Capacitance 6-2
6.4 Bidirectional Signals—MAD[7:0], MAS/[1:0], MCE/, MOE/,
MWE/ 6-3
6.5 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/,
GPIO[2:4] 6-3
6.6 Bidirectional Signals—AD[31:0], C_BE[3:0]/, FRAME/,
IRDY/, TRDY/, DEVSEL/, STOP/, PERR/, PAR 6-4
6.7 Input Signals—CLK, GNT/, IDSEL, RST/, SCLK, TCK,
TDI, TEST_HSC, TEST_RST, TMS, TRST/ 6-4
6.8 Output Signal—TDO 6-4
6.9 Output Signals—IRQ/, MAC/_TESTOUT, REQ/ 6-5
6.10 Output Signal—SERR/ 6-5
6.11 TolerANT Technology Electrical Characteristics for SE
SCSI Signals 6-6
6.12 External Clock 6-9
6.13 Reset Input 6-10
6.14 Interrupt Output 6-10
6.15 PCI Configuration Register Read 6-13
6.16 PCI Configuration Register Write 6-14
6.17 32-Bit Operating Register/SCRIPTS RAM Read 6-15
6.18 64-Bit Address Operating Register/SCRIPTS RAM Read 6-16
6.19 32-Bit Operating Register/SCRIPTS RAM Write 6-17
6.20 64-Bit Address Operating Register/SCRIPTS RAM Write 6-18
6.21 Nonburst Opcode Fetch, 32-Bit Address and Data 6-19
6.22 Burst Opcode Fetch, 32-Bit Address and Data 6-21
6.23 Back-to-Back Read, 32-Bit Address and Data 6-23
6.24 Back-to-Back Write, 32-Bit Address and Data 6-25
6.25 Burst Read, 32-Bit Address and Data 6-27
6.26 Burst Read, 64-Bit Address and Data 6-29
6.27 Burst Write, 32-Bit Address and Data 6-31
6.28 Burst Write, 64-Bit Address and 32-Bit Data 6-33
6.29 External Memory Read 6-35

xiv Contents
6.30 External Memory Write 6-38
6.31 Normal/Fast Memory (≥128 Kbytes) Single Byte
Access Read Cycle 6-42
6.32 Normal/Fast Memory (≥128 Kbytes) Single Byte
Access Write Cycle 6-43
6.33 Slow Memory (≤128 Kbytes) Read Cycle 6-48
6.34 Slow Memory (≤128 Kbytes) Write Cycle 6-49
6.35 ≤=64 Kbytes ROM Read Cycle 6-50
6.36 ≤64 Kbyte ROM Write Cycle 6-51
6.37 Initiator Asynchronous Send 6-52
6.38 Initiator Asynchronous Receive 6-53
6.39 Target Asynchronous Send 6-54
6.40 Target Asynchronous Receive 6-55
6.41 SCSI-1 Transfers (5.0 Mbytes) 6-55
6.42 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 40 MHz Clock 6-56
6.43 Ultra SCSI Transfers 20.0 Mbytes (8-Bit Transfers) or
40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6-56
6.44 160 PQFP Pin List by Location 6-60
6.45 169 BGA Pin List by Location 6-62
A.1 LSI53C875A PCI Register Map A-1
A.2 LSI53C875A SCSI Register Map A-2

LSI53C875A PCI to Ultra SCSI Controller 1-1
Chapter 1
General Description
Chapter 1 is divided into the following sections:
•Section 1.1, “New Features in the LSI53C875A”
•Section 1.2, “Benefits of Ultra SCSI”
•Section 1.3, “TolerANT®Technology”
•Section 1.4, “LSI53C875A Benefits Summary”
The LSI53C875A PCI to Ultra SCSI Controller brings Ultra SCSI
performance to host adapter, workstation, and general computer designs,
making it easy to add a high-performance SCSI bus to any PCI system.
It supports Ultra SCSI transfer rates with Single-Ended (SE) signaling for
SCSI devices.
The LSI53C875A has a local memory bus for local storage of the
device’s BIOS ROM in flash memory or standard EEPROMs. The
LSI53C875A supports programming of local flash memory for updates to
BIOS. Chapter 6, “Electrical Specifications,” has the chip package and
BGA specifications. Appendix B, “External Memory Interface Diagram
Examples,” has system diagrams showing the connections of the
LSI53C875A with an external ROM or flash memory.
The LSI53C875A integrates a high-performance SCSI core, a 64-bit PCI
bus master DMA core, and the LSI Logic SCSI SCRIPTS™ processor to
meet the flexibility requirements of SCSI-3 and Ultra SCSI standards. It
implements multithreaded I/O algorithms with a minimum of processor
intervention, solving the protocol overhead problems of previous
intelligent and nonintelligent adapter designs.
Figure 1.1 illustrates a typical LSI53C875A system and Figure 1.2
illustrates a typical LSI53C875A board application.

1-2 General Description
Figure 1.1 Typical LSI53C875A System Application
Figure 1.2 Typical LSI53C875A Board Application
PCI Bus
Interface
Controller
LSI53C875A
PCItoWideUltra
SCSI Controller
PCI Graphic Accelerator
PCI Fast Ethernet
Memory
Controller
Memory
Fixed Disk, Optical Disk
Printer, Tape, and Other
Peripherals
Central
Processing
Unit
(CPU)
PCI Bus
Processor Bus
Typical PCI
Computer System
Architecture
SCSI Bus
68 Pin
SCSI
Wide
Connector
LSI53C875A
32 Bit PCI to
SCSI Controller
Memory Control
Block
Flash EEPROM
Serial EEPROM
PCI Interface
PCI Address, Data, Parity and Control Signals
SCSI Data,
Parity and
Control
Signals
Memory
Address/Data
Bus
GPIO[1:0]

New Features in the LSI53C875A 1-3
1.1 New Features in the LSI53C875A
The LSI53C875A is a drop-in replacement for the LSI53C875 PCI to
Ultra SCSI Controller, with these additional benefits:
•Supports 32-bit PCI Interface with 64-bit addressing.
•Handles SCSI phase mismatches in SCRIPTS without interrupting
the CPU.
•Supports JTAG boundary scanning.
•Supports PC99 Power Management.
– Automatically downloads Subsystem Vendor ID, Subsystem ID,
and PCI power management levels D0, D1, D2, and D3.
•Improves PCI bus efficiency through improved PCI caching design.
•Transfers Load/Store data to or from 4 Kbytes of internal SCRIPTS
RAM.
Additional features of the LSI53C875A include:
•Hardware control of SCSI activity LED.
•32-bit ISTAT registers (Interrupt Status Zero (ISTAT0),Interrupt
Status One (ISTAT1),Mailbox Zero (MBOX0),Mailbox One
(MBOX1)).
•Optional 944 byte DMA FIFO supports large block transfers at Ultra
SCSI speeds. The default FIFO size of 112 bytes is also supported.
1.2 Benefits of Ultra SCSI
Ultra SCSI is an extension of the SPI-2 draft standard that allows faster
synchronous SCSI transfer rates. When enabled, Ultra SCSI performs
20 megatransfers per second. The LSI53C875A can perform 16-bit, Ultra
SCSI synchronous transfers as fast as 40 Mbytes/s. This advantage is
most noticeable in heavily loaded systems or with applications with large
block requirements, such as video on-demand and image processing.
An advantage of Ultra SCSI is that it significantly improves SCSI
bandwidth while preserving existing hardware and software investments.
The primary software changes required enable the chip to perform

1-4 General Description
synchronous negotiations for Ultra SCSI rates and to enable the clock
quadrupler. Chapter 2, “Functional Description,” contains more
information on Ultra SCSI design.
1.3 TolerANT®Technology
The LSI53C875A features TolerANT technology, which includes active
negation on the SCSI drivers and input signal filtering on the SCSI
receivers. Active negation actively drives the SCSI Request,
Acknowledge, Data, and Parity signals HIGH rather than allowing them
to be passively pulled up by terminators. Active negation is enabled by
setting bit 7 in the SCSI Test Three (STEST3) register.
TolerANT receiver technology improves data integrity in unreliable
cabling environments where other devices would be subject to data
corruption. TolerANT receivers filter the SCSI bus signals to eliminate
unwanted transitions, without the long signal delay associated with
RC-type input filters. This improved driver and receiver technology helps
eliminate double clocking of data, the single biggest reliability issue with
SCSI operations.
The benefits of TolerANT technology include increased immunity to noise
when the signal is going HIGH, better performance due to balanced duty
cycles, and improved fast SCSI transfer rates. In addition, TolerANT SCSI
devices do not cause glitches on the SCSI bus at power-up or
power-down, so other devices on the bus are also protected from data
corruption. TolerANT technology is compatible with both the Alternative
One and Alternative Two termination schemes proposed by the American
National Standards Institute.
1.4 LSI53C875A Benefits Summary
This section of the chapter provides an overview of the LSI53C875A
features and benefits. It contains these topics:
•SCSI Performance
•PCI Performance
•Integration

LSI53C875A Benefits Summary 1-5
•Ease of Use
•Flexibility
•Reliability
•Testability
1.4.1 SCSI Performance
To improve SCSI performance, the LSI53C875A:
•Has integrated SE transceivers.
•Bursts up to 512 bytes across the PCI bus through its 944 byte FIFO.
•Performs wide, Ultra SCSI synchronous transfers as fast as
40 Mbytes/s.
•Can handle phase mismatches in SCRIPTS without interrupting the
system processor, eliminating the need for CPU intervention during
an I/O disconnect/reselect sequence.
•Achieve Ultra SCSI transfer rates with an input frequency of 20 MHz
with the on-chip SCSI clock quadrupler.
•Includes 4 Kbytes internal RAM for SCRIPTS instruction storage.
•Has 31 levels of SCSI synchronous offset.
•Supports variable block size and scatter/gather data transfers.
•Performs sustained memory-to-memory DMA transfers to
approximately 100 Mbytes/s.
•Minimizes SCSI I/O start latency.
•Performs complex bus sequences without interrupts, including
restoring data pointers.
•Reduces ISR overhead through a unique interrupt status reporting
method.
•Uses Load/Store SCRIPTS instructions which increase performance
of data transfers to and from the chip registers without using PCI
cycles.
•Has SCRIPTS support for 64-bit addressing.
•Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast
I/O context switching.

1-6 General Description
•Supports additional arithmetic capability with the Expanded Register
Move instruction.
1.4.2 PCI Performance
To improve PCI performance, the LSI53C875A:
•Complies with PCI 2.2 specification.
•Supports 32-bit 33 MHz PCI interface with 64-bit addressing.
•Supports dual address cycles which can be generated for all
SCRIPTS for > 4 Gbyte addressability.
•Bursts 2, 4, 8, 16, 32, 64, or 128 Dword transfers across the PCI bus.
•Supports 32-bit word data bursts with variable burst lengths.
•Prefetches up to 8 Dwords of SCRIPTS instructions.
•Bursts SCRIPTS opcode fetches across the PCI bus.
•Performs zero wait-state bus master data bursts faster than
110 Mbytes/s (@ 33 MHz).
•Supports PCI Cache Line Size register.
•Supports PCI Write and Invalidate, Read Line, and Read Multiple
commands.
•Complies with PCI Bus Power Management Specification Rev 1.1.
1.4.3 Integration
Features of the LSI53C875A which ease integration include:
•High-performance SCSI core.
•Integrated SE transceivers.
•Full 32-bit PCI DMA bus master.
•Integrated SCRIPTS processor.
•Memory-to-Memory Move instructions allow use as a third party PCI
bus DMA controller.
1.4.4 Ease of Use
The LSI53C875A provides: