LSI LSIFC929 User manual

®
S14073
LSIFC929DualChannel
Fibre Channel I/O
Processor
Technical
Manual
August 2001
Revision 2.0

ii Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Electromagnetic Compatibility Notices
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions:
1. This device may not cause harmful interference, and
2. This device must accept any interference received, including interference that may cause undesired operation.
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15
of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a
residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed
and used in accordance with the instructions, may cause harmful interference to radio communications. However,
there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful
interference to radio or television reception, which can be determined by turning the equipment off and on, the user
is encouraged to try to correct the interference by one or more of the following measures:
•Reorient or relocate the receiving antenna.
•Increase the separation between the equipment and the receiver.
•Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
•Consult the dealer or an experienced radio/TV technician for help.
Shielded cables for SCSI connection external to the cabinet are used in the compliance testing of this Product.
LSI Logic is not responsible for any radio or television interference caused by unauthorized modification of this
equipment or the substitution or attachment of connecting cables and equipment other than those specified by
LSI Logic. The correction of interferences caused by such unauthorized modification, substitution, or attachment will
be the responsibility of the user.
The LSI Logic LSIFC929 is tested to comply with FCC standards for home or office use.
This Class B digital apparatus meets all requirements of the Canadian Interference-Causing Equipment Regulations.
Cet appareil numérique de la classe B respecte toutes les exigences du Règlement sur le matériel brouilleur du
Canada.
This is a Class B product based on the standard of the Voluntary Control Council for Interference from Information
Technology Equipment (VCCI). If this is used near a radio or television receiver in a domestic environment, it may
cause radio interference. Install and use the equipment according to the instruction manual.
LSI Logic Corporation
North American Headquarters
Milpitas, CA
408.433.8000

iii
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
This document is preliminary. As such, it contains data derived from functional
simulations and performance estimates. LSI Logic has not verified either the
functional descriptions, or the electrical and mechanical specifications using
production parts.
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
DB14-000135-02, Third Edition (August 2001)
This document describes LSI Logic Corporation’s LSIFC929 Dual Channel Fibre
Channel I/O Processor and will remain the official reference source for all
revisions/releases of this product until rescinded by an update.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design and GigaBlaze are registered trademarks of LSI Logic
Corporation. ARM is a registered trademark of ARM Ltd.,, used under license.
All other brand and product names may be trademarks of their respective
companies.
DB
To receive product literature, visit us at http://www.lsilogic.com.
For a current list of our distributors, sales offices, and design resource
centers, view our web page located at
http://www.lsilogic.com/contacts/na_salesoffices.html

iv Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.

LSIFC929 Dual Channel Fibre Channel I/O Processor v
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Preface
This book is the primary reference and technical manual for the
LSIFC929 Fibre Channel I/O Processor. It contains a complete functional
description for the LSIFC929 and includes complete physical and
electrical specifications for the product.
Audience
This document was prepared for logic designers and applications
engineers and is intended to provide an overview of the LSI Logic
LSIFC929 and to explain how to use the LSIFC929 in the initial stages
of system design.
This document assumes that you have some familiarity with
microprocessors and related support devices. The people who benefit
from this book are:
•Engineers and managers who are evaluating the LSIFC929 for
possible use in a system
•Engineers who are designing the LSIFC929 into a system
Organization
This document has the following chapters and appendixes:
•Chapter 1, Introduction,provides a general description of the
LSIFC929.
•Chapter 2, Fibre Channel Overview,briefly describes some key
elements of Fibre Channel, including Layers, Topologies, and
Classes of Service.

vi Preface Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
•Chapter 3, LSIFC929 Overview,provides an introduction to the
basic features of the LSIFC929, including the host interface, protocol
assist engines, and support components.
•Chapter 4, Signal Descriptions,lists and describes the signals on
the LSIFC929.
•Chapter 5, Register Descriptions,briefly describes the PCI address
space, the Configuration Registers, and the Host Interface Registers.
•Chapter 6, Specifications,describes the electrical specifications of
the LSIFC929, and provides pinout information and packaging
dimensions.
•Appendix A, Register Summary, is a register summary.
•Appendix B, Reference Specifications, lists several specifications
and applicable World Wide Web URLs that may be of benefit to the
reader.
•Appendix C, Glossary of Terms and Abbreviations, is a glossary
of terms and abbreviations.
Related Publications
Fusion-MPT Message Passing Interface Specification,
Number DB14-000174-00
Conventions Used in This Manual
The word assert means to drive a signal true or active. The word
deassert means to drive a signal false or inactive. Signals that are active
LOW end in an “/.”
Hexadecimal numbers are indicated by the prefix “0x” —for example,
0x32CF. Binary numbers are indicated by the prefix “0b” —for example,
0b0011.0010.1100.1111.

Preface vii
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Revision Record
Revision Date Remarks
0.3 04/2000 First Advance Information printing.
1.0 05/2001 First Preliminary release.
Changes:
Converted the Manual to LSI format.
Table 4.2 - RTRIM description changed.
Table 4.2 - RXLOS0 and RXLOS1 descriptions changed.
Table 4.4 - Test Modes removed from MODE[7:0] description.
Section 5.3.2 - Note reworded.
Register 0x00C, page 5-14 - Cache Line Size description modified.
Register 0x040, page 5-31 - Changed this register from Read/Write to Write
Only.
Table 6.8 - Min/Max values and test conditions changed.
Figure 4.1 and Tables 4.1 and 4.2 have been moved to the end of Chapter
6, making the layout of this Manual consistent with our current guidelines.
They are now Figure 6.16 and Tables 6.16 and 6.17
Table 4.1 - new signals are added to the device, incorporating hot swap
capabilities. They are also added to Figure 6.16 and Tables 6.16 and 6.17.
2.0 07/2001 Release of Final Manual.
Changes:
Deleted Section 1.7.
Removed “Draft” references from Manual.
Table 6.1 - Changed ESD maximum spec to 1.5 kV.
Section 6.2.2 - Referred user to the Fibre Channel Physical Interfaces
specification (FC-PI, Rev. 11) for Fibre Channel Interface Timings.
Appendix B, Table 6.8 - Updated the list of Reference Specifications.

viii Preface Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.

LSIFC929 Dual Channel Fibre Channel I/O Processor ix
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Contents
Chapter 1 Introduction
1.1 Overview 1-1
1.1.1 Hardware Features 1-1
1.1.2 FC Features 1-2
1.1.3 Software Features 1-3
1.1.4 OS Support 1-3
1.1.5 Targeted Applications 1-3
1.2 General Description 1-4
1.2.1 Multifunction PCI 1-5
1.2.2 Simple Autospeed Negotiation Algorithm 1-5
1.2.3 Failover 1-5
1.3 Hardware Overview 1-6
1.3.1 PCI Interface 1-7
1.3.2 32-Bit Memory Controller 1-7
1.3.3 I/O Processor 1-8
1.3.4 System Interface 1-8
1.3.5 Integrated 2 Gbaud Transceivers 1-8
1.3.6 Link Controllers 1-8
1.3.7 Transmitters 1-9
1.3.8 Receivers 1-9
1.3.9 Context Managers 1-9
1.4 Initiator Operations 1-9
1.5 Target Operations 1-9
1.6 Diagnostics 1-9
Chapter 2 Fibre Channel Overview
2.1 Introduction 2-1
2.2 FC Layers 2-2
2.3 Frames 2-3

x Contents Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
2.4 Exchanges 2-4
2.5 FC Ports 2-7
2.6 FC Topologies 2-7
2.6.1 Point-to-Point Topology 2-8
2.6.2 Fabric Topology 2-8
2.6.3 Arbitrated Loop Topology 2-8
2.7 Classes of Service 2-9
Chapter 3 LSIFC929 Overview
3.1 Introduction 3-1
3.1.1 Data Flows 3-2
3.2 Message Interface 3-3
3.2.1 Messages 3-3
3.2.2 Message Flow 3-4
3.3 SCSI Message Class 3-5
3.4 LAN Message Class 3-6
3.5 Target Message Class 3-7
3.6 Support Components 3-8
3.6.1 SSRAM Memory 3-8
3.6.2 Flash ROM 3-9
3.6.3 Serial EEPROM 3-9
Chapter 4 Signal Descriptions
Chapter 5 Registers
5.1 PCI Addressing 5-1
5.2 PCI Bus Commands Supported 5-2
5.3 PCI Cache Mode 5-3
5.3.1 Support for PCI Cache Line Size Register 5-4
5.3.2 Selection of Cache Line Size 5-4
5.3.3 Memory Write and Invalidate Command 5-4
5.3.4 Read Commands 5-6
5.4 Unsupported PCI Commands 5-7
5.5 Programming Model 5-7
5.6 PCI/Multifunction PCI Configuration Registers 5-7
5.6.1 Multifunction PCI 5-8
5.7 Host Interface Registers 5-24
5.8 Shared Memory 5-32

Contents xi
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Chapter 6 Specifications
6.1 Electrical Requirements 6-1
6.2 AC Timing 6-6
6.2.1 PCI Interface Timing Diagrams 6-6
6.2.2 Fibre Channel Interface Timings 6-18
6.2.3 Memory Interface Timings 6-19
6.3 Packaging 6-22
6.4 Mechanical Drawing 6-26
6.5 Package Thermal Considerations 6-27
Appendix A Register Summary
Appendix B Reference Specifications
Appendix C Glossary of Terms and Abbreviations
Index
Customer Feedback
Figures 1.1 LSIFC929 Typical Implementation 1-5
1.2 LSIFC929 Block Diagram 1-7
2.1 FC Layers 2-2
2.2 Link Control Frame 2-3
2.3 Data Frame 2-4
2.4 Exchange to Character 2-5
2.5 FCP Exchange 2-6
2.6 Write Event Trellis 2-7
2.7 Point-to-Point Topology 2-8
2.8 Fabric Topology 2-8
2.9 Arbitrated Loop Topology 2-9
3.1 LSIFC929 Block Diagram 3-2
3.2 LSIFC929 Message Flow 3-5

xii Contents Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
3.3 LAN Protocol Stack 3-7
3.4 LSIFC929 Typical Implementation 3-8
4.1 LSIFC929 Functional Signal Grouping 4-2
6.1 Configuration Register Read 6-7
6.2 Configuration Register Write 6-8
6.3 Operating Register Read 6-9
6.4 Operating Register Write 6-10
6.5 Back-to-Back Read 6-11
6.6 Back-to-Back Write 6-12
6.7 Burst Read 6-13
6.8 Burst Write 6-14
6.9 Read With 64-Bit Initiator and 64-Bit Target 6-15
6.10 64-Bit Dual-Address Cycle 6-16
6.11 SSRAM Read/Write/Read Timing Waveforms 6-19
6.12 FLASH ROM Read Timing Waveforms 6-20
6.13 FLASH ROM Write Timing Waveforms 6-21
6.14 LSIFC929 Pinout (329-Pin BGA) Top View 6-22
6.15 329-Pad Plastic Ball Grid Array 6-26
Tables 4.1 PCI Interface 4-3
4.2 Fibre Channel Interface 4-8
4.3 Memory Interface 4-10
4.4 Configuration Signals 4-12
4.5 Miscellaneous Signals 4-14
4.6 JTAG Test and I/O Processor Debug 4-15
4.7 Power and Ground Pins 4-16
5.1 PCI Bus Commands and Encoding Types 5-3
5.2 LSIFC929 PCI Configuration Register Map 5-8
5.3 PCI Memory 0 Address Map 5-24
6.1 Absolute Maximum Stress Ratings 6-1
6.3 Capacitance 6-2
6.4 Input Signals (FAULT1/, FAULT0/, ROMSIZE[1:0],
ARMEN/, FSELZ[1:0], MODE[7:0], SWITCH,
HOTSWAPEN/) 6-2
6.2 Operating Conditions 6-2
6.5 Schmitt Input Signals (REFCLK, TESTRESET/, ZCLK,
TCK, TDI, TRST/, TMS_CHIP, TMS_ICE) 6-3

Contents xiii
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
6.6 4 mA Bidirectional Signals (LIPRESET/, ODIS1,
ODIS0, BYPASS1/, BYPASS0/, MD[31:0], MA[21:0],
MWE[1:0]/, FLASHCS/, BWE[3:0]/, RAMCS/, ZZ,
MP[3:0], SCL, SDA, RXLOS1, RXLOS0, ADSC/, ADV/,
TDO) 6-3
6.7 8 mA Bidirectional Signals (MODDEF1[2:0],
MODDEF0[2:0], GPIO[3:0], MOE[1:0]/, LED[4:0]/, MCLK) 6-3
6.8 PCI Input Signals (PCICLK, GNT/, IDSEL, RST/) 6-4
6.9 PCI Bidirectional Signals (AD[63:0], C_BE[7:0]/, FRAME/,
IRDY/, TRDY/, STOP/, PERR/, PAR, ACK64/, ENUM/,
64EN/) 6-4
6.10 PCI Output Signals (PAR64, REQ/, REQ64/, DEVSEL/,
SERR/, INTA/, INTB/) 6-5
6.11 PCI Interface Timings 6-17
6.12 SSRAM Read/Write/Read Timings 6-19
6.13 FLASH ROM Read Timings 6-20
6.14 FLASH ROM Write Timings 6-21
6.15 Alphanumeric Pad Listing by BGA Position 6-24
6.16 Alphanumeric Pad Listing by Signal Name 6-25
6.17 Maximum Allowable Ambient Temperature vs. Airflow 6-27
A.1 LSIFC929 Multifunction PCI Registers A-1
A.2 LSIFC929 Host Interface Registers A-2
B.1 Reference Specifications B-1

xiv Contents Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.

LSIFC929 Dual Channel Fibre Channel I/O Processor 1-1
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Chapter 1
Introduction
This chapter provides general overview information on the LSIFC929
Dual Channel Fibre Channel I/O Processor chip. The chapter contains
the following sections:
•Section 1.1, “Overview”
•Section 1.2, “General Description”
•Section 1.3, “Hardware Overview”
•Section 1.4, “Initiator Operations”
•Section 1.5, “Target Operations”
•Section 1.6, “Diagnostics”
1.1 Overview
The LSIFC929 is a high-performance, cost effective Dual Channel Fibre
Channel (FC) I/O Processor. It represents the very latest system level
integration technology in intelligent I/O processors from LSI Logic. The
Storage Area Network (SAN) environment is fully supported with both
Fibre Channel Protocol for SCSI (FCP) and LAN/IP.
1.1.1 Hardware Features
Following is a list of hardware features supported by the LSIFC929.
•Highly integrated full duplex Dual Channel Fibre Channel I/O
Processor
•Integrated 2 Gbaud Dual Channel FC serial link
•64-bit/66 MHz host PCI bus (backward compatible with
32-bit/33 MHz)

1-2 Introduction
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
•Integrated BER link testing
•32-bit ARM RISC processor
•Intelligent high-performance context management
•Synchronous SRAM external memory interface
•Full simultaneous target and initiator operations
•Implements common Message Passing Interface (MPI)
•Failover
•Load Balancing
•Firmware supports up to 2000 concurrent host commands
•PC01 compliant
•PCI 2.2 compliant
•JTAG debug interface
•329-pin BGA
1.1.2 FC Features
Following is a list of Fibre Channel features supported by the LSIFC929.
•Class 2 support and Class 3 support (with optional confirmed
delivery)
•BB credit of 3, alternate login of 1 (each channel)
•FC-PH compliance
•FC-AL 7.0 compliance
•FC-FCP, FC-PLDA compliance
•FC-FLA compliance
•FCA-IP, IETF-IPFC compliance
•NL_Port (NL_Port Attach)
•FL_Port (Public Loop Attach)
•F_Port (Fabric Attach)
•N-Port (Point-to-Point)
•Autonegotiate between 1 Gbit/s and 2Gbit/s link speeds under
firmware control for easy updating

Overview 1-3
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
1.1.3 Software Features
Following is a list of software features supported by the LSIFC929.
•Fusion-MPT drivers
•Supports optimum server I/O profile with low CPU utilization
•Supports optimum workstation I/O profile with maximum I/O
performance
•Remote diagnostic capability
•OS drivers support fail over and load balancing
•SAN Storage Management
1.1.4 OS Support
Following is a list of operating systems supported by the LSIFC929.
•Windows 2000
•Windows NT 4.0 SP4 and NT 5.0
•Windows XP
•NetWare 4.11 and 5.0
•UnixWare 2.12 and Gemini
•Solaris 2.6, 2.7 – X86
•Linux
1.1.5 Targeted Applications
Following is a list of key applications targeted by the LSIFC929.
•SANs
•Server clustering environments
•Embedded RAID
•Low cost PCI/FC host adapters
•Host main boards
•Routers and bridges

1-4 Introduction
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
1.2 General Description
The LSI Logic LSIFC929 Dual Channel Fibre Channel I/O Processor is
a high-performance, Intelligent I/O Processor (IOP) designed to
simultaneously support mass storage and IP protocols on a full duplex
2 GBaud FC Link. The sophisticated design and local memory
architecture work together to reduce the host CPU and PCI bandwidth
required to support FC I/O operations.
From the host CPU perspective, the LSIFC929 manages the FC Link at
the exchange level for mass storage (FCP) protocols. The LSIFC929
supports multiple I/O requests per host interrupt in most applications.
From the FC Link perspective, the LSIFC929 is a highly efficient NL_Port
supporting point-to-point, and public and private loop topologies, as well
as the FC switch/attach topology defined under the ANSI X3T11 FC-PH
standard. The LSIFC929 contains sufficient hardware support to perform
Class 3 service. The LSIFC929 is uniquely designed to support FC
environments where independent, full duplex transmission is required for
maximum FC Link efficiency. Special attention has been given to the
design to accelerate context switching and Link utilization.
The LSIFC929 includes a 64-bit, 66 MHz PCI interface to the host
environment. The host interface is designed to minimize the amount of
time spent on the PCI bus for nondata moving activities such as
initialization, command and error recovery. In addition, the host interface
has inherent flexibility to support the OEM’s implementation trade-offs
between CPU, PCI, and I/O bandwidth.
The high level of integration in the LSIFC929 Controller enables low cost
FC implementations. Figure 1.1 shows a typical board configuration
incorporating the LSIFC929 Controller.

General Description 1-5
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
Figure 1.1 LSIFC929 Typical Implementation
1.2.1 Multifunction PCI
Coupled with the dual channel operation, the LSIFC929 adds
multifunction capability on the PCI bus. This capability allows the host to
see two distinct “channels” or host adapters. Each channel provides full,
concurrent support for FCP Initiator, Target, and LAN protocols.
1.2.2 Simple Autospeed Negotiation Algorithm
Backward compatibility with 1 Gbit/s FC devices is maintained through
the use of the “Simple Autospeed Negotiation Algorithm.” After a
power-on, loss of signal, or loss of word synchronization for longer than
the R_T_TOV time-out, the LSIFC929 will perform this operation to
determine whether a point-to-point device or all of the devices on a loop
are either 1 Gbit/s or 2 Gbits/s devices.
1.2.3 Failover
The LSIFC929 supports two PCI functions and FC ports, which improves
performance and provides a redundant path in high-availability systems
that require failover capabilities. In case of a Link Failure, the LSIFC929
architecture allows the OS driver to support automatic failover, without
the need for IOC intervention.
LSIFC929
Integrated
Transceiver Memory Controller
2
2
Serial
EEPROM
(2 Kbyte)
Flash
(1 Mbyte)
SSRAM
(1 Mbyte typ.)
Clock
(106 MHz)
32
PCI Bus
32/64
Integrated
Transceiver
2
2
FC
Channel 0
FC
Channel 1

1-6 Introduction
Copyright © 2000, 2001 by LSI Logic Corporation. All rights reserved.
1.3 Hardware Overview
In today’s fast growing server, RAID, and workstation marketplaces,
higher levels of performance, scalability and reliability are required to stay
competitive in the SAN market.
The LSIFC929 provides the performance and flexibility to meet
tomorrow’s FC connectivity requirements.
The LSIFC929 and the LSI Logic software drivers provide superior
performance and lower host CPU overhead than other competitive
solutions. Because of its high level of integration and streamlined
architecture, the LSIFC929 provides the highest level of performance in
a more cost effective FC solution.
Figure 1.2 shows the functional block diagram for the LSIFC929. The
architecture maximizes performance and flexibility by deploying fixed
gates in critical performance areas and utilizing multiple ARM RISC
processors (two for context management and an additional one for the
I/O Processor). Each of the major blocks is briefly described below.