LSI Symbios SYM53C040 User manual

®
Symbios®SYM53C040
Enclosure Services
Processor
Order Number S14042
Technical Manual
February 2000
Version 2.5

ii
This document contains proprietary information of LSI Logic Corporation. The
information contained herein is not to be used by or disclosed to third parties
without the express written permission of an officer of LSI Logic Corporation.
LSI Logic products are not intended for use in life-support appliances, devices,
or systems. Use of any LSI Logic product in such applications without written
consent of the appropriate LSI Logic officer is prohibited.
Document DB14-000125-00, Second Edition (February 2000)
This document describes revision C.1 of LSI Logic Corporation’s Symbios®
SYM53C040 Enclosure Services Processor and will remain the official reference
source for all revisions/releases of this product until rescinded by an update.
To receive product literature, visit us at http://www.lsilogic.com.
LSI Logic Corporation reserves the right to make changes to any products herein
at any time without notice. LSI Logic does not assume any responsibility or
liability arising out of the application or use of any product described herein,
except as expressly agreed to in writing by LSI Logic; nor does the purchase or
use of a product from LSI Logic convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of
LSI Logic or third parties.
Copyright © 1998–2000 by LSI Logic Corporation. All rights reserved.
TRADEMARK ACKNOWLEDGMENT
The LSI Logic logo design, LVD Link, Symbios, and TolerANT are trademarks or
registered trademarks of LSI Logic Corporation. MCS is a registered trademark
of Intel Corporation. All other brand and product names may be trademarks of
their respective companies.
DB

Contents iii
Contents
Chapter 1 Introduction
1.1 SYM53C040 Overview 1-1
1.2 SCSI Mode 1-2
1.3 SFF-8067 Mode 1-3
1.4 Features Summary 1-4
Chapter 2 Functional Description
2.1 Functional Blocks 2-3
2.1.1 SYM53C80-Based SCSI Control Logic 2-3
2.1.2 80C32 Microcontroller Core 2-3
2.1.3 Two-Wire Serial Interface 2-3
2.1.4 SFF-8067 Interface 2-4
2.1.5 16 Kbytes SRAM 2-4
2.1.6 DMA Function 2-4
2.2 Memory Map 2-4
2.3 SCSI Core Operation 2-5
2.3.1 Recommended Use of SCSI High ID Pins 2-5
2.3.2 LVD Link™ Technology 2-8
2.3.3 Programmed I/O Transfers 2-8
2.3.4 SCSI - DMA Transfers 2-11
2.4 DMA Function 2-13
2.5 Microcontroller Operation 2-14
2.5.1 ONCE Mode 2-14
2.6 Two-Wire Serial Interface Operation 2-15
2.6.1 Two-Wire Serial Interface Transfer Rate 2-16
2.6.2 Power-On Serial ROM Download 2-16
2.6.3 Address and Length Download Configuration 2-17
2.6.4 Firmware Download and Checksum 2-18

iv Contents
2.6.5 Manually Accessing External Two-Wire Serial
Devices 2-18
2.7 Power-On Configuration Options 2-21
2.7.1 Automatic Branch Generation 2-21
2.7.2 External Serial ROM Configuration 2-22
2.7.3 Serial ROM Chip Address 2-22
2.7.4 Download Port Select 2-23
2.8 Resets 2-23
2.9 SFF-8067 Mode 2-24
2.10 Interrupts 2-27
2.10.1 Microcontroller Interrupts 2-27
2.10.2 DMA and SCSI Interrupts 2-29
2.10.3 SFF-8067 Interrupts 2-31
2.10.4 Two-Wire Serial Interrupts 2-31
2.10.5 Masking and Enabling Interrupts 2-32
2.10.6 Polling and Hardware Interrupts 2-32
2.10.7 Interrupt Service Routine 2-32
2.11 JTAG Boundary Scan Testing 2-34
Chapter 3 Signal Descriptions
3.1 Safety Mode Signals 3-9
3.1.1 Miscellaneous Signals 3-9
3.1.2 SCSI Signals 3-13
3.1.3 JTAG Signals 3-16
3.1.4 Power and Ground Signals 3-17
3.2 SFF-8067 Mode 3-18
Chapter 4 SCSI and DMA Registers
Chapter 5 SFF-8067 Registers
Chapter 6 Two-Wire Serial Registers
Chapter 7 Miscellaneous Registers

Contents v
Chapter 8 System Registers
Chapter 9 Electrical Characteristics
9.1 Operating Requirements 9-2
9.2 3.3 Volt DC Specifications 9-3
9.3 AC Characteristics 9-7
9.3.1 Clock Timing 9-7
9.3.2 Reset Signal 9-8
9.4 Microcontroller Interface Timings 9-9
9.4.1 External Memory Interface 9-9
9.4.2 External Data Read Cycle 9-10
9.4.3 External Data Write Cycle 9-11
9.5 Multipurpose Register Access 9-12
9.6 Two-Wire Serial Timings 9-13
9.7 SFF-8067 Interface Timings 9-14
9.8 SCSI Timings 9-16
9.8.1 Initiator Asynchronous Send 9-16
9.8.2 Initiator Asynchronous Receive 9-17
9.8.3 Target Asynchronous Send 9-18
9.8.4 Target Asynchronous Receive 9-19
9.9 Mechanical Drawings 9-20
Appendix A Register Summary
Index
Customer Feedback
Figures 1.1 SCSI/SAF-TE Enclosure Implementation 1-2
1.2 SFF-8067/SES Enclosure Implementation 1-3
2.1 SYM53C040 Block Diagram 2-2
2.2 SYM53C040 Memory Map 2-5
2.3 Initiating Arbitration and Selection/Reselection 2-7
2.4 LVD Resistor Value 2-8

vi Contents
2.5 Programmed I/O Target Transfers 2-10
2.6 DMA Target Mode Transfers 2-12
2.7 DMA External Memory Access 2-14
2.8 Serial Read Operation 2-15
2.9 Serial Write Operation 2-15
2.10 Serial ROM Download 2-17
2.11 Two-Wire Serial Slave Data Transmit and Receive 2-19
2.12 Two-Wire Serial Master Data Transmit and Receive 2-20
2.13 SYM53C040 SFF-8067 Interface Control State Diagram 2-26
3.1 SYM53C040, 160-Pin QFP Option 3-2
3.2 SYM53C040 169-Ball BGA Top View 3-5
3.3 SYM53C040 Functional Pin Description 3-8
4.1 Register Set Overview 4-1
5.1 Register Set Overview 5-1
6.1 Register Set Overview 6-1
7.1 Register Set Overview 7-1
8.1 Register Set Overview 8-1
9.1 LVD Driver 9-3
9.2 LVD Receiver 9-4
9.3 SYM53C040 Clock Waveforms 9-7
9.4 Reset Waveforms 9-8
9.5 External Memory Interface Waveforms 9-9
9.6 External Data Read Waveforms 9-10
9.7 External Data Write Waveforms 9-11
9.8 Two-Wire Serial Bus Timings 9-13
9.9 SFF-8067 Discovery Phase Waveforms 9-14
9.10 SFF-8067 Write Phase Waveforms 9-14
9.11 SFF-8067 Read Waveforms 9-15
9.12 Initiator Asynchronous Send Waveforms 9-16
9.13 Initiator Asynchronous Receive Waveforms 9-17
9.14 Target Asynchronous Send Waveforms 9-18
9.15 Target Asynchronous Receive Waveforms 9-19
9.16 160 LD-Pin PQFP (PZ) Mechanical Drawing (Sheet 1 of 2) 9-21
9.17 169-Pin PBGA (GV) Mechanical Drawing 9-23

Contents vii
Tables 2.1 Initial ROM Download Contents 2-17
2.2 Power-On Configuration Pins and Options 2-21
2.3 External Pull-up Values for Automatic Branch Generation 2-22
2.4 Serial ROM Chip Addresses 2-23
2.5 Register Bits for Interrupt Handling 2-28
2.6 Interrupt Handling 2-33
3.1 SYM53C040 160-Pin QFP Pin List (Alphabetically by
Signal Name) 3-3
3.2 SYM53C040 160-Pin QFP Pin List (Numerically by
Pin Number) 3-4
3.5 Miscellaneous Signals 3-9
3.6 SCSI Signals 3-13
3.7 JTAG Signals 3-16
3.8 Power and Grounds Signals 3-17
3.9 Pin Assignments for SFF-8067 Mode 3-18
4.1 SCSI and DMA Registers 4-2
4.2 SCSI Phase Bit Values 4-9
5.1 SFF-8067 Interface Registers 5-2
6.1 Two-Wire Serial Registers 6-2
7.1 Miscellaneous Registers 7-2
7.3 Possible Watchdog Timer Values (40 MHz Internal Clock) 7-4
8.1 System Registers 8-2
8.2 Automatic Branch Destination Address 8-5
8.3 Fast LED Blink Rates (40 MHz Internal Clock) 8-7
8.4 Slow LED Blink Rates (20 MHz Internal Clock) 8-7
8.5 LED Behavior 8-21
8.6 LED Bank 1 Behavior 8-25
8.7 LED Bank 2 Behavior 8-29
9.1 Absolute Maximum Stress Ratings 9-2
9.2 Operating Conditions 9-2
9.3 LVD Driver SCSI Signals—SD[7:0]+ SD[7:0]−,SDP0+,
SDP0−,SREQ+,SREQ−,SACK/+,SACK/−, SHID[2:0]+,
SHID[2:0]−, SMSG/+, SMSG/−, SIO/+, SIO/−,SCD/+,
SCD/−,SATN/+,SATN/−, SBSY/+, SBSY/−, SSEL/+,
SSEL/−,SRST/+,SRST/−9-3

viii Contents
9.4 LVD Receiver SCSI Signals—SD[7:0]+, SD[7:0]−,SDP0+,
SDP0−, SREQ/+, SREQ/−, SACK/+, SACK/−,SMSG/+,
SMSG/−, SIO/+, SIO/−, SCD/+, SCD/−,SATN/+,SATN/−,
SBSY/+, SBSY/−, SSEL/+, SSEL/−,SRST/+,SRST/−,
SHID[2:0]+, SHID[2:0]−9-4
9.5 SE SCSI and SFF-8067 Signals—SD[7:0]+, SD[7:0]−,
SHID[2:0]+, SHID[2:0]−,SDP0+,SDP0−,SREQ+,
SREQ−,SACK+,SACK−9-4
9.6 SCSI Signals—DIFFSENS 9-5
9.7 Bidirectional 80C32 Signals—AD[7:0], A[15:8], ALE,
PSEN/, RD/, WR/ 9-5
9.8 Input Signals—CLK, TCK, TMS, TDI, TRST/, TESTIN 9-5
9.9 Bidirectional Signals—RESET/, TESTOUT, CL0, SDA0,
SCL1, SDA1 9-6
9.10 Bidirectional Signals—MPIO0[7:0], MPIO1[7:0],
MPIO2[7:0], MPIO3[3:0] 9-6
9.11 Bidirectional Signals—MPLED0[7:0], MPLED1[7:0],
MPLED2[7:0] 9-6
9.12 SYM53C040 Clock Timings 9-7
9.13 Reset Timings 9-8
9.14 External Memory Interface Timings 9-9
9.15 External Data Read Timings 9-10
9.16 External Data Write Timings 9-11
9.17 Multipurpose I/O and LED Timings 9-12
9.18 Two-Wire Serial Interface Timings, Normal Mode
(100 KHz Clock) 9-13
9.19 Two-Wire Interface Timings, Fast Mode (400 KHz Clock) 9-13
9.20 SFF-8067 Interface Timings 9-15
9.21 Initiator Asynchronous Send Timings 9-16
9.22 Initiator Asynchronous Receive Timings 9-17
9.23 Target Asynchronous Send Timings 9-18
9.24 Target Asynchronous Receive Timings 9-19
A.1 Register Summary by Description A-1
A.2 Register Summary by Address A-5

Preface ix
Preface
This technical manual provides reference information on the Symbios®
SYM53C040 Enclosure Services Processor. It contains a complete
functional description for the product and includes complete physical and
electrical specifications for it.
Audience
This manual assumes some prior knowledge of current and proposed
SCSI, I2C, and SFF-8067 standards, including the SAF-TE and SES
standards for parallel SCSI devices, as well as a detailed understanding
of serial data communication. It is intended for system designers who are
using this device to manage SCSI or Fibre Channel peripheral device
enclosures.
Organization
This document has the following chapters and appendix:
•Chapter 1, Introduction, contains general information about the
SYM53C040, including an overview of its features and functions.
•Chapter 2, Functional Description, describes the main functions of
the chip in more detail, including the major interfaces.
•Chapter 3, Signal Descriptions, contains the pin diagrams and
descriptions of each signal.
•Chapter 4, SCSI and DMA Registers
•Chapter 5, SFF-8067 Registers
•Chapter 6, Two-Wire Serial Registers
•Chapter 7, Miscellaneous Registers
•Chapter 8, System Registers

xPreface
•Chapter 9, Electrical Characteristics, contains the operating
conditions and AC timings for the chip and mechanical drawings.
•Appendix A, Register Summary
Related Publications
For background information, please contact:
ANSI
11 West 42nd Street
New York, NY 10036
[phone]
Ask for document number X3.131-199X (SCSI-2)
Global Engineering Documents
15 Inverness Way East
Englewood, CO 80112
[phone] or [phone] (outside U.S.) FAX [phone]
Ask for document number X3.131-1994 (SCSI-2); X3.253 (SCSI-3
Parallel Interface); or NCITS 305-199x (SCSI-3 Enclosure Services
(SES) Specification working draft)
SCSI Accessed Fault-Tolerant Enclosures (SAF-TE) Specification
This document can be downloaded from www.safte.org
Symbios Electronic Bulletin Board
[phone]
SCSI Electronic Bulletin Board
[phone]
Symbios World Wide Web Home Page
www.symbios.com
Symbios Internet Anonymous FTP Site
ftp.symbios.com (204.131.200.1)
Directory: /pub/symchips/scsi
SFF-8067 Specification
ENDL Fax Access
[phone] (call from a FAX machine)