Microsemi IGLOO2 FPGA DSP FIR Filter User manual

IGLOO2 FPGA Evaluation Kit
User Guide

IGLOO2 FPGA Evaluation Kit User Guide
IGLOO2 FPGA Evaluation Kit User Guide 3
Table of Contents
1 – Introduction .............................................................................................. 5
Kit Contents................................................................................................................................5
IGLOO2 FPGA Evaluation Kit Web Resources.........................................................................5
Board Description.......................................................................................................................5
2 – Installation and Settings ......................................................................... 9
Software Installation...................................................................................................................9
Hardware Installation .................................................................................................................9
IGLOO2 Power Sources ..........................................................................................................11
Testing the Hardware...............................................................................................................11
3 – Key Components Description and Operation ..................................... 13
Powering Up the Board............................................................................................................13
Current Measurement..............................................................................................................13
Memory Interface.....................................................................................................................15
SERDES0 Interface .................................................................................................................16
USB Interface...........................................................................................................................18
Marvell PHY (88E1340S).........................................................................................................18
Programming............................................................................................................................20
FTDI Interface..........................................................................................................................20
I2C Port Header.......................................................................................................................21
System Reset...........................................................................................................................22
Clock Oscillator........................................................................................................................22
Debugging................................................................................................................................23
GPIO Header Pin Out ..............................................................................................................25
4 – Pin List .................................................................................................... 27
5 – Board Components Placement ............................................................. 41
6 – Demo Design .......................................................................................... 45
M2GL-EVAL-KIT Board Demo Design.....................................................................................45
7 – Manufacturing Test ................................................................................ 47
M2GL-EVAL-KIT Board Testing Procedures...........................................................................47
Switches and LED Tests..........................................................................................................58
Debugging the Board...............................................................................................................58
List of Changes ............................................................................................ 60

Table of Contents
4 IGLOO2 FPGA Evaluation Kit User Guide
Product Support .......................................................................................... 61
Customer Service.....................................................................................................................61
Customer Technical Support Center........................................................................................61
Technical Support....................................................................................................................61
Website ....................................................................................................................................61
Contacting the Customer Technical Support Center ...............................................................61
ITAR Technical Support...........................................................................................................62

IGLOO2 FPGA Evaluation Kit User Guide 5
1 – Introduction
The IGLOO®2 field programmable gate array (FPGA) Evaluation Kit (M2GL-EVAL-KIT) is RoHS compliant and
enables the designer to develop applications that involve one or more of the following:
•Motor control
•System management
•Industrial automation
•High speed serial I/O applications like PCIe, SGMII, and user customizable serial interfaces
Kit Contents
Table 1 lists the contents of the IGLOO2 Evaluation Kit.
Table 1. Kit Contents
Quantity Description
1 IGLOO2 Evaluation Board with M2GL010T-1FGG484
1 FlashPro4 JTAG programmer for programming and debugging of the IGLOO2 device
1 USB 2.0 A male to mini-B Y-cable for UART/power interface (up to 1A) to PC
1 +12 V/2 A Wall-Mounted power supply
- FTDI drivers to perform the MTD test
IGLOO2 FPGA Evaluation Kit Web Resources
IGLOO2 Evaluation Kit web resources are available at:
http://www.microsemi.com/products/fpga-soc/design-resources/dev-kits/igloo2/igloo2-evaluation-kit#overview
Board Description
The IGLOO2 Evaluation Kit offers a full-featured Evaluation Board for IGLOO2 FPGAs. This kit inherently integrates
the following on a single chip:
•Reliable flash-based FPGA fabric
•Advanced security processing accelerators
•Digital signal processing (DSP) blocks
•Static random-access memory (SRAM)
•Embedded nonvolatile memory (eNVM)
•Industry-required high-performance communication interfaces
The board has numerous interfaces including an RJ45 for 10/100/1000 Ethernet, one Full-Duplex SERDES Lane
through sub miniature version A (SMA) connectors, a 64-bit GPIO Header, and various connectors for SPI support.
The IGLOO2 memory management system is supported by 512 Mb of on board mobile LPDDR SDRAM memory and
64 Mb SPI flash. The serializer and deserializer (SERDES) block can be accessed through the peripheral component
interconnect express (PCIe) edge connector or high speed SMA connectors.
•The board supports the M2GL010T device in an FG484 package
•The board is eight layers PCB and manufactured with FR4 dielectric material.

1 – Introduction
6 IGLOO2 FPGA Evaluation Kit User Guide
Block Diagram
Figure 1 shows the IGLOO2 evaluation kit block diagram:
IGLOO2 FPGA – M2GL010T-1FGG484
GPIO Header
PHY
88E1340S RJ45
PCIE edge
connector
FP4 HeaderRVI Header
ETM HeaderUSB3320
FT4232
Lane 3
Lane 0
SPI_0
Bank2
Bank2
USB micro AB
connector
USB mini B
connector
Bank1
SGMII
MSIO
Bank7
SERDES0
SPI flash
W25Q64FV
SSIG
LPDDR
MT46H32M16LF
8 Meg x 16 x 4
banks
MDDR
Bank0
JTAG
Bank4 SC_SPI
ETM
Bank1
MDIO
Bank7
Debug
Switches-4 Bank2
MSIO
Bank4
MSIO
Bank1
U15
J4 J5
J9
J1
P1
REFCLK0
Lane 1
Lane 2 SMA
Connectors
REFCLK1
JTAG PHY
23-pin header
Debug LEDs-8 Bank7
On Board
Oscillator-
125MHz
SMA
Connectors
Mux
Figure 1. IGLOO2 FPGA Evaluation Kit Block Diagram
Board Overview
Figure 2 shows an overview of the IGLOO2 Evaluation Kit Board features.
Figure 2. IGLOO2 FPGA Evaluation Kit Board Overview

1 – Introduction
IGLOO2 FPGA Evaluation Kit User Guide 7
I/O Voltage Rails
Table 2 lists the bank I/Os with voltage rails.
Table 2. I/O Voltage Rails
IGLOO2 Bank I/O Rail Voltage
Bank0 VDDI0 1.8 V
Bank1 VDDI1 3.3 V
Bank2 VDDI2 3.3 V
Bank3 VDDI3 3.3 V
Bank4 VDDI4 3.3 V
Bank5 VDDI5 2.5 V
Bank6 VDDI6 2.5 V
Bank7 VDDI7 3.3 V
Table 3 describes the IGLOO2 FPGA Evaluation Kit Board components.
Table 3. IGLOO2 FPGA Evaluation Kit Board Components
Name
Description
M2GL010T-1FGG484 Microsemi IGLOO2 FPGA
Mobile Low-Power DDR
SDRAM 512 Mb (MT46H32M16LF – 8 Meg x 16 x 4 banks) for storing the data bits.
SPI flash 64 Mb SPI flash Winbond electronics W25Q64FVSSIG connected to SPI port 0 of the IGLOO2
FPGA high performance memory system (HPMS).
Ethernet RJ45 connector (Ethernet jack with magnetic) interfacing with Marvell 10/100/1000 BASE-T PHY
chip 88E1340S in serial gigabit media independent interface (SGMII) mode, interfacing with the
Ethernet port of the IGLOO2 FPGA (on-chip MAC and external PHY).
RVI header RVI header for application programming and debugging from Keil ULINK or IAR J-Link.
FP4 header FlashPro4 programming header for IGLOO2 programming and debugging with Microsemi tools.
Future Technology
Devices International
(FTDI) programmer
FTDI programmer interface (J18) to program the external SPI flash.
E
mbedded trace macro
(ETM) cell header ETM header for debugging.
GPIO header General purpose input/output (GPIO) header for multi standard I/O (MSIO) signals to be routed.
PCIe edge connector PCI Express edge connector with one lane
Dual in-line package (DIP)
switch Debug switch for user application.
Light-emitting diodes
(LEDs) Eight active low LEDs that are connected to some of the user I/Os for debug.
Three active high LEDs that are used for power supply indication.
Push–button reset Push-button system reset for IGLOO2 system.
Push–button switches Four push-button switches for test and navigation.
USB interface
USB micro AB connector, interfacing with the high speed USB2.0 ULPI transceiver chip

1 – Introduction
8 IGLOO2 FPGA Evaluation Kit User Guide
Name Description
USB3320, interfacing with FPGA pins of the IGLOO2 HPMS.
OSC-125 125 MHz clock oscillator (differential output)
OSC-50 50 MHz clock oscillator
OSC-32 32.768 KHz low-power oscillator

IGLOO2 FPGA Evaluation Kit User Guide 9
2 – Installation and Settings
Software Installation
Download and install the latest release of Microsemi Libero®System-on-Chip (SoC) software v11.1 or later, from the
Microsemi website and register for a free Gold license. For instructions on how to install Libero and SoftConsole,
refer to the Libero Installation and Licensing Guide available on the Microsemi website.
Refer to the Installing IP Cores and Drivers User Guide to download and install Microsemi DirectCores, SGCores,
and driver firmware cores. These must be localized on the PC where Microsemi Libero is installed while designing
with Microsemi FPGAs.
Hardware Installation
The FlashPro4 programmer can be used to program the M2GL-EVAL-KIT board.
Jumpers, Switches, LEDs, and DIP Switch Settings
The recommended default jumpers, switches, LEDs, and DIP switch settings are defined in Table 4 through Table 6.
•Table 4 Jumper Settings
•Table 5 LEDs
•Table 6 Test Points
Connect the jumpers using the default settings to enable the pre-programmed demonstration design to function
correctly. Table 4 shows the jumpers along with default settings.
Note: Location of all the jumpers and test points are searchable in Figure 17 (page 42) of 5 – Board Components
Placement section.
Table 4. Jumper Settings
Jumper Function Default Settings
J23
Jumper to select switch-side Mux inputs of A or B to the line side. –
Pin 1-2 (Input A to the line side) that is on board 125 MHz differential
clock oscillator output will be routed to line side. Closed
Pin 2-3 (Input B to the line side) that is external clock required to source
through SMA connectors to the line side. Open
J22
Jumper to select the output enables control for the line side outputs. –
Pin 1-2 (Line side output enabled) Closed
Pin 2-3 (Line side output disabled) Open
J24 Jumper to provide the VBUS supply to USB when using in Host mode. Open
J8
JTAG selection jumper to select between RVI header or FP4 header for
application debug. –
Pin 1-2 FP4 for SoftConsole/FlashPro Closed
Pin 2-3 RVI for Keil ULINK™/IAR J-Link®Open
Pin 2-4 for Toggling JTAG_SEL signal remotely using GPIO capability of
FT4232 chip. Open
J3 Jumpers to select either SW2
input or signal ENABLE_FT4232 from
FT4232H chip. –

2 – Installation and Settings
10 IGLOO2 FPGA Evaluation Kit User Guide
Jumper Function Default Settings
Pin 1-2 for Manual power switching using SW7 switch. Closed
Pin 2-3 for Remote power switch using GPIO capability of FT4232 chip. Open
Table 5 lists the power supply and Ethernet LEDs.
Table 5. LEDs
LED Comment
DS1 - Green Indicates the 5 V rail.
DS2 - Green Indicates the 3.3 V rail.
DS3 - Green Indicates the 12 V power source.
DS5 - Green Connected to parallel LED output port 0 (P0_LED[0]) of Marvell PHY.
DS4 - Green Connected to parallel LED output port 0 (P0_LED[2]) of Marvell PHY.
DS6 - Green Connected to parallel LED output port 0 (P0_LED[3]) of Marvell PHY.
Table 6 lists the USB, ground, and other test points.
Table 6. Test Points
Test Point Description
TP8 USB switch in/out for DP signal.
TP9 USB switch in/out for DM signal.
TP1, TP2, TP4, TP5, TP6, TP7, TP10,
TP11 GND
TP3 Test point for DDR_VTT
TP12 Test point to measure the voltage at TP12 with reference to GND.
TP14 1.2 V current sensing test point
TP15 1.8 V current sensing test point
TP16, TP17 Test points across current sense resistor 0.05 Ohms for 1.2 V
TP18, TP19 Test points across current sense resistor 0.05 Ohms for 1.8 V

2 – Installation and Settings
IGLOO2 FPGA Evaluation Kit User Guide 11
IGLOO2 Power Sources
All the power supply devices used in the IGLOO2 FPGA Evaluation Kit are Microsemi devices. For more information
on power supply devices refer to http://www.microsemi.com/product-directory/ics/853-power-management
Voltage rails (12 V, 5 V, 3.3 V, 2.5 V, 1.8 V, 1.5 V, and 1.0 V) provided on the board is shown in Figure 3.
LDO
NX9548
DC/DC
LX7165
LX7165
LX7175
LX7186
12P0V
5P0V_REG EN
I/P
5P0V CORE
1P2V
VDDI 1, 2, 3, 4, 7
3P3V
VDDI 5, 6
2P5V
1P0V_PHY
LX7167
LX13043
TPS51200
LX8240
LPDDR, VREF0, VDDI 0,
PHY_1P8V, 1P8V
0.9V for LPDDR
DDR_VTT
VPP, PLL Supply
3P3V_LDO
VDDAPLL,
2P5V_LDO
SERDES_0_Lxy_VDDAPLL
SERDES_0_Lxy_REFRET
SERDES_0_PLL_VDDA
SERDES_0_PLL_VSSA
IGLOO2
Figure 3. Voltage Rails in the IGLOO2 FPGA Evaluation Kit
Testing the Hardware
If the board is shipped directly from Microsemi, it contains a test program that determines whether or not the board
works properly. If you suspect that the board is damaged, you can rerun the Manufacturing Test to verify the key
interfaces of the board functionality.
Refer to http://www.microsemi.com//download/rsc/?f=%20SF2-DEV-KIT-PP_Mfg_PF (to be released) for
manufacturing test procedures.

IGLOO2 FPGA Evaluation Kit User Guide 13
3 – Key Components Description and
Operation
This chapter describes the key component interfaces. For device datasheets, refer to:
http://www.microsemi.com/document-portal/doc_download/132042-igloo2-fpga-datasheet.
Powering Up the Board
The board can be powered through either of two 12 V sources that are, external +12 V/2 A DC jack or PCIe
connector as shown in Figure 4. Protection mechanism enables the external DC jack supply, if both the sources are
available, simultaneously.
When both the power sources are ON, board takes the power from external DC jack as Diode D3 becomes reverse
biased and path will be open for 12P0_PCIE. When the external DC voltage is not present, the board can be powered
up using the PCIe connector.
12P0V_IN 12P0V
PCIe
CON1
+12 V
DC
Jack
ENABLE_FT4232
2
5
1
3
4
6
SW7
J3
J6
Figure 4. Powering Up the Board
Current Measurement
1.2 V Current Sensing for Normal Operation
For applications which require current measurement high precision Operational Amplifier circuitry (U31 with gain 100)
is placed on the board to measure the output voltage at TP14 test point with reference to the ground.
Core power can be measured by following these steps:
1. Measure the output voltage (VOUT) at TP14.
2. I = (VOUT/5)
3. Core Power consumed P= (1.2 V)*I
For example, when the voltage measured across TP14 as 0.5 V, then the consumed core power is 0.12 W.

3 – Key Components Description and Operation
14 IGLOO2 FPGA Evaluation Kit User Guide
1.2 V Regulator
LX7165
0.05Ω_1%
5.0 V
1.2 V Gain
100
5.0 V TP14
U31
TP16 TP17
Figure 5. Core Power Measurement
Figure 5 shows the onboard core power measurement circuitry.
1.2 V Current Sensing for Flash*Freeze
The IGLOO2 device consumes very low power in Flash*Freeze mode. The voltage across the sense resistor (0.05
ohms) needs to be measured directly using a precision digital multi-meter that can read sub milli-volts. Test points
TP16 and TP17 can be used to directly measure voltage across the 1.2 V sense resistor.
To convert the voltage measured across sense resistor to power, use the following equation:
𝑃𝑜𝑤𝑒𝑟 = (voltage_measured_in_milli_volts
0.05 )∗1.2
1.8 V Current Sensing
For applications which require current measurement high precision Operational Amplifier circuitry (U32 with gain 100)
is placed on the board to measure the output voltage at TP15 test point with reference to the ground.
1.8 V power can be measured by following these steps:
1. Measure the output voltage (VOUT) at TP15.
2. I = (VOUT/5)
3. Power consumed P= (1.8 V)*I
For example, when the voltage measured across TP15 as 0.5 V, then the consumed core power is 0.18 W.
1.8 V Regulator
LX7167
0.05Ω_1%
5.0 V
1.8 V Gain
100
5.0 V TP15
U32
Figure 6. 1.8 V Power Measurement
Figure 6 shows the onboard 1.8 V power measurement circuitry.
Note: The measured accuracy is ± 10%.

3 – Key Components Description and Operation
IGLOO2 FPGA Evaluation Kit User Guide 15
Memory Interface
Dedicated I/Os are provided for HPMS DDR and fabric DDR for the IGLOO2 device. Apart from the dedicated I/Os,
regular I/Os can also be used to connect to other memory devices. Refer to Figure 7.
Mobile LPDDR SDRAM
An individual chip, 512 Mb LPDDR SDRAM memory is provided as flexible volatile memory for user applications. The
LPDDR interface is implemented in bank 0. The specifications of LPDDR SDRAM are listed below:
•MT46H32M16LF – 8 Meg x 16 x 4 banks
•Density: 512 Mb
•Data rate: LPDDR 16-bit at 400 Mbps = 6.4 Gbps
Note: For more information, refer to page 3 of Board Level Schematics document (provided separately).
SPI Serial Flash
The specifications of SPI Flash are listed below:
•Density: 64 Mb
•Voltage: 2.7 V - 3.6 V
•Frequency: 104 MHz
•Supports: SPI modes 0 and 3
•IGLOO2 HPMS - SPI0 interfaced to SPI flash
Note: For more information, refer to page 8 of Board Level Schematics document (provided separately).
IGLOO2 FPGA
LPDDR
MT46H32M16LFBF-6
Control lines
SPI Flash
W25Q64FVSSIG
MDDR- Bank0
Bank2
CLK
SPI_0
DQ[15:0]
A[13:0]
Winbond Electronics
Micron
Figure 7. IGLOO2 Memory Interface

3 – Key Components Description and Operation
16 IGLOO2 FPGA Evaluation Kit User Guide
SERDES0 Interface
The SERDES0 is having four lanes connected as below:
1. Lane0 is directly routed to the PCIe connector.
•TX Pad trace AC Coupling trace via (to bottom layer)trace PCIe connector pad
•RX Padtrace PCIe connector pad
2. Lane1 is used for loopback testing. This path is routed between the Tx and Rx with a 6 inch trace and 2
vias.
•TX Pad via (to Bottom layer) trace AC Coupling trace via (to top layer) RX pad
3. Lane2 routed to SMA connectors.
•TX Pad trace AC Coupling trace SMA connector pad
•RX Pad trace via (to bottom layer) trace via (to top layer) SMA connector Pad
4. Lane3 is routed to Marvell PHY (88E1340S).
•TX pad trace AC Coupling trace via trace routed in (6th layer) via (to top layer)
Marvel PHY pin
•RX pad via trace routed in 6th layer via (to top layer) trace AC Coupling trace
Marvel PHY pin
SERDES0 reference clock 0 is routed directly from the PCIe connector to IGLOO2 FPGA.
SERDES0 reference clock 1 is routed from the onboard 125 MHz clock oscillator and optionally routed from SMA
connectors through LVDS Mux/Buffer chip.
Expected SERDES reference clock specifications:
•Voltage level: 3.3 (± 0.3)V
•Differential LVDS
Symmetry: 50% (± 10%)
Rise/Fall Time: 1nsec Max @ 20% to 80% of supply (3.3 V)
Output Voltage Levels: “0”=0.90 Minimum, 1.10 Typical
“1”=1.43 Typical, 1.60 Maximum
Differential Output Voltage: 247 mV Minimum, 454 mV Maximum

3 – Key Components Description and Operation
IGLOO2 FPGA Evaluation Kit User Guide 17
IGLOO2
FPGA
SERDES0
RXD1
TXD0
TXD1
RXD0
REF CLK1P
Loopback
RXD3
TXD3
RXD2
TXD2
REF CLK1N
REF CLK0
PCIe
Connector
Marvell
PHY
Marvell
PHY
On board
Oscillator
MUX Circuit
3.3 V
A
B
MUX
O/Ps
SMA
Lane1
Lane0
Lane2
Lane3
SMA
O/P Sel
MUX Sel J23
J22
3.3 V
Figure 8. SERDES0 Interface
For more information on J22 and J23 jumpers, refer to Table 4.
Note:
•SERDES0 TXD pairs are capacitively coupled to the IGLOO2 device. Series AC coupling capacitors are used to
provide Common mode voltage independence.
•The AC coupling capacitors are not provided for SERDES 0 RXD signals. The mating board should have the AC
coupling capacitors.
•For more information, refer to page 4 of Board Level Schematics document (provided separately).

3 – Key Components Description and Operation
18 IGLOO2 FPGA Evaluation Kit User Guide
USB Interface
The SMSC USB3320 is a high speed USB 2.0 ULPI transceiver. It includes full support for the optional OTG protocol.
CPEN: External 5 V supply enables. It controls the external VBUS power switch.
IGLOO2
FPGA
USB- PHY
USB3320
Control lines
DATA[7:0]
Micro-AB
USB
Connector
ID
DM
DP
VBUS
ESD
Diodes
Jumper
MAX1823B
5P0V
CPEN
Bank2
26 MHz
REFCLK
XO
P1
J24
U19
U20
VBUS
VBUS
2.2uF
1K
OTG
Capable
Figure 9. USB Interface
Note: For more information, refer to page 10 of Board Level Schematics document (provided separately).
Marvell PHY (88E1340S)
The IGLOO2 Evaluation Kit utilizes the on board Marvell Alaska PHY device (88E1340S) for Ethernet
communications at 100 or 1000 Mbps. 88E1340S has four independent Gigabit Ethernet transceivers, but the board
uses only one transceiver. Each transceiver performs all the physical layer functions for 100BASE-TX and
1000BASE-T full or half duplex Ethernet on CAT5 twisted pair cable. The PHY connection to a user-provided
Ethernet cable is through an RJ-45 connector with built-in magnetics.
The 88E1340S device supports the quad SGMII for direct connection to an IGLOO2 chip. Refer to Figure 10.
The 88E1340S is configured through the CONFIG [3:0] pins and CLK_SEL [1:0].
CLK_SEL [1:0] is used to select the reference clock input option. On board, the status of CLK_SEL0 is High and
CLK_SEL1 is Low. REF_CLK is the 125 MHz reference differential clock input. It consists of LVDS differential inputs
with a 100Ω differential internal termination resistor.
•RCLK – Gigabit recovered clock
•SCLK – 25 MHz synchronous input reference clock
•Expected reference clock (REF_CLK) specifications
Voltage level: 3.3 (± 0.3)V
Differential LVDS
Symmetry: 50% (± 10%)
Rise/Fall Time: 1nsec Max @ 20% to 80% of supply (3.3 V)
Output Voltage Levels: “0”=0.90 Minimum, 1.10 Typical
“1”=1.43 Typical, 1.60 Maximum
Differential Output Voltage: 247 mV Minimum, 454 mV Maximum

3 – Key Components Description and Operation
IGLOO2 FPGA Evaluation Kit User Guide 19
SGMII
Magnetics/Jack
P0
0
1
2
3
SERDES0
LANE3
IGLOO2 FPGA
FT4232H
USB
Marvell PHY
88E1340S
1588 REFCLK+
25 MHz
JTAG
J13
U14
RCLK1
Clocks
SCLK
REF_CLKP
REF_CLKN
XTAL_IN
XTAL_OUT
RCLK2
Differential Clocks
MDC/ MDIO/ INT/ PHY_RST
On Board
Oscillator-
125MHz
Mux
SMA
Connectors
1588 REFCLK-
G1
H1
Bank7
Figure 10. IGLOO2 Marvell PHY Interface
Note: For more information, refer to page 11 and 12 of Board Level Schematics document (provided separately).

3 – Key Components Description and Operation
20 IGLOO2 FPGA Evaluation Kit User Guide
Programming
The IGLOO2 device can be programmed through the JTAG interface. Figure 11 shows various ways of IGLOO2
programming.
MUX
S
RVI
HEADER
FP4 Header
JTAG
SC_SPI
I0
I1 FP4 Cable
ETM Trace
Debugger Jlink Tracer Cable
FLASH_GOLDEN_N
JTAG_SEL
J8
J9
J4
J5
3P3V
3.3V
FT4232H
U14
CD1
IGLOO2 FPGA
Figure 11. IGLOO2 Programming Interface
JTAG_SEL: JTAG_SEL is used to switch between FP4 header (High) and RVI header or ETM header (Low).
For more information on J8 jumper, refer to Table 4.
RVI Header
One 10X2 RVI header is provided on the board for debugging. This header allows plugging in the Keil ULINK
debugger or IAR J-Link debugger.
FlashPro4 Programming Header
The IGLOO2 device on the Evaluation Kit can be programmed using a FlashPro4 programmer. In addition, FlashPro4
is used for software debugging by SoftConsole.
Note:
•For more information, refer to page 13 of Board Level Schematics document (provided separately).
•For more details, refer to the IGLOO2 Programming User Guide.
FTDI Interface
FT4232H chip features are listed below:
•USB 2.0 high speed (480 Mbps) to UART/MPSSE IC
•Single-chip USB to quad serial ports with a variety of configurations
•Entire USB protocol handled on the chip. USB specific firmware programming is not required
•USB 2.0 high speed (480 Mbps) and Full Speed (12 Mbps) compatible
•Two MPSSE on channel A and channel B, to simplify synchronous serial protocol (USB to JTAG, I2C, SPI,
or bit-bang) design
•Fully assisted hardware or X-On/X-Off software handshaking