Mitsubishi Melsec A series User manual
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SM
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Instra
MITSUBISHI
User's
Manual
Mitsubishi Programmable Logic Controller
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INTRODUCnON
Thank
you
for
choosing
the
Mitsubishi MELSEC-A Series
of
General Purpose Programmable
Controllers. Please read
this
manual carefully so
that
the equipment is used
to
its
optimum.
A
copy
of
this manual should be forwarded
to
the end User.
18
(NAJ 66058·A
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CONTENTS
1. GENERAL DESCRIPTION
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1-1
2.
SPEC
IFICATIONS
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2-1
"'2-5
2.1
General
Specifications
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2-1
2.2
CPU
Unit
Performance Specifications
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2-2
2.2.1 Functions
and
specifications
of
CPU
unit
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.
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.
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2-2
2.2.2 Performance specifications
of
CPU
unit built-in power supply
................
2-4
2.3 Memory Specifications
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2.4 Battery Specifications .
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2-5
3.
HANDLING
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3-1-3-10
3.1
Handling Instructions .
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3-1
3.1
.1
CPU
...................
.
...................................
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3-1
3.1
.2 Memory chips
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........................................
3-1
3.1.3 Battery
......
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3-2
3.2
CPU
Unit
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.
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. . 3-3
3.2.1 Nomenclature
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3-3
3.2.2 Setting
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........................
. . 3-7
3.2.3 Latch
range
setting
and
latch clear
..................................
..
. 3-9
4. CONCEPT AND CAUTIONS FOR
AOJ2CPU
SYSTEM CONFIGURATION .
......
.
4-1
"'4-7
4.1
Assignment
and
Concept
of
1
/0
Numbers
............
.
.............
.
...........
4-1
4.2 Precautions
for
Use
of
Type
AOJ2PW
Extension Power Supply
Unit
...
.
..........
.
..
4-3
5. LOADING AND INSTALLATION
..........
..
.........
..................
5-1-5-
11
5.1
Unit
Mounting
.......
.
..........
.
.......................................
5-1
5.1.1 Mounting instructions
.......................
.
...
. .
..
...............
5-1
5.1.2 Installation .
...
..
..
.
.........
.
.............................
.
......
5-2
5.1.3
Unit
-to-unit mounting method .
.......................................
5-3
5.1
.4
Unit
-to-unit mounting
..........
.
...................
.
....
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.
..
.
...
5-6
5.2 Wiring . .
.....
.
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.
...
.
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..
.......................................
5-7
5.2.1 Wiring instructions
.....
.
...
.
.......................................
5-7
5.2.2 Wiring
to
unit
terminals . .
....................
.
....
.
................
5-10
6. TEST OPERATION
AND
ADJUSTMENTS
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.
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6-1
-6-2
6.1
Check
Points Before Start
of
Test Operation
..
.
.........
. . .
.....................
6-1
6.2 Test Operation
and
Adjusting Procedure. .
...........................
.
...
.
.....
6-2
I
B(
NA)
~
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7. MAINTENANCE
AND
INSPECTION
......................................
7-1
-7·3
7.1
Daily Inspection
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..
. 7-1
7.2 Periodic Inspection
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. . 7-2
7.3 Battery Replacement
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7-3
7.4 Battery Replacing Procedure
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7-3
APPENDICES
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.
APP-1
APPENDIX 1 Dimensional Outline Drawing
(AOJ2CPU
unit)
.........................
APP
-1
18
CNAl
66058.C
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__
,_._G_E_N_ER_A_L_o_e_sc_R_I_PT_Io_N
____________
~;I~ELSEC~
1. GENERAL DESCRIPTION
This manual
gives
specifications and handling procedures
for
the
AOJ2CPU (referred
to
as
"AOJ2")
and AOJ2CPU-DC24 (referred
to
as
"AOJ2-DC24")
genera
l-purpose programmablecontrollers.
For
information
on
the AOJ2CPU 1/0 units, extension power supply
units
and
1/0 cables,
see
the
AOJ2 (1/0 unit) User's Manual.
Differences between AOJ2 and
AOJ2
-DC24
Item AOJ2 AOJ2-DC24
Input
power
supRIY
1
OOV
/200V
AC
24V
DC
Table
1.1
Differences between AOJ2
and
AOJ2·DC24
In this manual,
the
"AOJ2CPU" indicates
that
the
CPU
used
may
either be AOJ2
or
AOJ2
-DC24.
In the AOJ2 system, the number
of
1/0 available can
be
expanded
in the
range
28
to
336
points (maximum 480 points when using
an
extension
base
unit).
With a wall mounting method
(thin
type),
unit
thichness is
only
41
mm (1.61 inch). With a
unit
-
to
-
unit
moun-
ting
method, required
space
is
475cm2 (19 x 25) (73.6"sq. (7.48 x
9.84)). The system allows controlling
of
up
to
84
1/
0.
Included
with
the AOJ2CPU
unit,
the
fo
llowing components and
manuals
are
included.
Please
make
sure
of
these items afteropening
the
package.
AOJ2CPU
Unit
4KRAM
(furnished
to
the
unit)
A6BAT
(furnished
to
the
unit)
User's manual
for
AOJ2
(CPU
unit
edition)
User's manual
for
AOJ2
(1
/0
unit
edition)
1-1
1
1
1
18
(NA}
66058-D
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__
2_._s_Pe_c_IF_Ic_A_T_Io_N_s
____
~--------~
-
;IAfELSEC~
2. SPECIFICATIONS
2.1 General Spec
ifi
ca
tions
This chapter
desc
r
ibes
t
he
specifications
an
d perfor
mances
of
the
AOJ2C
PU
system.
Gen
eral specifications common to
ea
ch unit
for
AOJ2C
PU
system
are
shown in Table 2.1.
I
tam
Spec
ificat
io
ns
Operating
ambient
o
to
55"c
temperature
Storage ambient -20
to
75"C
tempe
r
ature
Operating ambient
10
to
90%R
H,
non~ondensing
humidity
Storage ambient
10
to
90%RH, non-condensing
humidity
Frequency Acceleration
Amp
litude SWeep
Count
Vibration Conforms 0.075mm
resistance
to
10
to 55Hz -(0.003inch)
10
times
JISC0911
55
to
150Hz
1g
-*(1 octave/minute)
Shock resistance Conforms
to
JIS
C
0912
(109 x 3 times in 3 directions)
Noise durability By noise simulator
of
1500Vpp
noise voltage,
1!-'S
noise width and
25
to
60Hz noise frequency
Dielectric 500V
AC
for
1
minute
across batch
of
AC
external terminals
withstand voltage and ground
500V
AC
for 1 minute across
DC
external terminals
and
ground
Insulation sMn
or
larger by
SOOV
DC
insulation resistance tester across
resistance
AC
external terminals
and
ground
Grounding Class 3 grounding; grounding is
not
required when it
is
impossible
Operating Free
of
corrosive gases. Dust should be minimal.
ambience
Cooling
method
Self-cooling
TaiJie 2.1 General Specifica
ti
ons
lREMAR
KSj
One octave marked * indicates a chan
ge
from
the
initial frequency
to
do
uble
or
half frequency. For example,
any
of
the
changes from 10Hz
to
20
Hz, from
20
Hz to 40Hz, from
40
Hz
to
20
Hz,
and 20Hz
to
10Hz are referred
to
as one
octave.
2-
1
IB
I
NAJ
66058-0
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__
2_.
_s_PE_c_rF_rc_A_rr_o_N_s
______________
-J;'AfELSEC~
2.2 CPU Unit Performance Specifications
This section describes the performance specifica
tions
of
the
A
OJ
2CPU
u
nit
.
2.2.1 Functions and specifications
of
CPU
unit
Table 2.2 shows performances and specificat i
on
s of
the
A
OJ
2CPU
unit.
~
Spec
ifications
I A
OJ
2 I
AOJ
2-
0 C24
Control method
Stored
program, repetitive
operation
1/0
control
method
Direct system
Language dediceted
to
sequence control
Programming language (combined use
of
relay symbol
type
,
logic symbolic language, end SAP language)
Sequence instruction 21 types
Instruction Basic instruction
38
types
Application 21
types
instruction
Processing speed Sequence instruction
4.4
to
5,6,.s/step
Memory
ca
pacity Max. 7K steps
4KEROM
3K
steps
Memory capacity 4KRAM
3K
stePS
and
memory
type
4KROM 3K steps
16KRAM 7K steps
8KROM
7K
steps
336
points
Number
of
1/0
points (Maximum
480
points
when using extension base unit)
M/LOOOO
to
2047
Internal relay (M/Ll (2048 points. Setting
for
M
/L
to
be
made
with
A6GPP
or
A7PU.)
Link relay (B)
8000
to
83FF
(1024 points. Available
for
internal relay)
Number
of
points
128 points
100ms
TO
to
T79
(80
po
ints, 0.1
to
3276.7
sec)
Timer 1
0ms
T80
to
T119
(40 points, 0.01
to
327.67
sec)
Retentive (100ms)
T120to
T127
(8 points, 0 .1
to
3276.7
sec)
Counter
CO
to
C127 (128 points, 1
to
32767)
Data
register
(0)
DO
to
05
11 (512
points
,
16
bits)
Annunciator (F)
FO
to
F255
(256 points, 1 bit)
Index register IV,
Zl
V, Z (2 points,
16
bits)
Pointer (P)
PO
to
P63 (64 points)
Special relay
(M)
M9000
to
M9255 (256 points)
Special register
(0)
09000
to
09
127 (128 points)
Can
be
created
with
A6GPP
Comment (Comment
entered
into
the
CPU are
only
95
points,
FO
to
F94.J
Latch (power failure compensation) Available f
or
L, B,
T,
C. D
function (Range to be
set
with
A6GPP
or
A7PU.I
Tab
le
2.
2
CPU
Unit Performance Specific
at
ions (Continu
e)
2-2
I
S(NA)~O
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2_._s_Pe_c_IF_Ic_A_T_Io_N_s
______________
~;'A4ELSEC~
=----------:-
Specificirtions
I AOJ2 I AOJ2-DC24
Remote RUN/STOP function Cen
be
operated with A6GPP
or
A7
PU
.
Operation mode
at
error Operati
on
continued
at
software instruction error
STOP
to
RUN'
output
mode Operation result
at
STOP
Is
regenerated.
Print title entry Pri
nt
title cannot
be
entered Into
the
CPU.
However, It can be created with A6GPP.
Watch dog timer error monitor,
Self-diagnostic function battery error, AC down
de
tection,
blown fuse detection, etc.
Allowable Instantaneous power Within 20ms
,.
,
Within
tms
failure period
At power
on,
at
power restoration Automatic restart when
"RUN"
switch
after
power failure
is
set
to
ON. (Initial start)
IC·RAM latch device back·up Battery backup, lithium battery used
(5 years
of
guarantee period)
Parameter Latch range
to
be
set with A6GPP
or
A7PU.
Other than sequence program area.
Microcomputer mode The
content
of
utility FD is written
into
the
microcomputer area.
Watch dog time
(WDT)
200ms fixed
Weight (
kg)
0.75
*Allowable lower limit input (power supply input) is t5.6V DC.
Table
2.2
CPU
Unit Performance Specifications
2-3
IB
INAI
66058-0
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2_._sP_e_ci_FIC_A_TI_o_Ns
__________________
~;'AfE~SEC~
2.2.2 Performance specifications
of
C
PU
unit built-in power supply
2.3
Me
m
ory
Specifications
Table 2.3 shows performance specificati
ons
of
the
power supply i
n-
co
rporated in
the
AO
J2CPU unit.
~
Pe
rf
ormance Specification
m AO
J2
A
OJ
2-DC24
100
to
12ov
Ac
+
10V
-16%
24V
Dc
+30%
I
nput
power (85
to
1
32V
AC) -36%
200
to
240V
AC+10% (15.6
to
31
.
2A
DC)
-
16%
(170
to
264V
ACI
I
nput
current 0.7A
or
less/0.35A
or
l
ess
1.5A
or
l
ess
(15.
6V
DC)/
1A
or
l
ess
(24V
DCI
...
Input
frequency
"
a.
50
/
60Hz
~
5%
---
c
-Maximum
input
56VA
or
less
---
apparent power
Input
electric power --- 24W
or
less
Inrush current
40A,
within
5ms
50A
(with
in 2ms)
Effi
ciency
65%
or
mo
re
65%
or
more
Rated
5V
DC
2A 2A
output
current
24V
DC
0.5A
-
--
;
c. Over-
5V
DC
2.4A
2.4A
...
" current
0 protection
24V
DC
0.6A
-
--
Output
rise time
Within
150ms
after
power
on
Wi
thin
150msafter
power
on
Power supply display
LED
display provided
LED
display provided
Table
2.3
Performance Specifications of C
PU
Unit Built-In Power Supply
Table
2.4
shows memory specifications ava
il
able for
the
AOJ2CP
U.
~
4KEROM
4KR
AM
4K
ROM 1
6K
RAM SK
ROM
pe
EEPROM
Memory (Aead/Write) IC-RAM EP-ROM IC-RAM EP-ROM
specifications Wri
te
(Read/Write) (Read
only)
(Read/Write) (Read
only)
disabled
during RUN
Memory
8K
bytes
8K
bytes
8K
bytes
32K
bytes
16K
bytes
capaci
ty
Number
of
3K
steps
3K
steps
3K
steps
7K
steps
7K
steps
steps
Struct
u
re
28
pin
IC package
Table 2.4 Memory Specifications
2-4
IB
(NA)
66058-0
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2_._sP_E_CI-~IC_A_TI_o_Ns
__________________
~;'Af£LSEC~
2.4 Battery Specification
Table 2.5 shows battery specifications
for
RAM memory backup
and
power failure compensation function.
::--------:
A6BAT
pe
Nominal voltage 3.6V DC
Battery guarantee pe'riod 6 years
Total power failure time 4 years
at
40°C
330
days at 76°C
Application I
C-RAM
memory backup and
powerfailure compensation function
Size mm (inch) 16 (0.63) diameter x
30
(1.18)
Table 2.5 Battery Specifications
2-5
18
(NA)
6605S-A
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__
3_._HA_N_o_L_IN_G------------------~~~ELSEC~
3.
HANDLING
3.1 Handling Instructions
3.
1.1
CPU
3.1.2 Memory chips
This chapter explains the handling instructions from unpacking
to
installation
and
also the nomenclature
and
setting
of
various condi-
tions.
This section explains the handling instructions
for
the unpacking
to
installation
of
PC
main
unit
, memory, battery, etc.
(1) Since the
case,
terminal block connector,
and
pin connector
of
this
PC
are
made
of
plastic, do
not
drop
or
subject
to
mechanical
shock.
(2) Do
not
remove the printed circuit board
of
any
unit
from
its
case
. Removal may
cause
board
damage.
(3)
When
wiring, take care
to
prevent entry
of
wire offcuts
into
the
unit.
If
any conductive debris
has
entered the
unit,
make
sure
that
it
is
removed.
(4) Tighten the
unit
mounting
screws
and
terminal
screws
in the
following
ranges.
Screw Tightening Torque
Range
(kg
-em)
1/0
unit
terminal blockterminal screw (M3 screw)
5to
8
1/0
unit
te
rminal block mounting screw (M4 screw) 8
to
14
CPU
unit terminal block screw 10
to
14
(M4 screw) (Power input section)
Unit mounting screw (not required normally)
8to
12
(M4
screw)
(1) To load the memory chip
into
the socket, securely
press
the
memory chip
into
the socket
and
then lock.
(2) Never place the chip on metal, which may allow current flow,
or
on
an
object which
is
charged
with
static electricity,
such
as
wood, plastic, vinyl, fiber, cable,
and
paper.
(3) Do
not
touch the
legs
of
the chip. Also, do
not
bend the
legs.
(4)
When
mounting the memory,
be
sure
to
fit
the chip
as
indicated
on the socket.
If
reversely installed, the chip
will
be
damaged
.
3-1
IB
(
NA)
6605&-A
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3_._H_AN_D_L_IN_G
__________________
~;f~ELSEC~
3.1.3 Battery
(5)
If
IC-RAM
is
removed
from
the socket, memory data
will
be
lost.
Therefore, caution should
be
exercised.
IMPORTANT
I
Before installing and removing the memory chip
to
and from
the
CPU,
be
sure
to
turn
off
the
power. If installation or
removal
is
performed during power on, the chip will
be
damaged.
(
1)
Do
not
short-circuit the battery.
(2) Do
not
disassemble
the
battery.
(3) Do
not
throw
the battery
into
flames. .
(4) Do
not
heat
the
battery.
(5) Do
not
solder the poles
of
the
battery.
3-2
18
(NA)
6€058-A
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__
3_._H_AN_o_L_IN_G--------------~--~~~ELSEC~
3.2
CPU
Unit
.This section describes
the
nomenclature and setting
of
t
he
AOJ2CPU
unit.
·
3.2.1 Nomenclature
Illuminates when AC power
is
on
a.nd
6V
DC
output
is
within normal
level
.
Indicates CPU operating status.
ON: Indicates
that
sequence ope-
ration is being executed
with
RUN key switch
set
to
RUN
or
CPU is not in remote
STOP state.
OFF:
Indicates
that
RUN key
switch is
In
STOP position
or
CPU is not
in
remote STOP
or
RESET
state.
Aeshing:
Indicates
that
error has been
detected
by
self-diagnostic
function
or
latch clear ope-
ration has been performed.
Composed
of
AC
input
terminal,
100/200V
AC
select terminal,
LG
(line ground) terminal, FG (flame
ground) terminal, and
24V
DC
output
terminal.
For
details and line
voltage, refer
to
the
AOJ2 User's
Manual
11/0
Unit Edition).
RUN: Executes operation
of
se-
quence program.
STOP: Turns
all
outputs
off
and
stops
the
operation
of
se-
quence program.
L.CLR: Sets
al
l
data
memories, ax·
cept
special relay
(M)
and
special register (D).
in
the
latch area
to
"OFF"
or
"0".
RESET: Resets hardware. Performs
reset at operation error oc-
currence and initializes ope-
ration. Latch memory is
not
cleared.
Sets memory loading, RAM/ROM
selection, and MEMORY PROTECT
switch setting. (Capped with a cover)
For
details, refer
to
the
following
page.
For
setting, refer
to
Section
3.2.2.
Used
to
connect
with the peripheral
equipment. (When
the
peripheral
equipment is not installad,
be
sure
to
place a cover
on
this connector.)
~
It
is
necessa,.Y
to
set
or
install the shaded area
before
test
run
and
adjustments.
3-3
18
(NA)
eeo6a.A
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__
3_._HA_N_D_L_IN_G------------------~~~ELSEC~
POINT I
(1) RUN LED remains
on
if
the
annunciator (F) is set.
(2) For
the
sett.ing
of
the
RUN/STOP switch
to
"L
.
CLR"
(Latch Clear), refer
to
the
AOJ2CPU Programming
Manual.
(3) Operation is started when
the
power is turned
on
with
the
RUN/STOP switch set
to
"RUN"
position. When
the
switch
is
changed from
RUN
to
STOP,
the
operation
is
stopped
and
all
outputs are turned off.
In
this case,
all
control infonnation in
RUN
mode completely remains.
If
the
switch
is
set
again
to
RUN
without
resetting,
the
operation
is
resumed. Usually,
the
operation may
be
started
by
turning
on
the
power with
the
switch
set
to
RUN.
3-4
IB
INA)
66058-A
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__
3_._H_AN_o_L_IN_G------------------~~~ELSEC~
Details
of
Memory Setting Area
Loaded with
IC
·RAM/EP·ROM/EEP
ROM.
Fixes
the
memory in the memory
loading socket. (Use a flat-blade
screwdriver
to
lock or unlock. For
the rotating direction, refer
to
the
seal
on the socket.)
Selecu
memory capacity.
4K
or
8K,
1-
=----=
~-11
to
be
used. Set using a short-circuit
chip.
Enables
or
disables write
to
the
mem-
ory when IC-RAM
or
EEPROM
is
installed Into
the
memory loading
socket.
M.PRO iniQWposition: disables write
M.PRO inlOFFJposition:
enables write
Connects
the
lead wire
of
the
battery.
(The
battery
lead is removed before
sh
i
pment
to
prevent battery di.-
charge.l
•
For
setting, refer
to
Section 3.2.2.
Selects RAM,
ROM,
or
EPROM. Use
the
shortchip
to
select.
Backs up
IC-RAM
memory and
the
power failure compensetion feature.
E::l
It is necessary
to
set
or
install the shaded area before
test
run and adjustments.
3-5
IB
INA)
60068-A
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3.
HANDLING
IDetails
of
Power Supply Terminal Block I
AOJ2-DC24
Terminal screw
M4x0.7x8
Power Input terminals
Connect 24V
DC
power supply.
LG
terminal
Ground terminal
for
power filter.
3-6
/MELSEC;4
Terminal cover
Protects
the
terminal block. Must
be
kept
on
the
terminal block except
during wiring.
FG terminal
Connected with shielding pattern
on
the
printedcircuit board.
18
INA166058-0
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__
·
3_._H_AN_o_L_IN_G
__________________
~;'n4ELSEC~
3.2.2 Setting
This section descr
ibes
the setting
of
IC·
RAM,
EP
·ROM, and
EEP
-
ROM
,
the
setting
of
the memory protect switch, and t
he
installation
of
the battery.
(1) Memory loading and setting
P-ROM/EEPAOM/IC·RAM operation
Hold
the
memory
without
touching
the
leg
s.
Turn and loosen
the
memory lock
in
the
socket.
Insert the memory
with
the
concave
set as Indicated
on
the
socket.
Turn and fix
the
memory lock wh
ile
pressing
the
memory with fingers.
Make
SIJre
that
the memory
is
not
lifted from
the
socket.
Apply the furnished mesking tape
to
the
ROM
SIJrface.
Insert
the
setting pin Into
[BQMJ
pin
connector.
Insert the setting
pin
into
@RJ
or
liD9
pin connector according
to
the cepaclty
of
the EP·
AOM
to
be
used.
Completed
The following
flow
chart
shows
how
to
install the memory i
nto
the memory socket and the placement
of
the setting pin accord-
ing
to
the memory type.
How
to
hold
the
rMmory
Insert
the
setting pin Into
IROMI
pin
connector.
Insert the setting pin into
[E)
or
liDS)
pin
connector
according
to
the IC.RAM capacity.
Insert the setting pin Into
IE
ROM)
pin connector.
Insert the setting
pin
into @Kl pin
connector according
to
the EEPROM
capacity.
Memory
letting
Memory T
ype
Pin Connector
Setting
Memory
Capc
.
ity
Setting
Memory
..
tting
(Memory
type)
4KROM
lW
~
~
1:&0
~
aa
BKROM
WJ
i'i
• mJ
~
@:])
4KAAM
lEI
lH!
I!QM)
[BAM]
~
...
16KRAM ~ IIKJ
~
•
l~t~~l
a:l
[E)
em
m2Ml
1&0
~
4KEROM
a:l
IB]
~
~
&I
I:IJ indicates
the
setting
pin
inserting
pos
ition.
3-7
IB
(N
.AI
6&l6e-A
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__
3_
.
_H_AN_o_L_IN_G------------------~~'~ELS£C~
POINTT
When
using 16KRAM, connect a peripheral
unit
to
the
CPU
and then perform
the
following memory clear operation.
IA6GPPI Key operation
BG
[Molle
CUISOf
to
"PC
MEMORY
All
CLEAR"
position}(~}{~){~
...
..
...... Set
the
AOJ2 key switch
to
RESET.
IA7PUl Key operation
BBGGJB88
80
8ITJ
........... Set
the
AOJ2 key switch
to
RESET.
After
completion
of
operation
with
one
of
the
above periph·
era'l
units, perform normal write operation.
(2) Setting the memory protect switch
When
IC·RAM
or
EEPROM memory
is
used,
the
memory protect
switch should
be
set
to
theiONlposition after
writing
programs in
order
to
avoid the memory contents from being rewritten due
to
.
misoperation
of
the peripheral device (A6GPP
or
A7PU). Set this
switch
to
iOFFlbefore correcting
the
memo
ry
contents.
~
Memory Protect Switch Setting
To set
to
ON
To
set
to
OFF
Memory Protect I
ONI
~
@[]
~
it
D
setting switch
loFFI
loFFI
Memory ProtectSwitch Setting
(3) Installing the battery
Since
the
battery connector
is
factory-disconnected, connect the
connector according
to
the
following procedure when using the
RAM memory
or
power failure compe.nsation function.
Open
the
cover
of
memory setting
area
in
the
CPU
front.
Make sure
that
the
battery is installed
properly,
Connect
the
battery
connector
to
the
printed circuit board
connector
after
checking its direction.
Completed
IREMARKS I
Battery
Connector for
battery
lead
Since
the
battery connector
is
removed before shipment
to
prevent discharge
during
tra
nsportation and/or storage, connect
the
connector when using
the
battery. 3-8
18
(NA)
66058-A
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
__
3_._HA_N_o_uN_G--------------------~;'AfELSEC~
3.2.3
Latch range setting and latch clear
(
1)
The
latch function retains
the
data
of
the
specified devices
(devices in
the
latch range)
if:
(a)
The
power
is
switched off.
(b)
The
PC
is
reset.
(2) Devices
L,
B,
T, C and D can
be
latched. Any
of
the
following
latch and non-latch ranges may
be
defined by
the
peripheral
device:
------
Non-Latch
Range
Latch
Range
MOto
M2047
TO
to
T127
No latch
CO
to
C127
DO
to
0511
BO
to
B3FF
MOto
M1023 L1024
to
L2047
Second-half
TO
to
T39/T80
to
T40
to
TI9/T100
to
latch T99/T1
20
to
T1
23
T1
19/T124
to
T1
27
(1
/2
latch)
CO
to
C63 C64
to
C127
DO
to
D255 D256
to
D511
BO
to
81
FF
B200to
B3FF
LO
to
L2047
TO
to
T127
Full latch
CO
to
C127
DO
to
0511
BOto B3FF
(3)
The
AOJ2
defaults
to
" 1
/2
latc
h.
"
When
the
AOJ2
is
used for
the
fi
rst time, latch clear must
be
performed
or
the
latch range parameter changed
to
"no
latch."
(Without this initialization, normal sequence processing may
not
be
ensured because
RAM
data
of
the
latched devices
is
indefinite.)
(a)
When
the
latch function
is
not used, change
the
latch range
parameter
to
"no
latch"
and reset.
(b) When
the
latch function
is
used, perform latch clear.
(4) Latch clear procedure
(a)
Latch clear initializes
the
latch and non-latch range data and
causes
the
devices
to
be as follows:
1) Y, M/L, F, B
.....
Switched off.
2) Special M (9000
to
9255)
. .
.............
Retained.
3)
T, C
...
..
. .
.....
Contact and coil are switched off.
Present value
is
set
to
0.
4) 0 , Z, V
..
.
...
...
Contents are reset
to
0.
5) Special D (9000
to
9127)
...
.
..
.
......
. .Retained.
3-9
IB
!NAJ
6605&V
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