Motorola CPU32 User manual

M68300 Family
CP 32 RM / AD
REV I
CENTRAL PROCESSOR UNIT
REFERENCE
MANUAL
" ®
MOTOROLA

CPU32
REFERENCE MANUAL
Motorola reserves the right to make changes without further notice to any products herein to improve reliability,
function or design. Motorola does not assume any liability arising out of the application or use of any product or
circuit described herein; neither does
it convey any license under its patent rights northe rights of others. Motorola
products are notdesigned, intended, or authorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or for any other application in which the
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of the Motorola product could create a situation where personal injury or death may occur. Should Buyer
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© MOTOROLA INC., 1990

PREFACE
This reference manual describes programming and operation of the CPU32
instruction processing module, found
in the M68300 Family of embedded
controllers. It is a part of a multivolume set of manuals -each volume
corresponds to a major module in the M68300 Family.
A user's manual for each device incorporating the CPU32 describes processor
function and operation with reference to other modules within the device.
This manual consists of the following sections and appendix:
Section 1 Overview
Section 2 Architecture Summary
Section 3 Data Organization and Addressing Capabilities
Section 4 Instruction Set
Section 5 Processing States
Section 6 Exception Processing
Section 7 Development Support
Section 8 Instruction Execution Timing
Appendix A M68000 Family Summary
Index
NOTE
In this manual, the terms assertion and negation specify driving a
signal to a particular logic state. Assert and assertion refer to
an active or true signal. Negate and negation refer to an
inactive or false signal. These terms are used independently of
the voltage level that they represent.
This manual is written for systems designers, systems programmers, and
applications programmers. Systems designers need general knowledge of the
entire volume, with particular emphasis
on Section 1, Section 7, and Appendix
A - they will also need to
be familiar with electrical speCifications and
mechanical data contained in the user's manual. Systems programmers should
become familiar with Sections 1 through 6, Section 8, and Appendix A.
Applications programmers can find most of the information they need in
Sections 1 through
5, Section 8, and Appendix A.
This manual is also written for users of the M68000 Family that are not familiar
with the CPU32. Although there are comparative references to other Motorola
microprocessors throughout the manual, Section 1, Section 2, and Appendix A
specifically identify the CPU32 within the M68000 Family, and discuss the
differences between it and related devices.
CPU32 REFERENCE MANUAL MOTOROLA
iii

MOTOROLA
iv CPU32 REFERENCE MANUAL

Paragraph
Number
1.1
1 .1 .1
1.1.2
1.1.3
1.1.4
1.1.5
1.1.6
1.1.6.1
1.1.6.2
1.1.7
1.1.8
1.2
2.1
2.2
2.3
2.3.1
2.3.1.1
2.3.1.2
2.3.1.3
2.3.2
3.1
3.2
3.3
3.4
3.4.1
3.4.1.1
3.4.1.2
TABLE OF CONTENTS
Title
Section 1
Overview
Page
Number
Features........................................................................................................1-2
Virtual Memory........................................................................................1-2
Loop Mode Instruction Execution........................................................1-3
Vector Base Register.............................................................................1-3
Improved Exception Handling..............................................................1-4
Enhanced Addressing Modes..............................................................1-4
Instruction Set.........................................................................................1-5
Table Lookup and Interpolate Instructions....................................1-5
Low-Power Stop Instruction.............................................................1-7
Processing States ..................................................................................1-7
Privilege States.......................................................................................1-7
Block Diagram.............................................................................................1-8
Section 2
Architecture
Summary
Programming ModeL .................................................................................. 2-1
Registers.......................................................................................................2-3
Data Types...................................................................................................2-4
Organization
in Registers......................................................................2-4
Data Registers....................................................................................2-4
Address Registers..............................................................................2-6
Control Registers ...............................................................................2-6
Organization
in Memory........................................................................2-7
Section 3
Data Organization and Addressing Capabilities
Program and Data References.................................................................3-2
Notation Conventions................................................................................3-2
Implicit Reference .......................................................................................3-3
Effective Address........................................................................................3-4
Register Direct Mode .............................................................................3-4
Data Register Direct ..........................................................................3-4
Address Register Direct....................................................................3-4
CPU32 REFERENCE MANUAL MOTOROLA
v

Paragraph
Number
3.4.2
3.4.2.1
3.4.2.2
3.4.2.3
3.4.2.4
3.4.2.5
3.4.2.6
3.4.3
3.4.3.1
3.4.3.2
3.4.3.3
3.4.3.4
3.4.3.5
3.4.3.6
3.4.4
3.5
3.5.1
3.5.2
3.6
3.7
3.7.1
3.7.2
3.7.3
4.1
4.1.1
4.1.1.1
4.1.1.2
4.1.2
4.2
4.2.1
4.3
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
4.3.10
MOTOROLA
vi
TABLE OF CONTENTS (Continued)
Title Page
Number
Memory Addressing Modes..................................................................3-4
Address Register Indirect.................................................................3-5
Address Register Indirect with Postincrement..............................3-5
Address Register Indirect with Predecrement ..............................3-5
Address Register Indirect with Displacement...............................3-6
Address Register Indirect with Index (8-Bit Displacement)
........ 3-6
Address Register Indirect with Index (Base Displacement)
....... 3-8
Special Addressing Modes..................................................................3-8
Program Counter Indirect with Displacement...............................3-8
Program Counter Indirect with Index (8-Bit Displacement)........3-9
Program Counter Indirect with Index (Base Displacement).......3-9
Absolute Short Address....................................................................
3-1 0
Absolute Long Address....................................................................3-11
Immediate Data..................................................................................3-11
Effective Address Encoding Summary...............................................3-12
Programming View of Addressing Modes..............................................3-14
Addressing Capabilities........................................................................3-15
General Addressing Mode Summary.................................................3-16
M68000 Family Addressing Capability...................................................3-18
Other Data Structures :...............................................................................3-19
System Stack..........................................................................................3-19
User Stacks.............................................................................................3-20
Queues.....................................................................................................3-21
Section 4
Instruction Set
M68000 Family Compatibility.................................................................. .4-1
New Instructions .....................................................................................4-2
Low-Power STOP (LPSTOP) ..........................................................4-2
Table Lookup and Interpolate (TBL) ..............................................4-2
Unimplemented Instructions.................................................................4-2
Instruction Format .......................................................................................4-3
Notation....................................................................................................4-4
Instruction Summary..................................................................................4-6
Condition Code Register.......................................................................4-6
Data Movement Instructions.................................................................4-8
Integer Arithmetic Operations...............................................................4-9
Logical Instructions................................................................................4-11
Shift and Rotate Instructions.................................................................4-11
Bit Manipulation Instructions................................................................4-12
Binary-Coded Decimal (BCD) Instructions........................................4-13
Program Control Instructions................................................................4-13
System Control Instructions..................................................................4-15
Condition Tests.......................................................................................4-17
CPU32 REFERENCE MANUAL

Paragraph
Number
TABLE OF CONTENTS (Continued)
Title Page
Number
4.4 Instruction Details.......................................................................................4-18
4.5 Instruction Format
Summary .....................................................................4-175
4.6 Table Lookup and Interpolation Instructions.........................................4-195
4.6.1 Table Example 1: Standard Usage ....................................................4-196
4.6.2 Table Example
2: Compressed Table...............................................4-197
4.6.3 Table Example
3: 8-Bit Independent Variable................................4-199
4.6.4 Table Example
4: Maintaining Precision ..........................................4-201
4.6.5 Table Example 5: Surface Interpolations..........................................4-203
4.7 Nested Subroutine Calls...........................................................................4-203
4.8 Pipeline Synchronization
with the NOP Instruction..............................4-203
5.1
5.2
5.2.1
5.2.2
5.2.3
5.3
5.3.1
5.3.1.1
5.3.1.2
5.3.1.3
5.3.1.4
5.3.1.5
Section 5
Processing States
State Transitions......................................................................................... 5-1
Privilege Levels ...........................................................................................5-2
Supervisor Privilege Level ...................................................................5-2
User Privilege
Level.. .............................................................................5-2
Changing Privilege Level .....................................................................5-3
Types of Address Space ...........................................................................5-3
CPU Space Access ................................................................................5-4
Type 0000 -Breakpoint..................................................................5-5
Type 0001 - MMU Access ..............................................................5-5
Type 0010 - Coprocessor Access................................................5-5
Type
0011 -Internal Register Access..........................................5-5
Type
1111 -Interrupt Acknowledge.............................................5-6
Section 6
Exception Processing
6.1 Definition of Exception Processing.......................................................... 6-1
6.1.1 Exception Vectors....................................................................................... 6-1
6.1 .2 Types of Exceptions...............................................................................6-3
6.1.3 Exception Processing Sequence........................................................6-3
6.1.4 Exception Stack Frame .........................................................................6-4
6.1.5 Multiple Exceptions................................................................................6-4
6.2 Processing of Specific Exceptions ..........................................................6-6
6.2.1 Reset.........................................................................................................6-6
6.2.2
'Bus Error..................................................................................................6-8
6.2.3 Address Error..........................................................................................6-9
6.2.4 Instruction Traps .....................................................................................6-9
6.2.5 Software Breakpoints ............................................................................
6-10
6.2.6 Hardware Breakpoints...........................................................................6-10
6.2.7 Format Error............................................................................................. 6-11
6.2.8 Illegal or Unimplemented Instructions................................................ 6-11
·6.2.9 Privilege Violations................................................................................6-12
CPU32 REFERENCE MANUAL MOTOROLA
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6.2.10
6.2.11
6.2.12
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.1.3
6.3.1.4
6.3.2
6.3.2.1
6.3.2.2
6.3.2.3
6.3.2.4
6.3.2.5
6.3.2.6
6.3.2.7
6.4
6.4.1
6.4.2
6.4.3
7.1
7.1.1
7.1.2
7.1.3
7.2
7.2.1
7.2.2
7.2.2.1
7.2.2.2
7.2.2.3
7.2.2.4
7.2.3
7.2.4
7.2.5
7.2.5.1
7.2.5.2
7.2.5.3
7.2.6
7.2.7
7.2.7.1
MOTOROLA
viii
TABLE OF CONTENTS (Continued)
Title Page
Number
Tracing......................................................................................................6-13
Interrupts..................................................................................................6-14
Return from Exception ...........................................................................6-16
Fault Recovery........................................................................................6-17
Types of Faults........................................................................................6-19
Type
I: Released Write Faults.........................................................6-20
Type II: Prefetch, Operand, RMW, and MOVEP Faults...............6-20
Type III: Faults During MOVEM Operand Transfers...................6-21
Type IV: Faults During Exception Processing .............................6-22
Correcting a Fault...................................................................................6-22
(Type
I) Completing Released Writes via Software.....................6-23
(Type
I) Completing Released Writes via RTE .............................6-23
(Type
II) Correcting Faults via RTE .................................................6-24
(Type III) Correcting Faults via Software.......................................6-24
(Type III) Correcting Faults
by Conversion and Restart..............6-25
(Type III) Correcting Faults via
RTE ................................................6-25
(Type
IV) Correcting Faults via Software.......................................6-25
CPU32 Stack Frames ................................................................................6-26
Normal Four-Word Stack Frame..........................................................6-26
Normal Six-Word Stack Frame............................................................6-27
BERR Stack Frame.................................................................................6-27
Section 7
Development Support
CPU32 Integrated Development Support.............................................. 7-1
Background Debug Mode (BDM) Overview...................................... 7-1
Deterministic Opcode Tracking Overview..........................................7-2
On-Chip Hardware Breakpoint Overview..........................................7-3
Background Debug Mode
(80M) ............................................................7-3
Enabling BDM.........................................................................................7-4
BDM Sources..........................................................................................7-4
External BKPT Signal .......................................................................7-5
BGND Instruction ...............................................................................7-5
Double Bus Faults .............................................................................7-5
Peripheral Breakpoints.....................................................................7-5
Entering BDM..........................................................................................7-5
Command EXecution .............................................................................7-6
Background Mode Registers................................................................7-6
Fault Address Register (FAR) ..........................................................7-6
Return Program Counter (RPC) ......................................................7-6
Current Instruction Program Counter (PCC).................................7-8
Returning
from BDM ...............................................................................7-8
Serial Interface........................................................................................7-8
CPU Serial Logic...............................................................................7-10
CPU32 REFERENCE MANUAL

Paragraph
Number
7.2.7.2
7.2.8
7.2.8.1
7.2.8.2
7.2.8.3
7.2.8.4
7.2.8.5
7.2.8.6
7.2.8.7
7.2.8.8
7.2.8.9
7.2.8.10
7.2.8.11
7.2.8.12
7.2.8.13
7.2.8.14
7.2.8.15
7.2.8.16
7.3
7.3.1
7.3.2
7.3.3
8.1
8.1.1
8.1.2
8.1.3
8.1.3.1
8.1.3.2
8.1.3.3
8.1.4
8.1.5
8.1.6
8.1.7
8.2
8.2.1
8.2.2
8.2.3
8.3
8.3.1
8.3.2
TABLE OF CONTENTS (Continued)
Title Page
Number
Development System Serial Logic.................................................7-12
Command Set.........................................................................................7-14
Command Format..............................................................................7-14
Command Sequence Diagrams.....................................................7-15
Command
Set Summary..................................................................7-17
Read
NO Register (RAREG/ROREG).............................................7-19
Write
NO Register (WAREG/wDREG) ...........................................7-19
Read System Register (RSREG).....................................................7-20
Write System Register (WSREG)....................................................7-21
Read Memory Location (READ)......................................................7-22
Write Memory Location (WRITE).....................................................7-23
Dump Memory Block (DUMP) .........................................................7-25
Fill Memory Block (FILL)...................................................................7-26
Resume Execution (GO)...................................................................7-27
Call User Code (CALL).....................................................................7-28
Reset Peripherals (RST)...................................................................7-30
No Operation (NOP) ..........................................................................7-31
Future Commands.............................................................................7-31
Deterministic Opcode Tracking................................................................7-32
Instruction Fetch (IFETCH)....................................................................7-32
Instruction Pipe (IPIPE)..........................................................................7-32
Opcode Tracking during Loop Mode..................................................7-34
Section 8
Instruction Execution Timing
Resource Scheduling ................................................................................ 8-1
Microsequencer...................................................................................... 8-1
Instruction Pipeline.................................................................................8-2
Bus Controller Resources.....................................................................8-3
Prefetch Controller.............................................................................8-3
Write-Pending Buffer.........................................................................8-3
Microbus Controller...........................................................................8-4
Instruction Execution Overlap ..............................................................8-4
Effects of Wait States .............................................................................8-5
Instruction Execution Time Calculation..............................................8-6
Effects of Negative Tails........................................................................8-7
Instruction Stream Timing Examples ......................................................8-8
Timing Example 1: Execution Overlap...............................................8-8
Timing Example
2: Branch Instructions..............................................8-9
Timing Example
3: Negative Tails.......................................................8-10
Instruction Timing Tables..........................................................................8-11
Fetch Effective Address.........................................................................8-13
Calculate Effective Address..................................................................8-15
CPU32 REFERENCE MANUAL MOTOROLA
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Paragraph
Number
8.3.3
8.3.4
8.3.5
8.3.6
8.3.7
8.3.8
8.3.9
8.3.10
8.3.11
8.3.12
8.3.13
8.3.14
MOTOROLA
x
TABLE OF CONTENTS (Continued)
Title Page
Number
MOVE Instruction....................................................................................8-16
Special-Purpose MOVE Instruction ....................................................8-16
Arithmetic/Logical Instructions.............................................................8-18
Immediate Arithmetic/Logical Instructions.........................................8-20
Binary-Coded Decimal and Extended Instructions..........................8-21
Single Operand Instructions.................................................................8-22
Shift/Rotate Instructions.........................................................................8-23
Bit Manipulation Instructions................................................................8-24
Conditional Branch Instructions...........................................................8-25
Control Instructions................................................................................8-26
Exception-Related Instructions and Operations ...............................8-27
Save and Restore Operations..............................................................8-28
Appendix A
M68000 Family Summary
Index
CPU32 REFERENCE MANUAL

Figure
Number
LIST OF ILLUSTRATIONS
Title Page Number
1-1 Loop Mode Instruction Sequence ...........................................................1-3
1-2
CPU32 Block Diagram ...............................................................................1-8
2-1 User Programming Model.........................................................................2-2
2-2 Supervisor Programming Model Supplement .....................................2-2
2-3 Status Register............................................................................................2-3
2-4 Data Organization
in Data Registers........................................,..............2-5
2-5 Address Organization
in Address Registers..........................................2-6
2-6 Memory Operand Addressing ..................................................................2-8
3-1 Single-Effective-Address Instruction Operation Word ......................... 3-1
3-2 Effective Address Specification Formats................................................3-12
3-3
Using SIZE in the Index Selection...........................................................3-14
3-4 Using Absolute Address with Indexes ....................................................3-15
3-5 Addressing
Array Items ..............................................................................3-16
3-6 M68000 Family Address Extension Words............................................3-17
4-1 Instruction Word General Format ............................................................4-3
4-2 Instruction Description Format .................................................................4-19
4-3 Table Example 1.........................................................................................4-196
4-4 Table Example 2.........................................................................................4-197
4-5 Table Example 3
..... ~ ...................................................................................4-199
6-1 Exception Stack Frame ..............................................................................6-4
6-2
Reset Operation Flowchart........................................................................6-7
6-3 Format
$0 -Four-Word Stack Frame....................................................6-27
6-4 Format
$2 -Six-Word Stack Frame ......................................................6-28
6-5 Internal Transfer Count Register..............................................................6-28
6-6 Format
$C - BERR Stack for Prefetches and Operands....................6-29
6-7 Format $C -BERR Stack During Four- or Six-Word Stack...............6-30
6-8 Format $C = m BERR Stack on MOVEM Operand ...............................6-30
7-1 In-Circuit Emulator Configuration ............................................................7-2
7-2 Bus State Analyzer Configuration ...........................................................7-2
7-3 BDM Block Diagram...................................................................................7-3
7-4 BDM Command Execution Flowchart.....................................................7-6
7-5
Debug Serial I/O Block Diagram...............................................,..............7-9
7-6 Serial Interface Timing Diagram..............................................................7-10
7-7 BKPT Timing for Single Bus Cycle.......................................................... 7-11
CPU32 REFERENCE MANUAL MOTOROLA
xi

Figure
Number
7-8
7-9
7-10
7-11
7-12
8-1
8-2
8-3
8-4
8-5
8-6
8-7
MOTOROLA
xii
LIST OF ILLUSTRATIONS (Continued)
Title Page
Number
BKPTTiming for Forcing BDM..................................................................7-12
BKPT/DSCLK Logic Diagram...................................................................7-12
Command-Sequence-Diagram Example..............................................7-15
Functional Model of Instruction Pipeline ................................................7-34
Instruction Pipeline Timing Diagram.......................................................7-35
Block Diagram of Independent Resources ............................................8-2
Simultaneous Instruction Execution........................................................8-4
Attributed Instruction Times.......................................................................8-5
Example 1 - Instruction Stream .............................................................8-8
Example 2 - Branch Taken.....................................................................8-8
Example 2 - Branch Not Taken..............................................................8-9
Example 3 - Branch Negative Tail ........................................................
8-10
CPU32 REFERENCE MANUAL

Table
Number
LIST OF TABLES
Title Page
Number
1-1 Instruction Set Summary...........................................................................1-6
3-1 Effective Addressing Mode Categories..................................................3-14
4-1 Condition Code Computations........................................................... '" ... 4-6
4-2 Data Movement Operations......................................................................4-8
4-3 Integer Arithmetic Operations...................................................................4-9
4-4 Logical Operations .....................................................................................
4-11
4-5 Shift and Rotate Operations......................................................................4-12
4-6 Bit Manipulation Operations .....................................................................4-13
4-7 Binary-Coded Decimal Operations .........................................................4-13
4-8
Program Control Operations.....................................................................4-14
4-9 System Control Operations.......................................................................4-15
4-10 Condition Tests ...........................................................................................4-17
4-11 Operation Cpde Map .................................................................................. 4-1 75
5-1 Address Spaces ..........................................................................................5-4
6-1 Exception Vector Assignments.................................................................6-2
6-2 Exception Priority Groups..........................................................................6-5
6-3 Tracing
ControL ...........................................................................................6-13
7-1 BOM Source Summary..............................................................................7-4
7-2
Polling the BOM Entry Source..................................................................7-6
7-3 CPU-Generated Message Encoding ......................................................7-9
7-4
BOM Command Summary................................................................ ~ ....... 7-18
CPU32 REFERENCE MANUAL MOTOROLA
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MOTOROLA
xiv CPU32 REFERENCE MANUAL

SECTION 1
OVERVIEW
The CPU32, the first-generation instruction processing module of the M68300
Family, is based on the industry-standard MC68000 processor. It has many
features
of the MC68010 and MC68020, as well as unique features suited for
high-performance controller applications. The
CPU32is source code and
binary code compatible with the M68000 Family.
CPU32 power consumption during normal operation is low because it is a high-
speed complementary metal-oxide semiconductor (HCMOS) device. Power
consumption can be reduced to a minimum during periods of inactivity by
executing the low-power stop (LPSTOP) instruction, which shuts down the
CPU32 and other intermodule bus (1MB) submodules.
Ease of programming is
an important consideration in using a microcontroller.
The CPU32 instruction format reflects a predominately register-memory
interaction philosophy. All data resources are available
to all operations
requiring those resources. There are eight multifunction data registers and
seven general-purpose addressing registers. The data registers readily support
8-bit (byte), 16-bit (word), and 32-bit (long word) operand lengths for all
operations. Address manipulation is supported by word and long-word
operations. Although the program counter (PC) and stack pointers (SP) are
special-purpose registers, they are also available for most data addressing
activities. Ease of program checking
and diagnosis is enhanced by trace and
trap capabilities
at the instruction level.
As controller applications become more complex and control programs become
larger, high-level language (HLL) will become the system designer's choice
in
programming languages. HLL aids rapid development of complex algorithms,
with less error, and
is readily portable. The CPU32 instruction set will efficiently
support
HLL.
CPU32 REFERENCE MANUAL OVERVIEW MOTOROLA
1-1

II
1.1 Features
Features of the CPU32 are as follows:
• Fully Upward Object Code Compatible with M68000 Family
• Virtual Memory Implementation
• Loop Mode of Instruction Execution
• Fast Multiply, Divide, and Shift Instructions
• Fast Bus Interface with Dynamic Bus Port Sizing
• Improved Exception Handling for Controller Applications
• Enhanced Addressing Modes
-Scaled Index
-Address Register Indirect with Base Displacement and Index
-Expanded PC Relative Modes
-32-Bit Branch Displacements
• Instruction Set Enhancements
-High-Precision Multiply and Divide
-Trap On Condition Codes
-Upper and Lower Bounds Checking
• Enhanced Breakpoint Instruction
• Trace on Change of Flow
• Table Lookup and Interpolate Instruction
• Low-Power Stop Instruction
• Hardware Breakpoint Signal, Background Mode
• 16.77-MHz Operating Frequency (-40 to 125°C)
• Fully Static Implementation
1.1.1 Virtual Memory
A system that supports virtual memory has a limited amount of high-speed
physical memory that can
be accessed directly by the processor and maintains
an image of a much larger "virtual" memory on a secondary storage device.
When the processor attempts to access a location
in the virtual memory map
that is not resident
in physical memory, a page fault occurs. The access to that
location is temporarily suspended while the necessary data is fetched from
secondary storage and placed in physical memory. The suspended access is
then restarted or continued. The CPU32 uses instruction restart, which requires
that only a small portion of the internal machine state be saved. After correcting
the fault, the machine state is restored, and the instruction
is refetched and
restarted. This process is completely transparent to the application program.
MOTOROLA
1-2
OVERVIEW
CPU32 REFERENCE MANUAL

1.1.2 Loop Mode Instruction Execution
The CPU32 has several features that provide efficient execution of program
loops. One of these features is the DBcc looping primitive. To increase the
performance of the CPU32, a loop mode has
been added to the processor. The
loop mode is used by any single-word instruction that does not change the
program flow. Loop mode is implemented
in conjunction with the DBcc
instruction. Figure
1-1 shows the required form of an instruction loop for the
processor to enter loop mode.
Loop mode is entered when DBcc is executed and loop displacement is
-4.
Once in loop mode, the processor performs only data cycles associated with the
instruction and suppresses instruction fetches. Termination condition and count
are checked after each execution of looped instruction data operations.
The
CPU automatically exits loop mode for interrupts or other exceptions.
ONE-WORD INSTRUCTION
~
DSce
OSee DISPLACEMENT
r--
$FFFC=-4
Figure 1-1. Loop Mode Instruction Sequence
1.1.3 Vector Base Register
The vector base register (VBR) contains the base address of the 1024-byte
exception vector table. The table contains 256 exception vectors. Exception
vectors are the memory addresses of routines that begin execution at the
completion of exception processing. Each routine performs operations
appropriate
to the corresponding exception. Because exception vectors are
memory addresses,
each table entry is a single long word.
Each vector
is assigned an 8-bit number. Vector numbers for some exceptions
are obtained from
an external device; others are supplied automatically by the
processor. The processor multiplies the vector number by four to calculate
vector offset, then adds the offset to the VBR base addre~s. The sum is the
memory address of the vector.
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Because the VBR stores the vector table base address, the table can be located
anywhere in memory.
It can also be dynamically relocated for each task
executed
by an operating system. Details of exception processing are provided
in SECTION 6 EXCEPTION PROCESSING.
1.1.4 Exception Handling
The processing of an exception occurs in four steps, with variations for different
exception causes. During the first step, a temporary internal copy of the status
register
is made, and the status register is set for exception processing. During
the second step, the exception vector is determined. During the third step, the
current processor context is saved. During the fourth step, a new context
is
obtained, and the processor then proceeds with normal instruction execution.
Exception processing saves the most volatile portion of the current context
by
pushing it on the supervisor stack. This context is organized in a format called
the exception stack frame. The stack frame always includes the status register
and program counter at the time
an exception occurs. To support generic
handlers, the processor also places the vector offset
in the exception stack
frame and marks the frame with a format code. The return-from-exception
(RTE)
instruction uses the format code to determine what information is on the stack,
so that context can be properly restored.
1.1.5 Enhanced Addressing Modes
Addressing in the CPU32 is register oriented. Most instructions allow the
results of the specified operation to
be placed either in a register or in memory.
There is
no need for extra instructions to store register contents in memory.
There are seven basic addressing modes:
1. Register Direct
2. Register Indirect
3. Register Indirect with Index
4. Program Counter Indirect with Displacement
5. Program Counter Indirect with Index
6. Absolute
7. Immediate
The register indirect addressing modes include postincrement, predecrement,
and offset capability. The
PC relative mode also has index and offset
capabilities.
In addition to the addressing modes, many instructions implicitly
specify the use of status register, SP, and/or PC. Addressing is explained fully
in SECTION 3 ADDRESSING MODES. A summary of M68000 Family
addressing modes is found
in APPENDIX A M68000 FAMILY SUMMARY.
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1.1.6 Instruction Set
The instruction set of the CPU32 is very similar to that of the MC68020 (see
Table 1-1). Two new instructions have been added to facilitate controller
applications -low-power stop (LPSTOP) and table lookup and interpolate
(TBL). The following M68020 instructions are not implemented
on the
CPU32:
BFxxx -Bit Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO,
BFINS, BFSET, BFTST)
CALLM,
RTM -Call Module, Return Module
CAS, CAS2 -Compare and Set (Read-Modify-Write Instructions)
cpxxx -Coprocessor Instructions (cpBcc, cpDBcc, cpGEN, cpRESTORE,
cpSAVE, cpScc, cpTRAPcc)
PACK, UNPK -
Pack, Unpack BCD Instructions
The CPU32 traps on unimplemented instructions and illegal effective
addressing modes, allowing the user to emulate instructions or to define
special-purpose functions. However, Motorola reserves the right to use all
currently unimplemented instruction operation codes for future M68000 core
enhancements.
See SECTION 4 INSTRUCTION SET for comprehensive information.
1.1.6.1 Table Lookup and Interpolation Instructions
To speed up real-time applications, a range of discrete data points is often
precalculated from a continuous control function, then stored
in memory. A full
range of data can require an inordinate amount of memory. The table
instructions make it possible to store a sample of the full range and recover
intermediate values quickly via linear interpolation. A round-to-nearest
algorithm can
be applied to the results.
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