Motorola NXP SYMPHONY DSP56007 Instruction manual

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
DSP56007
Order this document by:
DSP56007/D
©1996, 1997 MOTOROLA, INC.
SYMPHONY  AUDIO DSP FAMILY
24-BIT DIGITAL SIGNAL PROCESSORS
Motorola designed the Symphony  family of high-performance, programmable Digital Signal
Processors (DSPs) to support a variety of digital audio applications, including Dolby ProLogic,
ATRAC, and Lucasfilm Home THX processing. Software for these applications is licensed by
Motorola for integration into products like audio/video receivers, televisions, and automotive
sound systems with such user-developed features as digital equalization and sound field
processing. The DSP56007 is an MPU-style general purpose DSP, composed of an efficient 24-bit
Digital Signal Processor core, program and data memories, various peripherals optimized for
audio, and support circuitry. As illustrated in
Figure 1 , the DSP56000 core family compatible
DSP is fed by program memory, two independent data RAMs and two data ROMs, a Serial
Audio Interface (SAI), Serial Host Interface (SHI), External Memory Interface (EMI), dedicated
I/O lines, on-chip Phase Lock Loop (PLL), and On-Chip Emulation (OnCE
 ) port. The
DSP56007 has significantly more on-chip memory than the DSP56004.
ˇ
Figure 1 DSP56007 Block Diagram
Y Data
Memory*
X Data
Memory*
Program
Memory*
Program Control Unit
24-Bit
DSP56000
Core
OnCETM Port
PLL Clock
Gen.
4 9 5 29 16-Bit Bus
24-Bit Bus
Data ALU
24 ×24 + 56 →56-Bit MAC
Two 56-Bit Accumulators
Interrupt
Control
Program
Decode
Controller
Program
Address
Generator
4
IRQA, IRQB, NMI, RESET
43
Internal
Data
Bus
Switch
Address
Generation
Unit
Refer to Table 1 for memory configurations.
*
PAB
XAB
YAB
GDB
PDB
XDB
YDB
General
Purpose
Input/
Output
External
Memory
Interface
(EMI)
Serial
Audio
Interface
(SAI)
Serial
Host
Interface
(SHI)
AA0248
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ii DSP56007/D MOTOROLA
TABLE OF CONTENTS
SECTION 1 SIGNAL/CONNECTION DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . .1-1
SECTION 2 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1
SECTION 3 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-1
SECTION 4 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-1
SECTION 5 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5-1
FOR TECHNICAL ASSISTANCE:
Telephone: [phone]
Email: [email protected]
Internet: http://www.motorola-dsp.com
Data Sheet Conventions
T
his data sheet uses the following conventions:
OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is
active when low.)
“asserted” Means that a high true (active high) signal is high or that a low true (active low) signal
is low
“deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal
is high
Examples: Signal/Symbol Logic State Signal State Voltage
PIN True Asserted VIL/VOL
PIN False Deasserted VIH/VOH
PIN True Asserted VIH/VOH
PIN False Deasserted VIL/VOL
Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
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DSP56007
Features
MOTOROLA DSP56007/D iii
FEATURES
Digital Signal Processing Core
• Efficient, object code compatible with the 24-bit DSP56000 core family engine
• Up to 44 Million Instructions Per Second (MIPS)—22.7 ns instruction cycle at
88 MHz
• Highly parallel instruction set with unique DSP addressing modes
• Two 56-bit accumulators including extension byte
• Parallel 24
× 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
• Double precision 48
× 48-bit multiply with 96-bit result in 6 instruction cycles
• 56-bit addition/subtraction in 1 instruction cycle
• Fractional and integer arithmetic with support for multiprecision arithmetic
• Hardware support for block floating-point Fast Fourier Transforms (FFT)
• Hardware nested DO loops
• Zero-overhead fast interrupts (2 instruction cycles)
• Four 24-bit internal data buses and three 16-bit internal address buses for
simultaneous accesses to one program and two data memories
• Fabricated in high-density CMOS
Memory
• On-chip modified Harvard architecture, which permits simultaneous accesses
to program and two data memories
• Bootstrap loading from Serial Host Interface or External Memory Interface
Table 1 Memory Configuration (Word width is 24 bits)
Mode Program X Data Y Data Bootstrap
ROM
PE ROM RAM ROM RAM ROM RAM
0 6400 None 512 1024 512 2176 52
1 5120 1024 512 1024 512 1152 52
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iv DSP56007/D MOTOROLA
DSP56007
Features
Peripheral and Support Circuits
• Serial Audio Interface (SAI) includes two receivers and three transmitters,
master or slave capability, implementation of I
2
S, Sony, and Matsushita audio
protocols; and two sets of SAI interrupt vectors
• Serial Host Interface (SHI) features single master capability, 10-word receive
FIFO, and support for 8-, 16-, and 24-bit words
• External Memory Interface (EMI), implemented as a peripheral supporting:
– Page-mode DRAMs (one or two chips): 64 K
× 4, 256 K × 4,
and 4 M
× 4 bits
– SRAMs (one to four): 256 K
× 8 bits
– Data bus may be 4 or 8 bits wide
– Data words may be 8, 12, 16, 20, or 24 bits wide
• Four dedicated, independent, programmable General Purpose Input/Output
(GPIO) lines
• On-chip peripheral registers memory mapped in data memory space
• Three external interrupt request pins
• On-Chip Emulation (OnCE) port for unobtrusive, processor speed-
independent debugging
• Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer
for the core clock
• Power-saving Wait and Stop modes
• Fully static, HCMOS design for operating frequencies down to DC
• 80-pin plastic Quad Flat Pack surface-mount package; 14
× 14 × 2.20 mm
(2.15–2.45 mm range); 0.65 mm lead pitch
• Complete pinout compatibility between DSP56009, DSP56004,
DSP56004ROM, and DSP56007 for easy upgrades
• 5 V power supply
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DSP56007
Product Documentation
MOTOROLA DSP56007/D v
PRODUCT DOCUMENTATION
Table 2 lists the documents that provide a complete description of the DSP56007 and
are required to design properly with the part. Documentation is available from a local
Motorola distributor, a Motorola semiconductor sales office, a Motorola Literature
Distribution Center, or through the Motorola DSP home page on the Internet (the
source for the latest information).
Table 2 DSP56007 Documentation
Document Name Description of Content Order Number
DSP56000 Family
Manual DSP56000 core family architecture and the 24-bit core processor and instruction set DSP56KFAMUM/AD
DSP56007 User’s
Manual Memory, peripherals, and interfaces DSP56007UM/AD
DSP56007 Technical
Data Electrical and timing specifications, and pin and package descriptions DSP56007/D
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vi DSP56007/D MOTOROLA
DSP56007
Product Documentation
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MOTOROLA DSP56007/D 1-1
SECTION 1
SIGNAL/CONNECTION DESCRIPTIONS
SIGNAL GROUPINGS
The DSP56007 input and output signals are organized into the nine functional
groups, as shown in
Table 1-1 . The individual signals are illustrated in Figure 1-1 .
Table 1-1 DSP56007 Functional Group Signal Allocations
Functional Group Number of Signals Detailed Description
Power (V
CC
)9 Table 1-2
Ground (GND) 13 Table 1-3
Phase Lock Loop (PLL) 3 Table 1-4
External Memory Interface (EMI) 29 Table 1-5 and
Table 1-6
Interrupt and Mode Control 4 Table 1-7
Serial Host Interface (SHI) 5 Table 1-8
Serial Audio Interface (SAI) 9 Table 1-9 and
Table 1-10
General Purpose Input/Output (GPIO) 4 Table 1-11
On-Chip Emulation (OnCE) port 4 Table 1-12
Total 80
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1-2 DSP56007/D MOTOROLA
Signal/Connection Descriptions
Signal Groupings
Figure 1-1 DSP56007 SIgnals
MA0–MA14
MD0–MD7
MWR
MA17/MCS1/MRAS
MA16/MCS2/MCAS
GNDQ
VCCQ
RESET
MODA/IRQA
MODB/IRQB
MODC/NMI
SS/HA2
MISO/SDA
SCK/SCL
GNDS
VCCS
WSR
SCKR
SDI0
DSCK/OS1
DSI/OS0
DSO
DR
OnCE™
Port C
Port B
Port A
External Memory
Mode/Interrupt
80 signals
Serial Host
Rec0
SDO1
Tran1
WST
SCKT
SDO0
Tran0
Interface
MRD
MCS0
Serial Audio
Interface
Interface
MOSI/HA0
SDO2
Tran2
SDI1
Rec1
GPIO0–GPIO3
GPIO
HREQ
VCCP
GNDP
PCAP
PLL
PINIT
MA15/MCS3
EXTAL
GNDA
VCCA
GNDD
VCCD
Reset
AA0249G
Port
Power Inputs
Ground
Control
2
2
3
3
4
2
3
8
4
15
DSP56007
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Signal/Connection Descriptions
Power
MOTOROLA DSP56007/D 1-3
POWER
GROUND
Table 1-2 Power Inputs
Power Name Description
V
CCP
PLL Power —V
CCP
provides isolated power for the Phase Lock Loop (PLL). The
voltage should be well-regulated and the input should be provided with an
extremely low impedance path to the V
CC
power rail.
V
CCQ
Quiet Power —V
CCQ
provides isolated power for the internal processing logic. This
input must be tied externally to all other chip power inputs. The user must provide
adequate external decoupling capacitors.
V
CCA
Address Bus Power —V
CCA
provides isolated power for sections of the address bus
I/O drivers. This input must be tied externally to all other chip power inputs. The
user must provide adequate external decoupling capacitors.
V
CCD
Data Bus Power —VCCD provides isolated power for sections of the data bus I/O
drivers. This input must be tied externally to all other chip power inputs. The user
must provide adequate external decoupling capacitors.
VCCS Serial Interface Power—VCCS provides isolated power for the SHI and SAI. This
input must be tied externally to all other chip power inputs. The user must provide
adequate external decoupling capacitors.
Table 1-3 Grounds
Ground Name Description
GNDPPLL Ground—GNDPis ground dedicated for PLL use. The connection should be
provided with an extremely low-impedance path to ground. VCCP should be
bypassed to GNDPby a 0.47 µF capacitor located as close as possible to the chip
package.
GNDQQuiet Ground—GNDQprovides isolated ground for the internal processing logic.
This connection must be tied externally to all other chip ground connections. The
user must provide adequate external decoupling capacitors.
GNDAAddress Bus Ground—GNDAprovides isolated ground for sections of the address
bus I/O drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
GNDDData Bus Ground—GNDDprovides isolated ground for sections of the data bus I/O
drivers. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
GNDS Serial Interface Ground—GNDSprovides isolated ground for the SHI and SAI. This
connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
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1-4 DSP56007/D MOTOROLA
Signal/Connection Descriptions
Clock and PLL signals
CLOCK AND PLL SIGNALS
Note: While the PLL on this DSP is identical to the PLL described in the DSP56000
Family Manual
, two of the signals have not been implemented externally.
Specifically, there is no PLOCK signal or CKOUT signal available. Therefore,
the internal clock is not directly accessible and there is no external indication
that the PLL is locked. These signals were omitted to reduce the number of
pins and allow this DSP to be put in a smaller, less expensive package.
Table 1-4 Clock and PLL Signals
Signal
Name Signal Type
State
during
Reset Signal Description
EXTAL Input Input External Clock/Crystal—This input should be connected to an
external clock source. If the PLL is enabled, this signal is
internally connected to the on-chip PLL. The PLL can multiply
the frequency on the EXTAL pin to generate the internal DSP
clock. The PLL output is divided by two to produce a four-phase
instruction cycle clock, with the minimum instruction time being
two PLL output clock periods. If the PLL is disabled, EXTAL is
divided by two to produce the four-phase instruction cycle clock.
PCAP Input Input PLL Filter Capacitor—This input is used to connect a high-
quality (high “Q” factor) external capacitor needed for the PLL
filter. The capacitor should be as close as possible to the DSP with
heavy, short traces connecting one terminal of the capacitor to
PCAP and the other terminal to VCCP. The required capacitor
value is specified in Table 2-6 on page 2-6.
Note: When short lock time is critical, low dielectric absorption
capacitors such as polystyrene, polypropylene, or teflon are
recommended.
If the PLL is not used (i.e., it remains disabled at all times), there is
no need to connect a capacitor to the PCAP pin. It may remain
unconnected, or be tied to either Vcc or GND.
PINIT Input Input PLL Initialization (PINIT)—During the assertion of hardware
reset, the value on the PINIT line is written into the PEN bit of the
PCTL register. When set, the PEN bit enables the PLL by causing
it to derive the internal clocks from the PLL voltage controlled
oscillator output. When the bit is cleared, the PLL is disabled and
the DSP’s internal clocks are derived from the clock connected to
the EXTAL signal. After hardware RESET is deasserted, the
PINIT signal is ignored.
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