NEC VR4181 mPD30181 User manual

VR4181™
64-/32-Bit Microprocessor
Hardware


NEC Electronics Corporation 2000


MIPS Technologies, Inc. 1998
Printed in Japan
Document No. U14272EJ3V0UM00 (3rd edition)
Date Published November 2002 NS CP(K)
User’s Manual
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PD30181
查询UPD30181GM-66-8ED供应商

User’s Manual U14272EJ3V0UM
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[MEMO]

User’s Manual U14272EJ3V0UM 3
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimatelydegradethedeviceoperation. Stepsmustbetakentostopgenerationofstaticelectricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulatorsthateasilybuildstaticelectricity. Semiconductordevicesmustbestoredandtransported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wriststrap. Semiconductordevicesmustnotbetouchedwith barehands. Similarprecautionsneed
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
totheinputpins, it is possible that aninternalinputlevelmaybegenerated due to noise, etc., hence
causingmalfunction. CMOSdevicesbehave differentlythanBipolarorNMOSdevices. Inputlevels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
VR10000, VR12000, VR4000, VR4000 Series, VR4100, VR4100 Series, VR4110, VR4111, VR4121, VR4122,
VR4181, VR4300, VR4305, VR4310, VR4400, VR5000A, VR5432, and VRSeries are trademarks of NEC
Electronics Corporation.
MIPS is a registered trademark of MIPS Technologies, Inc. in the United States.
MBA is a trademark of Vadem Corporation.
Pentium, Intel, and StrataFlash are trademarks of Intel Corporation.
DEC VAX is a trademark of Digital Equipment Corporation.
PC/AT is a trademark of International Business Machines Corporation.

User’s Manual U14272EJ3V0UM
4
Exporting this product or equipment that includes this product may require a governmental license from the U.S.A. for some
countries because this product utilizes technologies limited by the export control regulations of the U.S.A.
The information in this document is current as of January, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
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"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
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(Note)
(1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
•
•
•
•
•
•
M8E 02.11-1

User’s Manual U14272EJ3V0UM 5
Regional Information
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: [phone]
800-366-9782
Fax: [phone]
800-729-9288
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: [phone]
Fax: [phone]
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]
NEC Electronics Shanghai, Ltd.
Shanghai, P.R. China
Tel: [phone]
Fax: [phone]
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: [phone]
Fax: [phone]
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: [phone]
Fax: [phone]
J02.11
NEC Electronics (Europe) GmbH
Duesseldorf,Germany
Tel: [phone]
Fax: [phone]
•Sucursal en España
Madrid, Spain
Tel: [phone]
Fax: [phone]
Vélizy-Villacoublay,France
Tel: [phone]
Fax: [phone]
•Succursale Française
•Filiale Italiana
Milano, Italy
Tel: [phone]
Fax: [phone]
•Branch The Netherlands
Eindhoven,TheNetherlands
Tel: [phone]
Fax: [phone]
•Tyskland Filial
Taeby, Sweden
Tel: [phone]
Fax: [phone]
•United Kingdom Branch
Milton Keynes, UK
Tel: [phone]
Fax: [phone]
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:

User’s Manual U14272EJ3V0UM
6
Major Revisions in This Edition (1/5)
Page Description
Throughout this
manual Separation of the following parts of the previous (the 2nd) edition
CHAPTER 3 MIPS III INSTRUCTION SET SUMMARY, CHAPTER 4 MIPS16 INSTRUCTION SET,
CHAPTER 5 VR4181 PIPELINE, CHAPTER 6 MEMORY MANAGEMENT SYSTEM (first half),
CHAPTER 7 EXCEPTION PROCESSING (second half), CHAPTER 9 CACHE MEMORY,
CHAPTER 10 CPU CORE INTERRUPTS, CHAPTER 27 MIPS III INSTRUCTION SET DETAILS,
CHAPTER 28 MIPS16 INSTRUCTION SET FORMAT
p. 30 Deletion of modem block in Figure 1-1. Internal Block Diagram
p. 34 Modification of description in 1.3.16 LCD interface
p. 35 Modification of Remark in 1.3.17 Wake-up events
pp. 38 to 42 Addition of 1.4.2 CPU instruction set overview and 1.4.3 Data formats and addressing
p. 43 Modification of description and deletion of figure in 1.4.4 CP0 registers
pp. 45, 46 Addition of 1.4.9 Power modes and 1.4.10 Code compatibility
p. 47 Addition of descriptions in 1.5 Clock Interface
pp. 48, 49 Addition of Figure 1-8. External Circuits of Clock Oscillator and Figure 1-9. Incorrect
Connection Circuits of Resonator
p. 52 Modification of Note in 2.2.1 System bus interface signals
p. 53 Modification of descriptions for SYSDIR and SYSEN# and addition of description in Note in 2.2.1
System bus interface signals
p. 58 Addition of description for IRDIN/RxD2 in 2.2.10 IrDA interface signals
p. 60 Addition and modification in 2.3 Pin Status in Specific Status
pp. 63 to 66 Addition of 2.4 Recommended Connection of Unused Pins and I/O Circuit Types and 2.5 Pin I/O
Circuits
pp. 67 to 90 Addition of CHAPTER 3 CP0 REGISTERS
p. 95 Modification of Table 4-6. DRAM Address Map
p. 97 Modification of description in 5.1.1 RTC reset
pp. 97 to 101, 104, 105 Addition of description in Note in Figure 5-1 through Figure 5-5, Figure 5-8, and Figure 5-9
p. 98 Modification in Figure 5-2. RSTSW Reset
p. 101 Modification of description in 5.1.5 HALTimer shutdown
p. 104 Addition of description in 5.3.1 Cold Reset
p. 105 Modification of description in 5.3.2 Soft Reset
pp. 106, 107 Addition of 5.4 Notes on Initialization
p. 108 Modification in Figure 6-1. VR4181 Internal Bus Structure
p. 109 Modification of description in 6.1.2 (3) LCD module (LCD Control Unit)
p. 111 Modification of description for bit 4 and addition of Caution and Remark in 6.2.1 BCUCNTREG1
(0x0A00 0000)
p. 113 Modification of descriptions for bits 14 to 12, bits 3 to 0, and Remark in 6.2.3 BCUSPEEDREG
(0x0A00 000C)
p. 114 Modification of Figure 6-2. ROM Read Cycle and Access Parameters
p. 117 Deletion of description for Div4 mode and addition of description in Remark in 6.2.6 (2) Peripheral
clock (TClock)

User’s Manual U14272EJ3V0UM 7
Major Revisions in This Edition (2/5)
Page Description
p. 119 Modification of description in 6.3.2 Connection to external ROM (x 16) devices
p. 122 Modification of Remark in 6.3.3 (4) 64 Mbit PageROM
p. 123 Modification of figure in 6.3.3 (5) 32 Mbit flash memory (when using IntelTM DD28F032)
pp. 125 to 128, 130 Modification of Figure 6-3 through Figure 6-8
p. 129 Addition of description in Table 6-2. VR4181 EDO DRAM Capacity
p. 134 Addition of Caution and modification in Remark in 6.5.2 MEMCFG_REG (0x0A00 0304)
p. 135 Modification of description for bits 6 to 4 in 6.5.3 MODE_REG (0x0A00 0308)
p. 136 Modification of Note in 6.5.4 SDTIMINGREG (0x0A00 030C)
p. 137 Addition of description in 6.6 ISA Bridge
p. 138 Addition of description in 6.7.1 ISABRGCTL (0x0B00 02C0)
p. 140 Modification of description for bits 10 and 9 and addition of description in 6.7.3 XISACTL (0x0B00
02C4)
p. 149 Modification of description for bits 3 and 2 in 7.2.6 AIUDMAMSKREG (0x0A00 0046)
p. 150 Modification of values at reset in 7.2.7 MICRCLENREG (0x0A00 0658) and 7.2.8 SPKRCLENREG
(0x0A00 065A)
p. 151 Addition of description for bit 8 in 7.2.9 MICDMACFGREG (0x0A00 065E)
p. 152 Addition of description for bit 0 in 7.2.10 SPKDMACFGREG (0x0A00 0660)
p. 153 Addition of description for bits 5 and 4 in 7.2.11 DMAITRQREG (0x0A00 0662)
p. 156 Modification of description and addition of Caution in 8.1 Overview
p. 157 Addition of Caution in Figure 8-1. SCK and SI/SO Relationship
pp. 157, 158 Addition and modification of descriptions in 8.2.2 SCK phase and CSI transfer timing
p. 159 Modification of description in 8.2.3 (1) Burst mode
pp. 161, 162 Addition of Remarks and description in 8.3.1 CSIMODE (0x0B00 0900)
p. 171 Addition of description in 9.1 Overview
p. 173 Modification of description in Table 9-1. ICU Registers
p. 184 Modification of address and description for bits 2 and 1, and addition of description in 9.2.9
KIUINTREG (0x0B00 0086)
p. 186 Modification of R/W and addition of description in 9.2.11 MAIUINTREG (0x0B00 0090)
p. 189 Modification of description in Figure 10-1. Transition of VR4181 Power Mode
pp. 190, 191 Addition and modification of descriptions in 10.2.1 Power mode and state transition
p. 191 Modification of description in Table 10-2. Operations During Reset
p. 192 Modification of location of 10.3.3 Deadman’s Switch reset
p. 192 Modification of Figure 10-2. EDO DRAM Signals on RSTSW Reset (SDRAM Bit = 0)
p. 192 Modification of description in 10.3.4 (2) Preserving SDRAM data
p. 193 Modification of description in Table 10-3. Operations During Shutdown
p. 194 Modification of description of Caution in 10.5 Power-on Control
p. 196 Modification of signal name in 10.5.2 Activation via CompactFlash interrupt request
p. 197 Modification of description in 10.5.3 Activation via GPIO activation interrupt request

User’s Manual U14272EJ3V0UM
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Major Revisions in This Edition (3/5)
Page Description
p. 198 Modification of description of Cautions in 10.5.4 Activation via DCD interrupt request
pp. 201 to 204 Modification of descriptions in 10.6.1 through 10.6.4
pp. 205 to 207 Addition of 10.6.5 through 10.6.8
p. 209 Modification of description for bit 6 in 10.7.1 PMUINTREG (0x0B00 00A0)
p. 211 Modification of value at reset for bit 7 in 10.7.2 PMUCNTREG (0x0B00 00A2)
p. 214 Modification of description for bit 2 to 0 in 10.7.4 PMUDIVREG (0x0B00 00AC)
p. 215 Modification of description for bit 4 in 10.7.5 DRAMHIBCTL (0x0B00 00B2)
p. 220 Modification of value at reset for bit 15 in 11.2.2 (3) ECMPHREG (0x0B00 00CC)
p. 238 Modification and addition of descriptions in 13.1.3 General-purpose registers
p. 242 Modification of description in 13.2.5 16-bit bus cycles
p. 254 Modification of R/W for bits 15 to 8 in 13.3.5 GPDATHREG (0x0B00 0308)
p. 267 Modification of description in 13.3.15 KEYEN (0x0B00 031C)
p. 270 Modification of description for bit 15 in 13.3.19 PCS1STRA (0x0B00 0326)
p. 273 Modification of description for bit 7 in 13.3.23 LCDGPMODE (0x0B00 032E)
p. 275 Addition of Caution in 14.1 General
p. 283 Modification of location of Note in Table 14-3. PIUCNTREG Bit Manipulation and States
p. 286 Modification of description for bits 5 to 0 in 14.3.4 PIUSTBLREG (0x0B00 0128)
p. 289 Addition of description in 14.3.6 PIUASCNREG (0x0B00 0130)
p. 290 Modification of description in Table 14-4. PIUASCNREG Bit Manipulation and States
p. 291 Addition of description in 14.3.7 PIUAMSKREG (0x0B00 0132)
p. 292 Modification of values at reset for bits 2 to 0 in 14.3.8 PIUCIVLREG (0x0B00 013E)
p. 295 Modification of description in Table 14-7. Mask Clear During Scan Sequencer Operation
p. 298 Addition of Note in Figure 14-6. Touch/Release Detection Timing
p. 298 Modification of Figure 14-7. A/D Port Scan Timing
p. 301 Modification of description and addition of Caution in 15.1 General
pp. 303, 304 Modification of addresses in 15.2.1 SDMADATREG (0x0B00 0160) and 15.2.2 MDMADATREG
(0x0B00 0162)
p. 308 Modification of values at reset for bits 11, 10 and 5 and addition of Caution in 15.2.6 SCNVC_END
(0x0B00 016E)
p. 314 Modification of values at reset for bits 11, 10 and 5 and addition of Caution in 15.2.12 MCNVC_END
(0x0B00 017E)
pp. 315, 316 Addition of descriptions in 15.3.1 Output (speaker) and 15.3.2 Input (microphone)
p. 320 Modification of description in 16.2.6 Interrupts and status reporting
p. 321 Modification of description in Table 16-3. KIU Interrupt Registers
p. 324 Modification of description for bits 1 and 0 in 16.3.3 KIUSCANS (0x0B00 0192)
p. 325 Modification of descriptions for bits 14 to 10 and bits 4 to 0 in 16.3.4 KIUWKS (0x0B00 0194)
p. 327 Modification and addition of descriptions for bits 2 to 0 in 16.3.6 KIUINT (0x0B00 0198)
p. 328 Modification of signal name in 17.1 General

User’s Manual U14272EJ3V0UM 9
Major Revisions in This Edition (4/5)
Page Description
p. 333 Modification of signal names in Figure 17-1. CompactFlash Interrupt Logic
p. 333 Modification of description for bit 0 in 17.3.3 CFG_REG_1 (0x0B00 08FE)
p. 336 Addition of Caution for bit 4 in 17.4.3 PWRRSETDRV (Index: 0x02)
p. 337 Modification of description for bit 7 in 17.4.4 ITGENCREG (Index: 0x03)
p. 338 Modification of description and addition of Caution for bit 0 in 17.4.5 CDSTCHGREG (Index: 0x04)
p. 341 Modification of descriptions for bits 7, 4, 3, and 0 in 17.4.8 IOCTRL_REG (Index: 0x07)
p. 344 Modification of description for bit 6 in 17.4.14 MEMWIDn_REG (Index: 0x11, 0x19, 0x21, 0x29,
0x31)
p. 345 Modification of description for bits 7 and 6 and addition of description in 17.4.16 MEMSELn_REG
(Index: 0x13, 0x1B, 0x23, 0x2B, 0x33)
p. 346 Addition of description in 17.4.17 MEMOFFLnREG (Index: 0x14, 0x1C, 0x24, 0x2C, 0x34)
p. 346 Modification of Remark for bits 5 to 0 in 17.4.18 MEMOFFHnREG (Index: 0x15, 0x1D, 0x25, 0x2D,
0x35)
p. 348 Modification of description for bit 2 in 17.4.20 GLOCTRLREG (Index: 0x1E)
p. 349 Modification of description for bits 1 and 0 and addition of description in 17.4.22 VOLTSELREG
(Index: 0x2F)
pp. 350, 351 Addition of 17.5 Memory Mapping of CompactFlash Card
p. 352 Addition of 17.6 Controlling Bus When CompactFlash Card Is Used
p. 356 Addition of function for bit 2 in 18.2.3 LEDCNTREG (0x0B00 0248)
p. 357 Modification of description in 18.2.4 LEDASTCREG (0x0B00 024A)
p. 359 Modification of figure in 18.3 Operation Flow
p. 360 Addition of Caution in 19.1 General
p. 361 Modification of description in Table 19-1. SIU1 Registers
pp. 362, 364, 376 Modification of values at reset in 19.3.1 through 19.3.3, 19.3.5, and 19.3.12
p. 365 Addition of description in Table 19-2. Correspondence between Baud Rates and Divisors
p. 368 Modification of descriptions for bits 2 to 0 in 19.3.7 SIUFC_1 (0x0C00 0012: Write)
p. 373 Modification of R/W and addition of description in 19.3.10 SIULS_1 (0x0C00 0015)
p. 375 Modification of descriptions for bits 7 to 4 in 19.3.11 SIUMS_1 (0x0C00 0016)
p. 377 Modification of R/W for bit 1 in 19.3.14 SIUACTMSK_1 (0x0C00 001C)
p. 379 Addition of description and Caution in 20.1 General
p. 380 Modification of description in Table 20-1. SIU2 Registers
pp. 381, 383, 395 Modification of values at reset in 20.3.1 through 20.3.3, 20.3.5, and 20.3.12
p. 384 Addition of description in Table 20-2. Correspondence between Baud Rates and Divisors
p. 387 Modification of descriptions for bits 2 to 0 in 20.3.7 SIUFC_2 (0x0C00 0002: Write)
p. 392 Modification of R/W and addition of description in 20.3.10 SIULS_2 (0x0C00 0005)
p. 394 Modification of descriptions for bits 7 to 4 in 20.3.11 SIUMS_2 (0x0C00 0006)
p. 395 Addition of description in 20.3.13 SIUIRSEL_2 (0x0C00 008)
p. 397 Modification of R/W for bit 1 in 20.3.16 SIUACTMSK_2 (0x0C00 000C)

User’s Manual U14272EJ3V0UM
10
Major Revisions in This Edition (5/5)
Page Description
p. 399 Modification of description in 21.1.1 LCD interface
p. 401 Modification of bus width in Figure 21-1. LCD Controller Block Diagram
p. 406 Modification of description in 21.3.4 Frame buffer memory and FIFO
p. 420 Addition of Remark in 21.4.11 LCDCFGREG0 (0x0A00 0414)
p. 428 Addition of Remark in 21.4.22 CPINDCTREG (0x0A00 047E)
p. 429 Addition of Caution in 21.4.23 CPALDATREG (0x0A00 0480)
p. 433 Addition of Caution in Table 23-1. Coprocessor 0 Hazards
pp. 436 to 438 Addition of APPENDIX A RESTRICTIONS ON VR4181
pp. 439 to 444 Addition of APPENDIX B INDEX
The mark shows major revised points.

User’s Manual U14272EJ3V0UM 11
PREFACE
Readers This manual targets users who intend to understand the functions of the VR4181 and
to design application systems using this microprocessor.
Purpose This manual introduces the hardware functions of the VR4181 to users, following the
organization described below.
Organization Two manuals are available for the VR4181: Hardware User’s Manual (this manual)
and Architecture User’s Manual common to the VR4100 SeriesTM.
Hardware
User’s Manual Architecture User’s Manual
• Pin functions
• Physical address space
• Function of Coprocessor 0
• Initialization interface
• Peripheral units
• Pipeline operation
• Cache organization and memory
management system
• Exception processing
• Interrupts
• Instruction set
How to read this manual It is assumed that the reader of this manual has general knowledge in the fields of
electric engineering, logic circuits, microcomputers, and SDRAMs.
To learn about the overall functions of the VR4181,
→Read this manual in sequential order.
To learn about instruction sets,
→Read VR4100 Series Architecture User’s Manual that is separately
available.
To learn about electrical specifications,
→Refer to Data Sheet that is separately available.
Conventions Data significance: Higher on left and lower on right
Active low: XXX# (trailing # after pin and signal names)
Note: Description of item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numeric representation: binary/decimal ... XXXX
hexadecimal ... 0xXXXX
Prefixes representing an exponent of 2 (for address space or memory capacity):
K (kilo) … 210 = 1024
M (mega) … 220 = 10242
G (giga) … 230 = 10243
T (tera) … 240 = 10244
P (peta) … 250 = 10245
E (exa) … 260 = 10246

User’s Manual U14272EJ3V0UM
12
Related Documents When using this manual, also refer to the following documents.
Document name Document number
VR4181 Hardware User’s Manual This manual
µ
PD30181 (VR4181) Data Sheet U14273E
VR4100 Series Architecture User’s Manual U15509E
VRSeries TM Programming Guide Application Note U10710E
The related documents indicated here may include preliminary version. However,
preliminary versions are not marked as such.

User’s Manual U14272EJ3V0UM 13
CONTENTS
CHAPTER 1 INTRODUCTION ............................................................................................................. 29
1.1 Features .................................................................................................................................... 29
1.2 Ordering Information ............................................................................................................... 30
1.3 VR4181 Key Features ............................................................................................................... 30
1.3.1 CPU core ..................................................................................................................................... 31
1.3.2 Bus interface ............................................................................................................................... 31
1.3.3 Memory interface ......................................................................................................................... 32
1.3.4 DMA controller (DCU) .................................................................................................................. 32
1.3.5 Interrupt controller (ICU) .............................................................................................................. 32
1.3.6 Real-time clock ............................................................................................................................ 32
1.3.7 Audio output (D/A converter) ....................................................................................................... 32
1.3.8 Touch panel interface and audio input (A/D converter) ............................................................... 32
1.3.9 CompactFlash interface (ECU) ................................................................................................... 32
1.3.10 Serial interface channel 1 (SIU1) .............................................................................................. 32
1.3.11 Serial interface channel 2 (SIU2) .............................................................................................. 32
1.3.12 Clocked serial interface (CSI) .................................................................................................... 33
1.3.13 Keyboard interface (KIU) ........................................................................................................... 33
1.3.14 General-purpose I/O .................................................................................................................. 33
1.3.15 Programmable chip selects ....................................................................................................... 34
1.3.16 LCD interface ............................................................................................................................ 34
1.3.17 Wake-up events ........................................................................................................................ 35
1.4 VR4110 CPU Core ..................................................................................................................... 35
1.4.1 CPU registers .............................................................................................................................. 37
1.4.2 CPU instruction set overview ...................................................................................................... 38
1.4.3 Data formats and addressing ...................................................................................................... 40
1.4.4 CP0 registers ............................................................................................................................... 43
1.4.5 Floating-point unit (FPU) ............................................................................................................. 44
1.4.6 Memory management unit ........................................................................................................... 44
1.4.7 Cache .......................................................................................................................................... 44
1.4.8 Instruction pipeline ...................................................................................................................... 44
1.4.9 Power modes .............................................................................................................................. 45
1.4.10 Code compatibility ..................................................................................................................... 46
1.5 Clock Interface ......................................................................................................................... 47
CHAPTER 2 PIN FUNCTIONS ............................................................................................................ 50
2.1 Pin Configuration ..................................................................................................................... 50
2.2 Pin Function Description ........................................................................................................ 52
2.2.1 System bus interface signals ....................................................................................................... 52
2.2.2 LCD interface signals .................................................................................................................. 54
2.2.3 Initialization interface signals ...................................................................................................... 55
2.2.4 Battery monitor interface signals ................................................................................................. 55
2.2.5 Clock interface signals ................................................................................................................ 55
2.2.6 Touch panel interface and audio interface signals ...................................................................... 56

User’s Manual U14272EJ3V0UM
14
2.2.7 LED interface signals ................................................................................................................... 56
2.2.8 CompactFlash interface and keyboard interface signals ............................................................. 56
2.2.9 Serial interface channel 1 signals ................................................................................................ 57
2.2.10 IrDA interface signals ................................................................................................................ 58
2.2.11 General-purpose I/O signals ...................................................................................................... 58
2.2.12 Dedicated VDD/GND signals ...................................................................................................... 59
2.3 Pin Status in Specific Status .................................................................................................. 60
2.4 Recommended Connection of Unused Pins and I/O Circuit Types .................................... 63
2.5 Pin I/O Circuits ......................................................................................................................... 66
CHAPTER 3 CP0 REGISTERS ............................................................................................................ 67
3.1 Coprocessor 0 (CP0) ............................................................................................................... 67
3.2 Details of CP0 Registers ......................................................................................................... 69
3.2.1 Index register (0) ......................................................................................................................... 69
3.2.2 Random register (1) ..................................................................................................................... 69
3.2.3 EntryLo0 (2) and EntryLo1 (3) registers ...................................................................................... 70
3.2.4 Context register (4) ...................................................................................................................... 71
3.2.5 PageMask register (5) ................................................................................................................. 72
3.2.6 Wired register (6) ......................................................................................................................... 73
3.2.7 BadVAddr register (8) .................................................................................................................. 74
3.2.8 Count register (9) ......................................................................................................................... 74
3.2.9 EntryHi register (10) .................................................................................................................... 75
3.2.10 Compare register (11) ............................................................................................................... 76
3.2.11 Status register (12) .................................................................................................................... 76
3.2.12 Cause register (13) .................................................................................................................... 79
3.2.13 Exception Program Counter (EPC) register (14) ....................................................................... 81
3.2.14 Processor Revision Identifier (PRId) register (15) .....................................................................82
3.2.15 Config register (16) .................................................................................................................... 83
3.2.16 Load Linked Address (LLAddr) register (17) .............................................................................84
3.2.17 WatchLo (18) and WatchHi (19) registers ................................................................................. 85
3.2.18 XContext register (20) ............................................................................................................... 86
3.2.19 Parity Error register (26) ............................................................................................................ 87
3.2.20 Cache Error register (27) ........................................................................................................... 87
3.2.21 TagLo (28) and TagHi (29) registers ......................................................................................... 88
3.2.22 ErrorEPC register (30) ............................................................................................................... 89
CHAPTER 4 MEMORY MANAGEMENT SYSTEM ............................................................................ 91
4.1 Overview ................................................................................................................................... 91
4.2 Physical Address Space ......................................................................................................... 92
4.2.1 ROM space .................................................................................................................................. 93
4.2.2 External system bus space .......................................................................................................... 93
4.2.3 Internal I/O space ........................................................................................................................ 94
4.2.4 DRAM space ............................................................................................................................... 95

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CHAPTER 5 INITIALIZATION INTERFACE ....................................................................................... 96
5.1 Reset Function ......................................................................................................................... 96
5.1.1 RTC reset .................................................................................................................................... 97
5.1.2 RSTSW reset .............................................................................................................................. 98
5.1.3 Deadman’s Switch reset .............................................................................................................. 99
5.1.4 Software shutdown ...................................................................................................................... 100
5.1.5 HALTimer shutdown .................................................................................................................... 101
5.2 Power-on Sequence ................................................................................................................ 102
5.3 Reset of CPU Core ................................................................................................................... 104
5.3.1 Cold Reset ................................................................................................................................... 104
5.3.2 Soft Reset .................................................................................................................................... 105
5.4 Notes on Initialization ............................................................................................................. 106
5.4.1 CPU core ..................................................................................................................................... 106
5.4.2 Internal peripheral units ............................................................................................................... 106
5.4.3 Returning from power mode ........................................................................................................ 107
CHAPTER 6 BUS CONTROL .............................................................................................................. 108
6.1 MBA Host Bridge ..................................................................................................................... 108
6.1.1 MBA Host Bridge ROM and register address space ................................................................... 109
6.1.2 MBA modules address space ...................................................................................................... 109
6.2 Bus Control Registers ............................................................................................................. 110
6.2.1 BCUCNTREG1 (0x0A00 0000) ................................................................................................... 111
6.2.2 CMUCLKMSK (0x0A00 0004) ..................................................................................................... 112
6.2.3 BCUSPEEDREG (0x0A00 000C) ................................................................................................ 113
6.2.4 BCURFCNTREG (0x0A00 0010) ................................................................................................ 115
6.2.5 REVIDREG (0x0A00 0014) ......................................................................................................... 116
6.2.6 CLKSPEEDREG (0x0A00 0018) ................................................................................................. 117
6.3 ROM Interface .......................................................................................................................... 118
6.3.1 External ROM devices memory mapping .................................................................................... 118
6.3.2 Connection to external ROM (x 16) devices ................................................................................ 119
6.3.3 Example of ROM connection ....................................................................................................... 120
6.3.4 External ROM cycles ................................................................................................................... 125
6.4 DRAM Interface ........................................................................................................................ 128
6.4.1 EDO DRAM configuration ............................................................................................................ 128
6.4.2 Mixed memory mode (EDO DRAM only) ..................................................................................... 129
6.4.3 EDO DRAM timing parameters ................................................................................................... 129
6.4.4 SDRAM configuration .................................................................................................................. 130
6.5 Memory Controller Register Set ............................................................................................. 131
6.5.1 EDOMCYTREG (0x0A00 0300) .................................................................................................. 131
6.5.2 MEMCFG_REG (0x0A00 0304) .................................................................................................. 133
6.5.3 MODE_REG (0x0A00 0308) ....................................................................................................... 135
6.5.4 SDTIMINGREG (0x0A00 030C) .................................................................................................. 136
6.6 ISA Bridge ................................................................................................................................ 137

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6.7 ISA Bridge Register Set ........................................................................................................... 137
6.7.1 ISABRGCTL (0x0B00 02C0) ....................................................................................................... 138
6.7.2 ISABRGSTS (0x0B00 02C2) ....................................................................................................... 139
6.7.3 XISACTL (0x0B00 02C4) ............................................................................................................. 140
CHAPTER 7 DMA CONTROL UNIT (DCU) ....................................................................................... 142
7.1 General ...................................................................................................................................... 142
7.2 DCU Registers ......................................................................................................................... 144
7.2.1 Microphone destination 1 address registers ................................................................................ 145
7.2.2 Microphone destination 2 address registers ................................................................................ 146
7.2.3 Speaker source 1 address registers ............................................................................................ 147
7.2.4 Speaker source 2 address registers ............................................................................................ 148
7.2.5 DMARSTREG (0x0A00 0040) ..................................................................................................... 149
7.2.6 AIUDMAMSKREG (0x0A00 0046) ............................................................................................... 149
7.2.7 MICRCLENREG (0x0A00 0658) .................................................................................................. 150
7.2.8 SPKRCLENREG (0x0A00 065A) ................................................................................................. 150
7.2.9 MICDMACFGREG (0x0A00 065E) .............................................................................................. 151
7.2.10 SPKDMACFGREG (0x0A00 0660) ............................................................................................ 152
7.2.11 DMAITRQREG (0x0A00 0662) .................................................................................................. 153
7.2.12 DMACTLREG (0x0A00 0664) .................................................................................................... 154
7.2.13 DMAITMKREG (0x0A00 0666) .................................................................................................. 155
CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI) ............................................................. 156
8.1 Overview ................................................................................................................................... 156
8.2 Operation of CSI ....................................................................................................................... 156
8.2.1 Transmit/receive operations ........................................................................................................ 156
8.2.2 SCK phase and CSI transfer timing ............................................................................................. 157
8.2.3 CSI transfer types ........................................................................................................................ 159
8.2.4 Transmit and receive FIFOs ........................................................................................................ 160
8.3 CSI Registers ............................................................................................................................ 160
8.3.1 CSIMODE (0x0B00 0900) ........................................................................................................... 161
8.3.2 CSIRXDATA (0x0B00 0902) ........................................................................................................ 163
8.3.3 CSITXDATA (0x0B00 0904) ........................................................................................................ 163
8.3.4 CSILSTAT (0x0B00 0906) ........................................................................................................... 164
8.3.5 CSIINTMSK (0x0B00 0908) ......................................................................................................... 166
8.3.6 CSIINTSTAT (0x0B00 090A) ....................................................................................................... 167
8.3.7 CSITXBLEN (0x0B00 090C) ........................................................................................................ 169
8.3.8 CSIRXBLEN (0x0B00 090E) ....................................................................................................... 170
CHAPTER 9 INTERRUPT CONTROL UNIT (ICU) ............................................................................ 171
9.1 Overview ................................................................................................................................... 171
9.2 Register Set .............................................................................................................................. 173
9.2.1 SYSINT1REG (0x0A00 0080) ..................................................................................................... 174
9.2.2 MSYSINT1REG (0x0A00 008C) .................................................................................................. 176
9.2.3 NMIREG (0x0A00 0098) .............................................................................................................. 178

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9.2.4 SOFTINTREG (0x0A00 009A) .................................................................................................... 179
9.2.5 SYSINT2REG (0x0A00 0200) ..................................................................................................... 180
9.2.6 MSYSINT2REG (0x0A00 0206) .................................................................................................. 181
9.2.7 PIUINTREG (0x0B00 0082) ........................................................................................................ 182
9.2.8 AIUINTREG (0x0B00 0084) ........................................................................................................ 183
9.2.9 KIUINTREG (0x0B00 0086) ........................................................................................................ 184
9.2.10 MPIUINTREG (0x0B00 008E) ................................................................................................... 185
9.2.11 MAIUINTREG (0x0B00 0090) ................................................................................................... 186
9.2.12 MKIUINTREG (0x0B00 0092) ................................................................................................... 187
CHAPTER 10 POWER MANAGEMENT UNIT (PMU) ...................................................................... 188
10.1 General ................................................................................................................................... 188
10.2 VR4181 Power Mode .............................................................................................................. 188
10.2.1 Power mode and state transition ............................................................................................... 188
10.3 Reset Control ......................................................................................................................... 191
10.3.1 RTC reset .................................................................................................................................. 191
10.3.2 RSTSW reset ............................................................................................................................ 192
10.3.3 Deadman’s Switch reset ............................................................................................................ 192
10.3.4 Preserving DRAM data on RSTSW reset .................................................................................. 192
10.4 Shutdown Control ................................................................................................................. 193
10.4.1 HALTimer shutdown .................................................................................................................. 193
10.4.2 Software shutdown .................................................................................................................... 193
10.4.3 BATTINH shutdown ................................................................................................................... 193
10.5 Power-on Control ................................................................................................................... 194
10.5.1 Activation via Power Switch interrupt request ........................................................................... 195
10.5.2 Activation via CompactFlash interrupt request .......................................................................... 196
10.5.3 Activation via GPIO activation interrupt request ........................................................................ 197
10.5.4 Activation via DCD interrupt request ......................................................................................... 198
10.5.5 Activation via ElapsedTime (RTC alarm) interrupt request ....................................................... 200
10.6 DRAM Interface Control ........................................................................................................ 201
10.6.1 Entering Hibernate mode (EDO DRAM) .................................................................................... 201
10.6.2 Entering Hibernate mode (SDRAM) .......................................................................................... 202
10.6.3 Exiting Hibernate mode (EDO DRAM) ...................................................................................... 203
10.6.4 Exiting Hibernate mode (SDRAM) ............................................................................................. 204
10.6.5 Entering Suspend mode (EDO DRAM) ..................................................................................... 205
10.6.6 Entering Suspend mode (SDRAM) ............................................................................................ 206
10.6.7 Exiting Suspend mode (EDO DRAM) ........................................................................................ 207
10.6.8 Exiting Suspend mode (SDRAM) .............................................................................................. 207
10.7 Register Set ............................................................................................................................ 208
10.7.1 PMUINTREG (0x0B00 00A0) .................................................................................................... 209
10.7.2 PMUCNTREG (0x0B00 00A2) .................................................................................................. 211
10.7.3 PMUWAITREG (0x0B00 00A8) ................................................................................................. 213
10.7.4 PMUDIVREG (0x0B00 00AC) ................................................................................................... 214
10.7.5 DRAMHIBCTL (0x0B00 00B2) .................................................................................................. 215

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CHAPTER 11 REALTIME CLOCK UNIT (RTC) ................................................................................ 216
11.1 General .................................................................................................................................... 216
11.2 Register Set ............................................................................................................................ 216
11.2.1 ElapsedTime registers ............................................................................................................... 217
11.2.2 ElapsedTime compare registers ................................................................................................ 219
11.2.3 RTCLong1 registers .................................................................................................................. 221
11.2.4 RTCLong1 count registers ......................................................................................................... 223
11.2.5 RTCLong2 registers .................................................................................................................. 225
11.2.6 RTCLong2 count registers ......................................................................................................... 227
11.2.7 RTC interrupt register ................................................................................................................ 229
CHAPTER 12 DEADMAN’S SWITCH UNIT (DSU) ........................................................................... 230
12.1 General .................................................................................................................................... 230
12.2 Register Set ............................................................................................................................ 230
12.2.1 DSUCNTREG (0x0B00 00E0) ................................................................................................... 231
12.2.2 DSUSETREG (0x0B00 00E2) ................................................................................................... 232
12.2.3 DSUCLRREG (0x0B00 00E4) ................................................................................................... 233
12.2.4 DSUTIMREG (0x0B00 00E6) .................................................................................................... 234
12.3 Register Setting Flow ............................................................................................................ 235
CHAPTER 13 GENERAL PURPOSE I/O UNIT (GIU) ...................................................................... 236
13.1 Overview ................................................................................................................................. 236
13.1.1 GPIO pins and alternate functions ............................................................................................. 236
13.1.2 I/O direction control ................................................................................................................... 238
13.1.3 General-purpose registers ......................................................................................................... 238
13.2 Alternate Functions Overview .............................................................................................. 238
13.2.1 Clocked serial interface (CSI) .................................................................................................... 238
13.2.2 Serial interface channels 1 and 2 .............................................................................................. 239
13.2.3 LCD interface ............................................................................................................................. 241
13.2.4 Programmable chip selects ....................................................................................................... 242
13.2.5 16-bit bus cycles ........................................................................................................................ 242
13.2.6 General purpose input/output .................................................................................................... 242
13.2.7 Interrupt requests and wake-up events ..................................................................................... 243
13.3 Register Set ............................................................................................................................ 244
13.3.1 GPMD0REG (0x0B00 0300) ...................................................................................................... 246
13.3.2 GPMD1REG (0x0B00 0302) ...................................................................................................... 248
13.3.3 GPMD2REG (0x0B00 0304) ...................................................................................................... 250
13.3.4 GPMD3REG (0x0B00 0306) ...................................................................................................... 252
13.3.5 GPDATHREG (0x0B00 0308) ................................................................................................... 254
13.3.6 GPDATLREG (0x0B00 030A) .................................................................................................... 255
13.3.7 GPINTEN (0x0B00 030C) .......................................................................................................... 256
13.3.8 GPINTMSK (0x0B00 030E) ....................................................................................................... 257
13.3.9 GPINTTYPH (0x0B00 0310) ...................................................................................................... 258
13.3.10 GPINTTYPL (0x0B00 0312) .................................................................................................... 260
13.3.11 GPINTSTAT (0x0B00 0314) .................................................................................................... 262

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13.3.12 GPHIBSTH (0x0B00 0316) ...................................................................................................... 263
13.3.13 GPHIBSTL (0x0B00 0318) ...................................................................................................... 264
13.3.14 GPSICTL (0x0B00 031A) ........................................................................................................ 265
13.3.15 KEYEN (0x0B00 031C) ........................................................................................................... 267
13.3.16 PCS0STRA (0x0B00 0320) ..................................................................................................... 268
13.3.17 PCS0STPA (0x0B00 0322) ..................................................................................................... 268
13.3.18 PCS0HIA (0x0B00 0324) ........................................................................................................ 269
13.3.19 PCS1STRA (0x0B00 0326) ..................................................................................................... 270
13.3.20 PCS1STPA (0x0B00 0328) ..................................................................................................... 270
13.3.21 PCS1HIA (0x0B00 032A) ........................................................................................................ 271
13.3.22 PCSMODE (0x0B00 032C) ..................................................................................................... 272
13.3.23 LCDGPMODE (0x0B00 032E) ................................................................................................ 273
13.3.24 MISCREGn (0x0B00 0330 to 0x0B00 034E) ........................................................................... 274
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU) ................................................................. 275
14.1 General ................................................................................................................................... 275
14.1.1 Block diagrams .......................................................................................................................... 276
14.2 Scan Sequencer State Transition ......................................................................................... 278
14.3 Register Set ............................................................................................................................ 280
14.3.1 PIUCNTREG (0x0B00 0122) ..................................................................................................... 281
14.3.2 PIUINTREG (0x0B00 0124) ...................................................................................................... 284
14.3.3 PIUSIVLREG (0x0B00 0126) .................................................................................................... 285
14.3.4 PIUSTBLREG (0x0B00 0128) ................................................................................................... 286
14.3.5 PIUCMDREG (0x0B00 012A) .................................................................................................... 287
14.3.6 PIUASCNREG (0x0B00 0130) .................................................................................................. 289
14.3.7 PIUAMSKREG (0x0B00 0132) .................................................................................................. 291
14.3.8 PIUCIVLREG (0x0B00 013E) .................................................................................................... 292
14.3.9 PIUPBnmREG (0x0B00 02A0 to 0x0B00 02AE, 0x0B00 02BC to 0x0B00 02BE) .................... 293
14.3.10 PIUABnREG (0x0B00 02B0 to 0x0B00 02B6) ........................................................................ 294
14.4 State Transition Flow ............................................................................................................ 295
14.5 Relationships among TPX, TPY, ADIN, and AUDIOIN Pins and States ............................ 297
14.6 Timing ..................................................................................................................................... 298
14.6.1 Touch/release detection timing ................................................................................................. 298
14.6.2 A/D port scan timing .................................................................................................................. 298
14.7 Data Loss Conditions ............................................................................................................ 299
CHAPTER 15 AUDIO INTERFACE UNIT (AIU) ................................................................................ 301
15.1 General ................................................................................................................................... 301
15.2 Register Set ............................................................................................................................ 302
15.2.1 SDMADATREG (0x0B00 0160) ................................................................................................. 303
15.2.2 MDMADATREG (0x0B00 0162) ................................................................................................ 304
15.2.3 DAVREF_SETUP (0x0B00 0164) ............................................................................................. 305
15.2.4 SODATREG (0x0B00 0166) ...................................................................................................... 306
15.2.5 SCNTREG (0x0B00 0168) ........................................................................................................ 307
15.2.6 SCNVC_END (0x0B00 016E) ................................................................................................... 308
15.2.7 MIDATREG (0x0B00 0170) ....................................................................................................... 309

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15.2.8 MCNTREG (0x0B00 0172) ........................................................................................................ 310
15.2.9 DVALIDREG (0x0B00 0178) ..................................................................................................... 311
15.2.10 SEQREG (0x0B00 017A) ........................................................................................................ 312
15.2.11 INTREG (0x0B00 017C) .......................................................................................................... 313
15.2.12 MCNVC_END (0x0B00 017E) ................................................................................................. 314
15.3 Operation Sequence ............................................................................................................. 315
15.3.1 Output (speaker) ........................................................................................................................ 315
15.3.2 Input (microphone) .................................................................................................................... 316
CHAPTER 16 KEYBOARD INTERFACE UNIT (KIU) ....................................................................... 317
16.1 General .................................................................................................................................... 317
16.2 Functional Description .......................................................................................................... 317
16.2.1 Automatic keyboard scan mode (Auto Scan mode) .................................................................. 318
16.2.2 Manual keyboard scan mode (Manual Scan mode) .................................................................. 318
16.2.3 Key press detection ................................................................................................................... 318
16.2.4 Scan operation .......................................................................................................................... 319
16.2.5 Reading scanned data ............................................................................................................... 320
16.2.6 Interrupts and status reporting ................................................................................................... 320
16.3 Register Set ............................................................................................................................ 321
16.3.1 KIUDATn (0x0B00 0180 to 0x0B00 018E) ................................................................................ 322
16.3.2 KIUSCANREP (0x0B00 0190) ................................................................................................... 323
16.3.3 KIUSCANS (0x0B00 0192) ........................................................................................................ 324
16.3.4 KIUWKS (0x0B00 0194) ............................................................................................................ 325
16.3.5 KIUWKI (0x0B00 0196) ............................................................................................................. 326
16.3.6 KIUINT (0x0B00 0198) .............................................................................................................. 327
CHAPTER 17 COMPACTFLASH CONTROLLER (ECU) .................................................................. 328
17.1 General .................................................................................................................................... 328
17.2 Register Set Summary ........................................................................................................... 328
17.3 ECU Control Registers .......................................................................................................... 331
17.3.1 INTSTATREG (0x0B00 08F8) ................................................................................................... 331
17.3.2 INTMSKREG (0x0B00 08FA) .................................................................................................... 332
17.3.3 CFG_REG_1 (0x0B00 08FE) .................................................................................................... 333
17.4 ECU Registers ........................................................................................................................ 334
17.4.1 ID_REV_REG (Index: 0x00) ...................................................................................................... 334
17.4.2 IF_STAT_REG (Index: 0x01) ..................................................................................................... 335
17.4.3 PWRRSETDRV (Index: 0x02) ................................................................................................... 336
17.4.4 ITGENCTREG (Index: 0x03) ..................................................................................................... 337
17.4.5 CDSTCHGREG (Index: 0x04) ................................................................................................... 338
17.4.6 CRDSTATREG (Index: 0x05) .................................................................................................... 339
17.4.7 ADWINENREG (Index: 0x06) .................................................................................................... 340
17.4.8 IOCTRL_REG (Index: 0x07) ...................................................................................................... 341
17.4.9 IOADSLBnREG (Index: 0x08, 0x0C) ......................................................................................... 342
17.4.10 IOADSHBnREG (Index: 0x09, 0x0D) ...................................................................................... 342
17.4.11 IOSLBnREG (Index: 0x0A, 0x0E) ............................................................................................ 343
17.4.12 IOSHBnREG (Index: 0x0B, 0x0F) ........................................................................................... 343