NEC Renesas mPD720210 Instructions for use

User’s Manual
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
μ PD720210
User’s Manual: Hardware
Rev.2.00 May 2014
ASSP (Four-port USB 3.0 Hub Controller)
www.renesas.com

Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software,
and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you
or third parties arising from the use of these circuits, software, or information.
2. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics
does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages
incurred by you resulting from errors in or omissions from the information included herein.
3. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of
third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No
license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of
Renesas Electronics or others.
4. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration,
modification, copy or otherwise misappropriation of Renesas Electronics product.
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recommended applications for each Renesas Electronics product depends on the product’s quality grade, as indicated below.
“Standard”: Computers; office equipment; communications equipment; test and measurement equipment; audio and visual
equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc.
“High Quality”: Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-
crime systems; and safety equipment etc.
Renesas Electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to
human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property
damages (nuclear reactor control systems, military equipment etc.). You must check the quality grade of each Renesas
Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any
application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred
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Electronics.
6. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics,
especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or
damages arising out of the use of Renesas Electronics products beyond such specified ranges.
7. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have
specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further,
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and regulations.
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manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. You should not use
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by the military, including but not limited to the development of weapons of mass destruction. When exporting the Renesas
Electronics products or technology described in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations.
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places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this
document, Renesas Electronics assumes no responsibility for any losses incurred by you or third parties as a result of
unauthorized use of Renesas Electronics products.
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Electronics.
12. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document
or Renesas Electronics products, or if you have any other inquiries.
(Note 1) “Renesas Electronics” as used in this document means Renesas Electronics Corporation and also includes its majority-
owned subsidiaries.
(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
(2012.4)

NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected
wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH
(MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the
device when the input level is fixed, and also in the transition period when the input level passes through the
area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of
static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control
must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators
that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work benches
and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with
mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device.
Immediately after the power source is turned ON, devices with reset functions have not yet been initialized.
Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not
initialized until the reset signal is received. A reset operation must be executed immediately after power-on
for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and external interface, as a rule, switch on the external power supply after switching on the internal
power supply. When switching the power supply off, as a rule, switch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for
each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while
the device is not powered. The current injection that results from input of such a signal or I/O pull-up power
supply may cause malfunction and the abnormal current that passes in the device at this time may cause
degradation of internal elements. Input of signals during the power off state must be judged separately for
each device and according to related specifications governing the device.

Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States
and/or other countries.

PREFACE
Readers This manual is intended for engineers who need to be familiar with the capability
of the μ PD720210 in order to develop application systems based on it.
Purpose The purpose of this manual is to help users understand the hardware capabilities
(listed below) of the
μ PD720210.
Configuration This manual consists of the following chapters:
•Overview
•Pin function
•External ROM settings
•USB descriptor information
•Pin strapping
•Functions description
•Peripheral component connection
Guidance Readers of this manual should already have a general knowledge of electronics,
logic circuits, and microcomputers.
Notation This manual uses the following conventions:
Data bit significance: High-order bits on the left side;
low-order bits on the right side
Active low: XXXXB (Pin and signal names are suffixed with B.)
Note: Explanation of an indicated part of text
Caution: Information requiring the user’s special attention
Remark: Supplementary information
Numerical value: Binary ... xxxx or xxxxb
Decimal ... xxxx
Hexadecimal ... xxxxh
Related Document Use this manual in combination with the following document.
The related documents indicated in this publication may include preliminary
versions. However, preliminary versions are not marked as such.
•
μ PD720210 Data Sheet: R19DS0070E

CONTENTS
1. Overview..............................................................................................................................................1
1.1 Features....................................................................................................................................1
1.2 Applications .............................................................................................................................2
1.3 Ordering Information ..............................................................................................................2
1.4 Block Diagram .........................................................................................................................3
1.5 Pin Configuration ....................................................................................................................5
2. Pin Function ........................................................................................................................................6
2.1 Power Supply...........................................................................................................................6
2.2 Analog Interface ......................................................................................................................7
2.3 System Clock ...........................................................................................................................7
2.4 System Interface Pins .............................................................................................................8
2.5 USB Port Control Pins ............................................................................................................9
2.6 USB Data Pins........................................................................................................................10
2.7 SPI Interface...........................................................................................................................11
2.8 Test Pin...................................................................................................................................11
3. External ROM Settings.....................................................................................................................12
3.1 Overview.................................................................................................................................12
3.2 Supported ROMs ...................................................................................................................12
3.3 ROM Contents........................................................................................................................13
3.4 Configurable Items................................................................................................................14
3.5 Low Power Mode during Suspend.......................................................................................15
4. USB Descriptor Information ............................................................................................................16
4.1 SuperSpeed Descriptors ......................................................................................................16
4.1.1 Device Descriptor ..................................................................................................................16
4.1.2 BOS Descriptor .....................................................................................................................17
4.1.3 Configuration Descriptor........................................................................................................19
4.1.4 Hub Descriptor ......................................................................................................................21
4.2 High Speed Standard Descriptor .........................................................................................22
4.2.1 Device Descriptor ..................................................................................................................22
4.2.2 BOS Descriptor .....................................................................................................................23
4.2.3 Device Qualifier Descriptor....................................................................................................24
4.2.4 Configuration Descriptor........................................................................................................24
4.2.5 Interface Descriptor (combined with Configuration Descriptor) .............................................25
4.2.6 Endpoint Descriptor (combined with Configuration Descriptor) .............................................25
4.2.7 Other Speed Configuration Descriptor ..................................................................................25
4.2.8 Interface Descriptor (combined with Other Speed Configuration Descriptor) ........................26
4.2.9 Endpoint Descriptor (combined with Other Speed Configuration Descriptor)........................26
4.2.10 Class Specified Hub Class Descriptor...................................................................................27
4.3 Full Speed Standard Descriptor...........................................................................................28
4.3.1 Device Descriptor ..................................................................................................................28
4.3.2 BOS Descriptor .....................................................................................................................28
4.3.2.1 USB 2.0 Extension...........................................................................................28
4.3.2.2 SuperSpeed USB.............................................................................................29
4.3.2.3 Container ID.....................................................................................................29
4.3.3 Device Qualifier Descriptor....................................................................................................29

4.3.4 Configuration Descriptor........................................................................................................30
4.3.5 Interface Descriptor (combined with Configuration Descriptor) .............................................30
4.3.6 Endpoint Descriptor (combined with Configuration Descriptor) .............................................30
4.3.7 Other Speed Configuration Descriptor ..................................................................................31
4.3.8 Interface Descriptor (combined with Other Speed Configuration Descriptor) ........................31
4.3.9 Endpoint Descriptor (combined with Other Speed Configuration Descriptor)........................31
5. Pin Strapping ....................................................................................................................................32
5.1 Pin Strapping Settings..........................................................................................................32
5.1.1 External SPI ROM.................................................................................................................32
5.1.2 LED function..........................................................................................................................33
5.1.3 Number of ports.....................................................................................................................33
5.1.4 Non-Removable Ports ...........................................................................................................34
5.1.5 Gang / Individual Port Power Control ....................................................................................34
5.1.6 Battery Charging mode .........................................................................................................35
5.1.7 GIO function ..........................................................................................................................36
5.1.8 Address length of External ROM...........................................................................................36
5.1.9 PPON1B Output function ......................................................................................................37
6. Functions Description......................................................................................................................38
6.1 Battery Charging ...................................................................................................................38
6.1.1 Battery Charging Mode .........................................................................................................39
6.1.2 HW configuration requirement...............................................................................................41
6.1.3 Downstream port VBUS control.............................................................................................41
6.2 Remote Wake Up function....................................................................................................42
6.2.1 Remote Wake Up function ....................................................................................................42
6.3 Clock Output Function..........................................................................................................43
6.3.1 Clock Output Usage ..............................................................................................................43
6.3.2 Clock Output Function Settings.............................................................................................44
6.3.3 Clock Output Function Control ..............................................................................................45
7. Peripheral Component Connection ................................................................................................46
7.1 Unused Pin Connection........................................................................................................46
7.2 USB Upstream Port Connection ..........................................................................................47
7.3 USB Downstream Port Connection .....................................................................................48
7.4 VBUS Power Switching Connection....................................................................................49
7.4.1 USB Power Switch ................................................................................................................49
7.4.2 Current Limiter.......................................................................................................................50
7.5 Crystal Connection................................................................................................................51
7.6 RESET Connection................................................................................................................52
7.7 RREF Connection ..................................................................................................................53
7.8 Internal LDO (5V 3.3V) Connection (in use) ...................................................................54
7.9 Internal LDO (5 V 3.3 V) Connection (out of use) ..........................................................55
7.10 Internal Switching Regulator (5 V 1.05 V) Connection (in use)....................................56
7.11 Internal Switching Regulator (5 V 1.05 V) Connection (out of use) .............................57
7.12 External Serial ROM Connection .........................................................................................58
7.13 LED Control Connection.......................................................................................................59

LIST OF FIGURES
Figure No. Title Page
1-1 μPD720210 Block Diagram.............................................................................................................................3
1-2 Pin Configuration of μ PD720210 (Top View) ..................................................................................................5
6-1 VBUS Control Configuration with Battery Charging Function........................................................................41
6-2 Downstream Port VBUS Control ...................................................................................................................41
6-3 Remote Wake Up Function ...........................................................................................................................42
6-4 Clock Output Usage (without External ROM)................................................................................................43
7-1 USB Upstream Port Connection....................................................................................................................47
7-2 USB Downstream Port Connection ...............................................................................................................48
7-3 VBUS Switch Connection..............................................................................................................................49
7-4 VBUS Current Limiter Connection.................................................................................................................50
7-5 Crystal Connection........................................................................................................................................51
7-6 Reset Connection..........................................................................................................................................52
7-7 RREF Connection .........................................................................................................................................53
7-8 Internal LDO Connection in use ....................................................................................................................54
7-9 Internal LDO Connection out of use ..............................................................................................................55
7-10 Internal Switching Regulator Connection in use..........................................................................................56
7-11 Internal Switching Regulator Connection out of use....................................................................................57
7-12 External Serial ROM Connection ................................................................................................................58
7-13 LED Control Connection .............................................................................................................................59

LIST OF TABLES (1/2)
Table No. Title Page
1-1 Terminology ....................................................................................................................................................4
3-1 External SPI ROM Information......................................................................................................................13
4-1 Device Descriptor..........................................................................................................................................16
4-2 BOS Descriptor .............................................................................................................................................17
4-3 USB 2.0 Extension ........................................................................................................................................17
4-4 SuperSpeed Device Capabilities...................................................................................................................18
4-5 Container ID..................................................................................................................................................18
4-6 Configuration Descriptor ...............................................................................................................................19
4-7 Interface Descriptor.......................................................................................................................................19
4-8 Endpoint Descriptor.......................................................................................................................................20
4-9 Endpoint Companion Descriptor ...................................................................................................................20
4-10 Hub Descriptor ............................................................................................................................................21
4-11 Device Descriptor........................................................................................................................................22
4-12 BOS Descriptor ...........................................................................................................................................23
4-13 USB 2.0 Extension ......................................................................................................................................23
4-14 SuperSpeed USB........................................................................................................................................23
4-15 Container ID................................................................................................................................................23
4-16 Device Qualifier Descriptor..........................................................................................................................24
4-17 Configuration Descriptor..............................................................................................................................24
4-18 Interface Descriptor.....................................................................................................................................25
4-19 Endpoint Descriptor.....................................................................................................................................25
4-20 Other Speed Configuration Descriptor ........................................................................................................25
4-21 Interface Descriptor.....................................................................................................................................26
4-22 Endpoint Descriptor.....................................................................................................................................26
4-23 Class Specified Hub Class Descriptor.........................................................................................................27
4-24 Device Descriptor........................................................................................................................................28
4-25 BOS Descriptor ...........................................................................................................................................28
4-26 USB 2.0 Extension ......................................................................................................................................28
4-27 SuperSpeed USB........................................................................................................................................29
4-28 Container ID................................................................................................................................................29
4-29 Device Qualifier Descriptor..........................................................................................................................29
4-30 Configuration Descriptor..............................................................................................................................30
4-31 Interface Descriptor.....................................................................................................................................30
4-32 Endpoint Descriptor.....................................................................................................................................30
4-33 Other Speed Configuration Descriptor ........................................................................................................31
4-34 Interface Descriptor.....................................................................................................................................31
5-1 Pin Strapping Setting ....................................................................................................................................32
5-2 External SPI ROM.........................................................................................................................................32
5-3 LED Function ................................................................................................................................................33
5-4 Number of Ports............................................................................................................................................33
5-5 Non-Removable Ports...................................................................................................................................34
5-6 Gang / Individual Port Power Control............................................................................................................34
5-7 Battery Charging Mode .................................................................................................................................35
5-8 GIO Function.................................................................................................................................................36

LIST OF TABLES (2/2)
Table No. Title Page
5-9 Address Length of External ROM..................................................................................................................36
5-10 PPON1B Output Function ...........................................................................................................................37
6-1 Battery Charging Mode .................................................................................................................................39
6-2 Battery Charging Mode .................................................................................................................................40
6-3 Clock Output Function Settings.....................................................................................................................44
6-4 Clock Output Stop Condition.........................................................................................................................45
6-5 Clock Output Start Condition.........................................................................................................................45
7-1 Unused Pin Connection ................................................................................................................................46

User’s Manual
μ PD720210
ASSP (Four-port USB 3.0 Hub Controller)
R19UH0093EJ0200 Rev.2.00 Page 1 of 59
May 26, 2014
R19UH0093EJ0200
Rev.2.00
May 26, 2014
1. Overview
The μ PD720210 is a USB 3.0 hub controller that complies with the Universal Serial Bus (USB) Specification
Revision 3.0 and operates at up to 5 Gbps. The device incorporates Renesas’ market proven design
expertise in USB 3.0 interface technologies and market proven USB 2.0 hub core. The device is fully
compatible with all prior versions of USB spec and 100 % compatible with Renesas’ industry standard USB 3.0
host controller. It comes in a small 76-pin QFN package and integrates several commonly required external
components, making it ideally suited for applications with limited PCB space. In addition,
μ PD720210
incorporates Renesas’ low-power technologies and supports all mainstream battery charging specifications.
1.1 Features
Compliant with Universal Serial Bus 3.0 Specification Revision 1.0, which is released by USB
Implementers Forum, Inc.
-Supports the following speed data rate. : Low-speed (1.5 Mbps) / Full-speed (12 Mbps) /
High-speed (480 Mbps) / SuperSpeed (5 Gbps)
-Supports USB 3.0 link power management (U0/U1/U2/U3)
-Supports USB 2.0 link power management (LPM: L0/L1/L2/L3)
Configurable downstream port count of 2, 3, or 4
Supports all VBUS control options
-Individual or global over-current detection
-Individual or ganged power control
Supports USB 3.0/2.0 Compound (non-removable) devices by I/O pin configuration
Supports clock output (24/12 MHz) for Compound (non-removal) device on downstream ports
Supports Energy Star and EuP specifications for low-power PC peripherals and monitors
Single 5V Power Supply
-On chip LDO for 3.3 V from 5 V input and Switching Regulator for 1.05 V from 5 V input
System clock: 24 MHz Crystal or Oscillator
Supports USB Battery Charging Specification Revision 1.2 and other portable devices
-DCP mode of BC 1.2
-CDP mode of BC 1.2
-China Mobile Phone Chargers
-EU Mobile Phone Chargers
-Apple iOS devices
-Other major portable devices
Supports SPI ROM for optional firmware and parameter data
Small Footprint
-Small and low pin count package with simple pin assignment for PCB layout
-Integration of many peripheral components
-Direct routing of all USB signal traces to connector pins using one layer of the PCB
Self/Bus-Powered modes can be set by pin strapping
Integrated termination resistors for USB
Provides SUSPEND status output
Supports Port Indicator control (only Green color)

μ PD720210 1. Overview
R19UH0093EJ0200 Rev.2.00 Page 2 of 59
May 26, 2014
1.2 Applications
Standalone Hub, Monitor-Hub, Docking Station, Integrated Hub, etc.
1.3 Ordering Information
Part Number Package Operating Temperature Remark
μ PD720210K8-BAF-A 76-pin QFN (9 ×9) 0 to +70°C Lead-free product

μ PD720210 1. Overview
R19UH0093EJ0200 Rev.2.00 Page 3 of 59
May 26, 2014
1.4 Block Diagram
Figure 1-1. μPD720210 Block Diagram
SS-PHY
HS/FS/LS PHY
SS-PHY
HS/FS/LS PHY
SS-PHY
HS/FS/LS PHY
SS-PHY
HS/FS/LS PHY
SS
DS Port
Control
SS
Hub Core
HS/FS/LS
Hub Core
SS-PHY
HS/FS/LS PHY
VBUS Monitor
USB
Connector
USB
Connector
USB
Connector
USB
Connector
USB
Connector
VBUS
Switch
VBUS
Switch
VBUS
Switch
VBUS
Switch
VBUS
VBUS
Control
5v
SW Regulator
(V50IN -> VDD10)
3.3v
1.05v
FET
Control
5v
SPI
I/F
SPI
ROM
OSC
24MHz
CLKOUT
12/24MHz
LDO
(V50IN -> VDD33) HS/FS/LS
DS Port
Control
SS
US Port
Control
HS/FS/LS
US Port
Control

μ PD720210 1. Overview
R19UH0093EJ0200 Rev.2.00 Page 4 of 59
May 26, 2014
Table 1-1. Terminology
Block Name Description
SS PHY SuperSpeed transceiver
HS/FS/LS PHY High-/Full-/Low-speed transceiver
VBUS Monitor Monitors the VBUS voltage level of the upstream port.
SS US Port
Control
Upstream port control logic for SuperSpeed
HS/FS/LS US
Port Control
Upstream port control logic for High-/Full-/Low-speed
SS Hub Core Central control logic for SS-Hub.
HS/FS/LS Hub
Core
Central control logic for HS/FS/LS Hub.
SS DS Port
Control
Downstream port control logic for SuperSpeed
HS/FS/LS DS
Port Control
Downstream port control logic for HS/FS/LS
VBUS Control Controls all the external port power switches
SPI Interface Connected to external serial ROM which can hold the optional firmware and hub settings
SW-Regulator Switching regulator control logic to output 1.05 V power from 5 V input, utilizing the
external transisto
r
LDO Integrated Low Drop Out regulator to output 3.3 V power from 5 V input.

μ PD720210 1. Overview
R19UH0093EJ0200 Rev.2.00 Page 5 of 59
May 26, 2014
1.5 Pin Configuration
•76-pin QFN (9 ×9)
μ PD720210K8-BAF-A
Figure 1-2. Pin Configuration of μ PD720210 (Top View)
VDD33 XT2 XT1 IC(L) RREF AVDD33 VDD10 U3RXDPU U3RXDNU VDD10 U3TXDPU U3TXDNU VDD10 U2DMU U2DPU VDD33 PPON4B OCI4B PPON3B
GND
U3TXDP3
U3TXDN3
VDD10
U3RXDP3
U3RXDN3
VDD33
U2DP3
U2DM3
VDD10
U3TXDP4
U3TXDN4
VDD10
U3RXDP4
U3RXDN4
VDD33
U2DP4
U2DM4
LED1B/SUSPEND
SPICSB
OCI3B
PPON2B
OCI2B
V10FB
ILIM
NGDRV
PGDRV
AVDD33R
V50IN
V33OUT
VDD10
PPON1B/NRDRSTB
OCI1B
BUSSEL
VBUSM
VDD33
SPISCK/LED4B
SPISO/LED3B
SPISI/LED2B
SUSPEND/NRDCLKO
RESETB
U3TXDP1
U3TXDN1
VDD10
U3RXDP1
U3RXDN1
VDD33
U2DP1
U2DM1
VDD10
U3TXDP2
U3TXDN2
VDD10
U3RXDP2
U3RXDN2
VDD33
U2DP2
U2DM2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58

μ PD720210 2. Pin Function
R19UH0093EJ0200 Rev.2.00 Page 6 of 59
May 26, 2014
2. Pin Function
This section describes each pin function.
Strapping information in the tables shows how the pin can be used to configure the functional settings of this
controller when the pin is pulled up/down, as detected at the end of chip reset. Refer to Chapter 5 for a
complete description of all available pin strap settings. Also refer to Section 3.4 for a list of chip configuration
settings available via external SPI ROM (optional).
2.1 Power Supply
Pin Name Pin No. I/O
Type Function
VDD10
5, 11, 14,
22, 28, 31,
47, 64, 67,
70
Power 1.05 V power supply for Core Logic
VDD33
8, 17, 25,
34, 42, 61,
76
Power 3.3 V power supply for IO buffer
AVDD33 71 Power 3.3 V power supply for Analog circuit
V50IN 49 Power
LDO Regulator 5 V Input
Need to be connected to GND, when integrated LDO is not
used.
V33OUT 48 Power
LDO 3.3 V Output
15 kΩand 4.7 μ F are required between this pin and GND,
when integrated LDO is not used.
AVDD33R 50 Power SW Regulator 3.3 V Input
NGDRV 52 - SW Regulator Nch FET Control (Note)
PGDRV 51 - SW Regulator Pch FET Control (Note)
ILIM 53 - SW Regulator Current Sense
V10FB 54 - SW Regulator Output Monitor
Note: See section 7.10 for important information about the selection of FET.

μ PD720210 2. Pin Function
R19UH0093EJ0200 Rev.2.00 Page 7 of 59
May 26, 2014
2.2 Analog Interface
Pin Name Pin No. I/O
Type Function
RREF 72 -
Reference Voltage Input for USB 2.0
RREF must be connected to a 1.6 kΩresistor with a tolerance of
+/- 1%.
It is strongly recommended to use a single resistor for 1.6 kΩ,
versus the combined resistance with multiple resistors to
achieve this value and tolerance.
2.3 System Clock
Pin Name Pin No. I/O
Type Function
XT1 74 IN
External Oscillator Input
Connect to 24 MHz crystal.
This pin can be a 3.3 V Oscillator input as well.
XT2 75 OUT
External Oscillator Output
Connect to 24 MHz crystal
When using single-ended clock input to XT1, this pin should be
left open.

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May 26, 2014
2.4 System Interface Pins
Pin Name Pin
No.
I/O
Type
Active
Level Function
SUSPEND/NRDCLKO 1 OUT High/NA
SUSPEND Output or CLKOUT depending on pin strap setting of
SPICSB and OCI1B.
SUSPEND is Suspend state output
1: in suspend state
0: not in suspend state
[Note]
SUSPEND/NRDCLKO output level is Hi-z till this pin function is
configured as SUSPEND output or clock output for
non-removable device
SPICSB OCI1B Pin Function
Low Low NRDCLKO
High SUSPEND
High X Depends on Serial ROM
setting
VBUSM 43 IN High
Upstream Port VBUS Monitor
Divide VBUS to 3.3V and connect to VBUSM
BUSSEL 44 IN N/A
Power Mode Select Input
0: Bus-power setting
1: Self-power setting
LED1B/SUSPEND 37 OUT Low
When the external ROM is not used (SPICSB is low),
LED1B/SUSPEND is used as LED function for LED1B pin for
port1 with the following pin strap settings. When the external
ROM is used (SPICSB is high) and SUSPEND function is enabled
in the ROM Writing Tool, LED1B/SUSPEND is used as
SUSPEND function. If the SUSPEND function is not enabled, this
pin is not functional (Hi-Z).
[Function]
LED1B is LED control output signal to indicate port enable. Note
that
μ PD720210 supports only Green Color of port indicator.
0: Port is enabled
Hi-Z: Port is disabled
Suspend state is shown by the following pin level.
1: in suspend state
0: not in suspend state
SPICSB SPISCK/
LED4B
SPISO/
LED3B
SPISI/
LED2B
LED1B/
SUSPEND
Pin Function
Low High High High High LED1B
Low Others High Reserved (Hi-Z)
Low X X X Low Reserved (Hi-Z)
High X X X X SUSPEND or Hi-Z
[Pin strapping option]
- LED function (Refer to Chapter 5.1.2)
- Battery Charging mode (Refer to Chapter 5.1.6)
- Address length of external ROM (Refer to Chapter 5.1.8)
RESETB 2 IN Low Chip Reset Input

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May 26, 2014
2.5 USB Port Control Pins
Pin Name Pin No. I/O
Type
Active
Level Function
OCI1B 45 IN Low
[Function]
Over Current Input
0: Over-current condition is detected.
1: Non over-current condition is detected.
[Pin strapping option]
OCI1B Pin Function
High Removable device setting
and Over current input.
Low Non-Removable setting.
This pin is used to select non-removable setting.
OCI2B, OCI3B,
OCI4B
55, 57,
59 IN Low
[Function]
Over Current Input
0: Over-current condition is detected.
1: Non over-current condition is detected.
[Pin strapping option]
OCIXB Pin Function
High Removable device setting
and Over Current Input.
Low Non-Removable setting.
This pin is used to select non-removable setting.
PPON1B/NRDRSTB 46 I/O Low
[Function]
Port Power Control or NRDRSTB (Non-Removable
Device Reset) depending on pin strap setting of this
pin.
PPON1B/NRDRSTB Pin Function
High PPON1B
Low NRDRSTB
PPON1B is a Port Power Control signal
0: Power supply for VBUS is on.
1: Power supply for VBUS is off.
NRDRSTB is a reset signal for Non-Removable
device.
PPON2B 56 I/O Low
[Function]
This pin is a Port Power Control signal.
0: Power supply for VBUS is on.
1: Power supply for VBUS is off.
[Pin strapping option]
This pin is used for pin strapping option:
Gang/Individual Power Control of all ports.
PPON2B Gang/Individual Mode
High Individual
Low Gang

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May 26, 2014
Pin Name Pin No. I/O
Type
Active
Level Function
PPON3B, PPON4B 58, 60 I/O Low
[Function]
These pins are a Port Power Control signal.
0: Power supply for VBUS is on.
1: Power supply for VBUS is off.
[Pin strapping option]
These pins are used for pin strapping options to select
Number of ports.
PPON4B PPON3B Number of ports
Low Low 2 ports setting
Port 3 & 4 are not used.
Low High 3 ports setting
Port 4 is not used
High Low Prohibit setting
High High All ports are used
2.6 USB Data Pins
Pin Name Pin No. I/O
Type Function
U3TXDN1,
U3TXDN2,
U3TXDN3,
U3TXDN4
4, 13, 21,
30 OUT USB 3.0 Downstream Transmit data D- signal for SuperSpeed
U3TXDNU 65 OUT USB 3.0 Upstream Transmit data D- signal for SuperSpeed
U3TXDP1,
U3TXDP2,
U3TXDP3,
U3TXDP4
3, 12, 20,
29 OUT USB 3.0 Downstream Transmit data D+ signal for SuperSpeed
U3TXDPU 66 OUT USB 3.0 Upstream Transmit data D+ signal for SuperSpeed
U3RXDN1,
U3RXDN2,
U3RXDN3,
U3RXDN4
7, 16, 24,
33 IN USB 3.0 Downstream Receive data D- signal for SuperSpeed
U3RXDNU 68 IN USB 3.0 Upstream Receive data D- signal for SuperSpeed
U3RXDP1,
U3RXDP2,
U3RXDP3,
U3RXDP4
6, 15, 23,
32 IN USB 3.0 Downstream Receive data D+ signal for SuperSpeed
U3RXDPU 69 IN USB 3.0 Upstream Receive data D+ signal for SuperSpeed
U2DN1, U2DN2,
U2DN3, U2DN4
10, 19, 27,
36 I/O USB 2.0 Downstream D- signal for High-/Full-/Low-speed
U2DNU 63 I/O USB 2.0 Upstream D- signal for High-/Full-/Low-speed
U2DP1, U2DP2,
U2DP3, U2DP4
9, 18, 26,
35 I/O USB 2.0 Downstream D+ signal for High-/Full-/Low-speed
U2DPU 62 I/O USB 2.0 Upstream D+ signal for High-/Full-/Low-speed