NEC V850E/MS1 UPD703100 User manual

User’s Manual
µ
µµ
µ
PD703100
µ
µµ
µ
PD703100A
µ
µµ
µ
PD703101
µ
µµ
µ
PD703101A
µ
µµ
µ
PD703102
µ
µµ
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PD703102A
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PD70F3102
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PD70F3102A
Printed in Japan
Document No. U12688EJ4V0UM00 (4th edition)
Date Published January 2000 N CP(K)
V850E/MS1TM
32-/16-Bit Single-Chip Microcontrollers
Hardware
1997©

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User’s Manual U12688EJ4V0UM00 3
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimatelydegradethedeviceoperation. Stepsmustbetakentostopgenerationofstaticelectricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulatorsthateasilybuildstaticelectricity. Semiconductordevicesmustbestoredandtransported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wriststrap. Semiconductordevicesmust notbetouchedwithbarehands. Similarprecautionsneed
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
totheinputpins, it is possible that an internalinputlevelmaybegenerateddue to noise, etc., hence
causingmalfunction. CMOSdevicesbehave differentlythanBipolarorNMOS devices. Inputlevels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
V850E/MS1 and V850 Family are trademarks of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or
other countries.

User’s Manual U12688EJ4V0UM00
4
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
License not needed:
µ
PD703100, 703100A, 70F3102, 70F3102A
The customer must judge the need for license:
µ
PD703101, 703101A, 703102, 703102A
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98.8

User’s Manual U12688EJ4V0UM00 5
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: [phone]
800-366-9782
Fax: [phone]
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: [phone]
Fax: [phone]
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: [phone]
Fax: [phone]
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: [phone]
Fax: [phone]
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: [phone]
Fax: [phone]
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: [phone]
Fax: [phone]
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: [phone]
Fax: [phone]
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: [phone]
Fax: [phone]
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: [phone]
Fax: [phone]
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: [phone]
Fax: [phone]
J99.1

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User’s Manual U12688EJ4V0UM00 7
Major Revisions in This Edition
Page Description
p. 98 Change of R/W and bit units for manipulation for PMX and PMCX in 3.4.8 Peripheral I/O registers
p. 108 Addition of Caution to 4.5.2 (1) Bus size configuration register (BSC)
p. 151 Modification of WAIT signal in Figure 5-10 DRAM Access Timing During DMA Flyby Transfer
p. 172 Addition of interrupt factor (INTAD) to 6.3.6 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
p. 235 Deletion of part of explanation from 8.5.1 (3) (a) When in the PLL mode
p. 235 Deletion of 8.5.1 (3) (b) When in the Direct mode
p. 326 Modification of Figure 11-3 Select Mode Operation Timing: 1-Buffer Mode (ANI1)
p. 349 Change of block type of Port 2 in 12.2 (1) Function of each port
p. 355 Modification of Figure 12-3 Type C Block Diagram
p. 367 Addition of Figure 12-17 Type Q Block Diagram
p. 374 Change of block types of P22 and P25 in 12.3.3 (1) Operation in control mode
p. 375 Modification of Caution in 12.3.3 (2) (a) Port 2 mode register (PM2)
p. 378 Deletion of Caution from 12.3.4 (2) (a) Port 3 mode register (PM3)
p. 398 Deletion of Caution from 12.3.12 (2) (a) Port 11 mode register (PM11)
p. 407 Addition of Caution and modification of explanation in 12.3.16 (2) (a) Port X mode register (PMX)
p. 408 Addition of Caution and modification of explanation in 12.3.16 (2) (b) Port X mode control register (PMCX)
The mark shows major revised points.

User’s Manual U12688EJ4V0UM00
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User’s Manual U12688EJ4V0UM00 9
INTRODUCTION
Readers This manual is intended for users who wish to understand the functions of the
V850E/MS1 (
µ
PD703100, 703100A, 703101, 703101A, 703102, 703102A, 70F3102,
70F3102A) to design application systems using the V850E/MS1.
Purpose This manual is designed to help users understand the hardware functions of the
V850E/MS1.
Organization The V850E/MS1 User’s Manual consists of two manuals: Hardware (this manual) and
Architecture (V850E/MS1 User’s Manual Architecture). The organization of each
manual is as follows:
Hardware Architecture
•Pin functions •Data type
•CPU function •Register set
•Internal peripheral functions •Instruction format and instruction set
•Flash memory programming •Interrupts and exceptions
•Pipeline operation
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
•To find the details of a register where the name is known
→Refer to APPENDIX A REGISTER INDEX.
•To find the details of a function, etc. where the name is known
→Refer to APPENDIX C INDEX.
•To understand the details of an instruction function
→Refer to the V850E/MS1 User’s Manual Architecture.
•To understand the overall functions of the V850E/MS1
→Read this manual in the order of the CONTENTS.

User’s Manual U12688EJ4V0UM00
10
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: xxx (overscore over pin or signal name)
Memory map address: Higher address on the top and lower address on the bottom
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representation: Binary ... xxxx or xxxxB
Decimal ... xxxx
Hexadecimal ... xxxxH
Prefix indicating power of 2
(address space, memory K (kilo) ... 210 = 1,024
capacity): M (mega) ... 220 = 1,0242
G (giga) ... 230 = 1,0243
Data type: Word ... 32 bits
Halfword ... 16 bits
Byte ... 8 bits

User’s Manual U12688EJ4V0UM00 11
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Document related to device
Document Name Document No.
µ
PD703100-33, 703100-40, 703101-33, 703102-33 Data Sheet U13995E
µ
PD703100A-33, 703100A-40, 703101A-33, 703102A-33 Data Sheet U14168E
µ
PD70F3102-33 Data Sheet U13844E
µ
PD70F3102A-33 Data Sheet U13845E
V850E/MS1 User’s Manual Hardware This manual
V850E/MS1 User’s Manual Architecture U12197E
V850E/MS1 Application Note Hardware U14214E
Documents related to development tools (User’s Manuals)
Document Name Document No.
IE-703102-MC (In-circuit Emulator) U13875E
IE-703102-MC-EM1, IE-703102-MC-EM1-A (In-circuit Emulator Option
Board) U13876E
Operation U13998E
C Language U13997E
Assembly Language U13828E
CA850 (C Compiler Package)
Project Manager U13996E
Basics U13430ERX850 (Real-Time OS)
Installation U13410E
Fundamental U13773ERX850 Pro (Real-Time OS)
Installation U13774E
ID850 (Integrated Debugger)
(Ver.1.31) Operation Windows™ Based U13716E
ID850 (Integrated Debugger)
(Ver.2.00 or later) Operation Windows Based U14217E
SM850 (System Simulator)
(Ver.2.00 or later) Operation Windows Based U13759E
RD850Note (Task Debugger) U11158E
RD850 (Ver.3.0) (Task Debugger) U13737E
RD850 Pro (Ver.3.0) (Task Debugger) U13916E
AZ850 (System Performance Analyzer) U14410E
PG-FP3 (Flash Memory Programmer) U13502E
Note Supporting ID850 (Ver.1.32)

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User’s Manual U12688EJ4V0UM00 13
CONTENTS
CHAPTER 1 INTRODUCTION................................................................................................................. 27
1.1 Outline......................................................................................................................................... 27
1.2 Features....................................................................................................................................... 28
1.3 Applications................................................................................................................................ 30
1.4 Ordering Information ................................................................................................................. 30
1.5 Pin Configuration (Top View).................................................................................................... 31
1.6 Function Block ........................................................................................................................... 35
1.6.1 Internal block diagram...................................................................................................................35
1.6.2 Internal units..................................................................................................................................36
CHAPTER 2 PIN FUNCTIONS................................................................................................................. 39
2.1 List of Pin Functions.................................................................................................................. 39
2.2 Pin Status.................................................................................................................................... 47
2.3 Description of Pin Functions .................................................................................................... 49
2.4 Pin Input/Output Circuits and Recommended Connection of Unused Pins........................ 65
2.5 Pin Input/Output Circuits........................................................................................................... 67
CHAPTER 3 CPU FUNCTION ................................................................................................................ 69
3.1 Features....................................................................................................................................... 69
3.2 CPU Register Set........................................................................................................................ 70
3.2.1 Program register set......................................................................................................................71
3.2.2 System register set........................................................................................................................72
3.3 Operation Modes........................................................................................................................ 74
3.3.1 Operation modes...........................................................................................................................74
3.3.2 Operation mode specification........................................................................................................75
3.4 Address Space............................................................................................................................ 76
3.4.1 CPU address space.......................................................................................................................76
3.4.2 Image.............................................................................................................................................77
3.4.3 Wrap-around of CPU address space.............................................................................................78
3.4.4 Memory map..................................................................................................................................79
3.4.5 Area...............................................................................................................................................80
3.4.6 External expansion mode..............................................................................................................87
3.4.7 Recommended use of address space...........................................................................................89
3.4.8 Peripheral I/O registers..................................................................................................................92
3.4.9 Specific registers.........................................................................................................................100
CHAPTER 4 BUS CONTROL FUNCTION .......................................................................................... 103
4.1 Features..................................................................................................................................... 103
4.2 Bus Control Pins ...................................................................................................................... 103
4.3 Memory Block Function........................................................................................................... 104
4.4 Bus Cycle Type Control Function........................................................................................... 105
4.4.1 Bus cycle type configuration register (BCT)................................................................................105
4.5 Bus Access............................................................................................................................... 107
4.5.1 Number of access clocks.............................................................................................................107

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4.5.2 Bus sizing function.......................................................................................................................108
4.5.3 Bus width .....................................................................................................................................109
4.6 Wait Function............................................................................................................................113
4.6.1 Programmable wait function ........................................................................................................113
4.6.2 External wait function...................................................................................................................114
4.6.3 Relationship between programmable wait and external wait.......................................................114
4.6.4 Bus cycles in which the wait function is valid...............................................................................115
4.7 Idle State Insertion Function ...................................................................................................117
4.8 Bus Hold Function....................................................................................................................119
4.8.1 Outline of function........................................................................................................................119
4.8.2 Bus hold procedure......................................................................................................................120
4.8.3 Operation in power save mode....................................................................................................120
4.8.4 Bus hold timing............................................................................................................................121
4.9 Bus Priority Order.....................................................................................................................122
4.10 Boundary Operation Conditions.............................................................................................122
4.10.1 Program space ............................................................................................................................122
4.10.2 Data space...................................................................................................................................123
CHAPTER 5 MEMORY ACCESS CONTROL FUNCTION.................................................................125
5.1 SRAM, External ROM, External I/O Interface..........................................................................125
5.1.1 SRAM connections ......................................................................................................................125
5.1.2 SRAM, external ROM, external I/O access..................................................................................126
5.2 Page ROM Controller (ROMC).................................................................................................130
5.2.1 Features.......................................................................................................................................130
5.2.2 Page ROM connections...............................................................................................................130
5.2.3 On-page/off-page judgment.........................................................................................................132
5.2.4 Page ROM configuration register (PRC)......................................................................................134
5.2.5 Page ROM access.......................................................................................................................135
5.3 DRAM Controller.......................................................................................................................136
5.3.1 Features.......................................................................................................................................136
5.3.2 DRAM connections......................................................................................................................137
5.3.3 Address multiplex function...........................................................................................................138
5.3.4 DRAM configuration registers 0 to 3 (DRC0 to DRC3)...............................................................139
5.3.5 DRAM type configuration register (DTC).....................................................................................142
5.3.6 DRAM access..............................................................................................................................143
5.3.7 DRAM access during DMA flyby transfer.....................................................................................151
5.3.8 Refresh control function...............................................................................................................153
5.3.9 Self-refresh functions...................................................................................................................158
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)....................................................................161
6.1 Features.....................................................................................................................................161
6.2 Configuration............................................................................................................................162
6.3 Control Registers......................................................................................................................163
6.3.1 DMA source address registers 0 to 3 (DSA0 to DSA3) ...............................................................163
6.3.2 DMA destination address registers 0 to 3 (DDA0 to DDA3) ........................................................165
6.3.3 DMA byte count registers 0 to 3 (DBC0 to DBC3).......................................................................167
6.3.4 DMA addressing control registers 0 to 3 (DADC0 to DADC3).....................................................168
6.3.5 DMA channel control registers 0 to 3 (DCHC0 to DCHC3)..........................................................170

User’s Manual U12688EJ4V0UM00 15
6.3.6 DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)...............................................................171
6.3.7 DMA disable status register (DDIS).............................................................................................173
6.3.8 DMA restart register (DRST) .......................................................................................................173
6.3.9 Flyby transfer data wait control register (FDW)...........................................................................174
6.4 DMA Bus States........................................................................................................................ 175
6.4.1 Types of bus states .....................................................................................................................175
6.4.2 DMAC state transition..................................................................................................................178
6.5 Transfer Mode........................................................................................................................... 179
6.5.1 Single transfer mode ...................................................................................................................179
6.5.2 Single-step transfer mode ...........................................................................................................180
6.5.3 Block transfer mode.....................................................................................................................180
6.6 Transfer Types.......................................................................................................................... 181
6.6.1 Two-cycle transfer.......................................................................................................................181
6.6.2 Flyby transfer...............................................................................................................................185
6.7 Transfer Objects....................................................................................................................... 189
6.7.1 Transfer type and transfer objects...............................................................................................189
6.7.2 External bus cycle during DMA transfer......................................................................................189
6.8 DMA Channel Priorities............................................................................................................ 190
6.9 Next Address Setting Function............................................................................................... 190
6.10 DMA Transfer Start Factors..................................................................................................... 191
6.11 Interrupting DMA Transfer....................................................................................................... 192
6.11.1 Interruption factors.......................................................................................................................192
6.11.2 Forcible interruption.....................................................................................................................192
6.12 Terminating DMA Transfer ...................................................................................................... 192
6.12.1 DMA transfer end interrupt..........................................................................................................192
6.12.2 Terminal count output..................................................................................................................192
6.12.3 Forcible termination.....................................................................................................................193
6.13 Boundary of Memory Area ...................................................................................................... 194
6.14 Transfer of Misalign Data ........................................................................................................ 194
6.15 Clocks of DMA Transfer........................................................................................................... 194
6.16 Maximum Response Time to DMA Request .......................................................................... 194
6.17 One Time Single Transfer with DMARQ0 to DMARQ3.......................................................... 196
6.18 Bus Arbitration for CPU........................................................................................................... 197
6.19 Precaution................................................................................................................................. 197
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION ................................................. 199
7.1 Features..................................................................................................................................... 199
7.2 Non-Maskable Interrupt ........................................................................................................... 204
7.2.1 Operation.....................................................................................................................................205
7.2.2 Restore........................................................................................................................................207
7.2.3 Non-maskable interrupt status flag (NP) .....................................................................................208
7.2.4 Noise elimination.........................................................................................................................208
7.2.5 Edge detection function...............................................................................................................208
7.3 Maskable Interrupts.................................................................................................................. 209
7.3.1 Operation.....................................................................................................................................209
7.3.2 Restore........................................................................................................................................211
7.3.3 Priorities of maskable interrupts..................................................................................................212
7.3.4 Interrupt control register (xxICn)..................................................................................................216

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7.3.5 In-service priority register (ISPR).................................................................................................218
7.3.6 Maskable interrupt status flag (ID)...............................................................................................218
7.3.7 Noise elimination .........................................................................................................................219
7.3.8 Edge detection function...............................................................................................................220
7.4 Software Exception ..................................................................................................................222
7.4.1 Operation.....................................................................................................................................222
7.4.2 Restore........................................................................................................................................223
7.4.3 Exception status flag (EP) ...........................................................................................................224
7.5 Exception Trap..........................................................................................................................225
7.5.1 Illegal op code definition..............................................................................................................225
7.5.2 Operation.....................................................................................................................................226
7.5.3 Restore........................................................................................................................................226
7.6 Multiple Interrupt Processing Control....................................................................................227
7.7 Interrupt Latency Time.............................................................................................................229
7.8 Periods in Which Interrupt Is Not Acknowledged.................................................................229
CHAPTER 8 CLOCK GENERATOR FUNCTIONS..............................................................................231
8.1 Features.....................................................................................................................................231
8.2 Configuration............................................................................................................................231
8.3 Input Clock Selection...............................................................................................................232
8.3.1 Direct mode .................................................................................................................................232
8.3.2 PLL mode ....................................................................................................................................232
8.3.3 Clock control register (CKC)........................................................................................................233
8.4 PLL Lockup...............................................................................................................................234
8.5 Power Saving Control ..............................................................................................................235
8.5.1 Outline .........................................................................................................................................235
8.5.2 Control registers ..........................................................................................................................237
8.5.3 HALT mode..................................................................................................................................238
8.5.4 IDLE mode...................................................................................................................................240
8.5.5 Software STOP mode..................................................................................................................242
8.5.6 Clock output inhibit mode ............................................................................................................243
8.6 Securing Oscillation Stabilization Time .................................................................................244
8.6.1 Specifying securing of oscillation stabilization time.....................................................................244
8.6.2 Time base counter (TBC).............................................................................................................246
CHAPTER 9 TIMER/COUNTER FUNCTION (REAL-TIME PULSE UNIT)........................................247
9.1 Features.....................................................................................................................................247
9.2 Basic Configuration..................................................................................................................248
9.2.1 Timer 1.........................................................................................................................................251
9.2.2 Timer 4.........................................................................................................................................253
9.3 Control Registers......................................................................................................................254
9.4 Timer 1 Operation.....................................................................................................................262
9.4.1 Count operation ...........................................................................................................................262
9.4.2 Count clock selection...................................................................................................................263
9.4.3 Overflow.......................................................................................................................................264
9.4.4 Clearing/starting timer by TCLR1n signal input ...........................................................................265
9.4.5 Capture operation........................................................................................................................266
9.4.6 Compare operation......................................................................................................................269

User’s Manual U12688EJ4V0UM00 17
9.5 Timer 4 Operation..................................................................................................................... 271
9.5.1 Count operation...........................................................................................................................271
9.5.2 Count clock selection...................................................................................................................271
9.5.3 Overflow ......................................................................................................................................271
9.5.4 Compare operation......................................................................................................................272
9.6 Application Example................................................................................................................ 274
9.7 Precaution................................................................................................................................. 281
CHAPTER 10 SERIAL INTERFACE FUNCTION................................................................................ 283
10.1 Features..................................................................................................................................... 283
10.2 Asynchronous Serial Interfaces 0, 1 (UART0, UART1)......................................................... 284
10.2.1 Features ......................................................................................................................................284
10.2.2 Configuration...............................................................................................................................285
10.2.3 Control registers..........................................................................................................................287
10.2.4 Interrupt request..........................................................................................................................294
10.2.5 Operation.....................................................................................................................................295
10.3 Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3) ..................................................................... 299
10.3.1 Features ......................................................................................................................................299
10.3.2 Configuration...............................................................................................................................299
10.3.3 Control registers..........................................................................................................................301
10.3.4 Basic operation............................................................................................................................304
10.3.5 Transmission by CSI0 to CSI3 ....................................................................................................306
10.3.6 Reception by CSI0 to CSI3..........................................................................................................307
10.3.7 Transmission and reception by CSI0 to CSI3..............................................................................308
10.3.8 Example of system configuration.................................................................................................309
10.4 Dedicated Baud Rate Generators 0 to 2 (BRG0 to BRG2)................................................... 310
10.4.1 Configuration and function...........................................................................................................310
10.4.2 Baud rate generator compare registers 0 to 2 (BRGC0 to BRGC2)............................................313
10.4.3 Baud rate generator prescaler mode registers 0 to 2 (BPRM0 to BPRM2).................................314
CHAPTER 11 A/D CONVERTER.......................................................................................................... 315
11.1 Features..................................................................................................................................... 315
11.2 Configuration............................................................................................................................ 315
11.3 Control Registers ..................................................................................................................... 318
11.4 A/D Converter Operation ......................................................................................................... 323
11.4.1 Basic operation of A/D converter.................................................................................................323
11.4.2 Operation mode and trigger mode...............................................................................................324
11.5 Operation in A/D Trigger Mode ............................................................................................... 329
11.5.1 Select mode operations...............................................................................................................329
11.5.2 Scan mode operations.................................................................................................................331
11.6 Operation in Timer Trigger Mode............................................................................................ 332
11.6.1 Select mode operations...............................................................................................................333
11.6.2 Scan mode operations.................................................................................................................337
11.7 Operation in External Trigger Mode ....................................................................................... 341
11.7.1 Select mode operations (external trigger select).........................................................................341
11.7.2 Scan mode operations (external trigger scan).............................................................................343
11.8 Operating Precautions............................................................................................................. 345
11.8.1 Stopping conversion operation....................................................................................................345

User’s Manual U12688EJ4V0UM00
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11.8.2 External/timer trigger interval.......................................................................................................345
11.8.3 Operation of standby mode .........................................................................................................345
11.8.4 Compare match interrupt when in timer trigger mode..................................................................345
11.8.5 Timer 1 functions when in external trigger mode.........................................................................346
CHAPTER 12 PORT FUNCTIONS........................................................................................................347
12.1 Features.....................................................................................................................................347
12.2 Port Configuration....................................................................................................................348
12.3 Port Pin Functions....................................................................................................................368
12.3.1 Port 0...........................................................................................................................................368
12.3.2 Port 1...........................................................................................................................................371
12.3.3 Port 2...........................................................................................................................................374
12.3.4 Port 3...........................................................................................................................................377
12.3.5 Port 4...........................................................................................................................................380
12.3.6 Port 5...........................................................................................................................................382
12.3.7 Port 6...........................................................................................................................................384
12.3.8 Port 7...........................................................................................................................................386
12.3.9 Port 8...........................................................................................................................................387
12.3.10 Port 9 ...........................................................................................................................................391
12.3.11 Port 10 .........................................................................................................................................394
12.3.12 Port 11 .........................................................................................................................................397
12.3.13 Port 12 .........................................................................................................................................401
12.3.14 Port A...........................................................................................................................................403
12.3.15 Port B...........................................................................................................................................405
12.3.16 Port X...........................................................................................................................................407
CHAPTER 13 RESET FUNCTIONS......................................................................................................409
13.1 Features.....................................................................................................................................409
13.2 Pin Functions............................................................................................................................409
13.3 Initialization...............................................................................................................................410
CHAPTER 14 FLASH MEMORY (
µ
µµ
µ PD70F3102, 70F3102A)..............................................................413
14.1 Features.....................................................................................................................................413
14.2 Writing by Flash Programmer .................................................................................................413
14.3 Programming Environment .....................................................................................................414
14.4 Communication System...........................................................................................................414
14.5 Pin Handling..............................................................................................................................415
14.5.1 MODE3/VPP pin............................................................................................................................415
14.5.2 Serial interface pin.......................................................................................................................415
14.5.3 RESET pin...................................................................................................................................417
14.5.4 NMI pin ........................................................................................................................................417
14.5.5 MODE0 to MODE2 pins...............................................................................................................417
14.5.6 Port pin ........................................................................................................................................417
14.5.7 WAIT pin......................................................................................................................................417
14.5.8 Other signal pins..........................................................................................................................417
14.5.9 Power supply...............................................................................................................................418
14.6 Programming Method...............................................................................................................418
14.6.1 Flash memory control..................................................................................................................418

User’s Manual U12688EJ4V0UM00 19
14.6.2 Flash memory programming mode..............................................................................................419
14.6.3 Selection of communication mode...............................................................................................419
14.6.4 Communication command...........................................................................................................420
APPENDIX A REGISTER INDEX.......................................................................................................... 423
APPENDIX B INSTRUCTION SET LIST.............................................................................................. 431
B.1 General Examples .................................................................................................................... 431
B.2 Instruction Set (in Alphabetical Order) .................................................................................. 434
APPENDIX C INDEX.............................................................................................................................. 441

User’s Manual U12688EJ4V0UM00
20
LIST OF FIGURES (1/4)
Figure No. Title Page
3-1 Program Counter (PC)...................................................................................................................................71
3-2 Interrupt Source Register (ECR)....................................................................................................................72
3-3 Program Status Word (PSW).........................................................................................................................73
3-4 CPU Address Space......................................................................................................................................76
3-5 Image on Address Space ..............................................................................................................................77
3-6 Internal ROM Area in Single-Chip Mode 1.....................................................................................................84
3-7 Recommended Memory Map.........................................................................................................................91
4-1 Example of Inserting Wait States.................................................................................................................114
5-1 Example of Connection to SRAM................................................................................................................125
5-2 SRAM, External ROM, External I/O Access Timing.....................................................................................126
5-3 Example of Page ROM Connections...........................................................................................................130
5-4 On-Page/Off-Page Judgment for Page ROM Connection...........................................................................132
5-5 Page ROM Access Timing...........................................................................................................................135
5-6 Examples of Connections to DRAM ............................................................................................................137
5-7 Row Address/Column Address Output........................................................................................................138
5-8 High-Speed Page DRAM Access Timing.....................................................................................................143
5-9 EDO DRAM Access Timing.........................................................................................................................147
5-10 DRAM Access Timing During DMA Flyby Transfer .....................................................................................151
5-11 CBR Refresh Timing....................................................................................................................................157
5-12 CBR Self-Refresh Timing ............................................................................................................................159
6-1 DMAC Bus Cycle State Transition Diagram................................................................................................178
6-2 Single Transfer Example 1 ..........................................................................................................................179
6-3 Single Transfer Example 2 ..........................................................................................................................179
6-4 Single-Step Transfer Example 1..................................................................................................................180
6-5 Single-Step Transfer Example 2..................................................................................................................180
6-6 Block Transfer Example...............................................................................................................................180
6-7 Timing of Two-Cycle Transfer......................................................................................................................181
6-8 Timing of Flyby Transfer (DRAM →External I/O)........................................................................................185
6-9 Timing of Flyby Transfer (Internal Peripheral I/O →Internal RAM).............................................................188
6-10 Buffer Register Configuration ......................................................................................................................190