NEC mPD78C14 A Quick start guide

©
1994
The µ PD78C14(A)isasingle-chip,CMOS8-bitmicrocontrollerinwhicha16-bitALU,aROM,aRAM,anA/Dconverter,
a multifunction timer/event counter, and a serial interface are all integrated. Moreover, a 48-Kbyte external expansion
memory (ROM/RAM) can be connected.
Since the µ PD78C14(A) uses the CMOS construction, its operations are performed with low power consumption. By
using the standby function, functions such as data retention are performed with lower power consumption.
For details on functions, refer to the User’s Manual listed below. Please read it before starting design work.
87AD series
µ PD78C18 User’s Manual: IEU-1314
FEATURES
High reliability as compared with µ PD78C14
159 instructions: 87AD instruction set
Multiply and divide instructions, 16-bit arithmetic operation instructions
Instruction cycle: 0.8 µ s at 15 MHz
Internal ROM: 16384 W x 8
Internal RAM: 256 W x 8
Direct addressing to an external memory (ROM/RAM) up to 64 Kbytes
Highly accurate 8-bit A/D converter: Eight analog inputs
General-purpose serial interface: Asynchronous, synchronous, and I/O interface modes
Multifunction 16-bit timer/event counter
Two 8-bit timers
I/O lines: 44
Interrupt functions: Three external, eight internal
• Non-maskable interrupt: 1
• Maskable interrupts: 10
Zero-cross detection function (two inputs)
Standby functions: HALT mode, Hardware/software STOP mode
ORDERING INFORMATION
Part number Package Quality grade
µ PD78C14G(A)-xxx-36 64-pin plastic QUIP Special
µ PD78C14GF(A)-xxx-3BE 64-pin plastic QFP (14 x 20 mm) Special
µ PD78C14L(A)-xxx 68-pin plastic QFJ (950 x 950 mil) Special
Remark xxx is a ROM code suffix.
Document No. IC-2813B
(O.D. No. IC-8242B)
Date Published May 1995 P
Printed in Japan
µ PD78C14(A)
MOS INTEGRATED CIRCUIT
8-BIT SINGLE-CHIP MICROCONTROLLER (WITH A/D CONVERTER)
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
©
1991
HThe mark shows revised points.
*
DATA SHEET
The information in this document is subject to change without notice.
*

2
µ PD78C14(A)
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0/TxD
PC1/RxD
PC3/INT2
PC4/TO
PC5/CI
PC6/CO0
PC7/CO1
NMI
INT1
MODE1
RESET
MODE0
X2
X1
VSS
PB0
PC2/SCK
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
18
20
21
22
23
24
25
26
27
28
29
30
31
32
9
19
VDD
STOP
PD7
PD6
PD5
PD4
PD3
PD2
PD0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
WR
RD
AVDD
VAREF
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
AVSS
PD1
ALE
64
63
62
61
60
59
58
57
55
54
53
52
51
50
49
48
47
45
44
43
42
41
40
39
38
37
36
35
34
33
56
46
PD78C14G(A)-XXX-36
µ
PD2 PD1 PD0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 ALE WR RD AVDD VAREF AN7 AN6 AN5
PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
PC0/TxD
PC1/RxD
PC2/SCK
PC3/INT2
PC4/TO
PC5/CI
PC6/CO0 PC7/CO1
NMI
PD3 52
PD4 53
PD5 54
PD6 55
PD7 56
STOP 57
VDD 58
PA0 59
PA1 60
PA2 61
PA3 62
PA4 63
PA5 641 2 3 4 5 6 7 8 9 10111213141516 1718 19
515049484746454443 42414039 3837 36353433 AN4
AN3
AN2
AN1
AN0
AVSS
VSS
X1
X2
MODE0
RESET
MODE1
INT1
32
31
30
29
28
27
26
25
24
23
22
21
20
µ
PD78C14GF(A)-XXX-3BE
Pin Configuration (Top View)
*

µ PD78C14(A)
3
IC PA6 PA5 PA4 PA3 PA2 PA1 PA0 VDD STOP PD7 PD6 PD5 PD4 PD3 PD2 IC
PC7/CO1
NMI
INT1
MODE1
RESET
MODE0
X2 X1
VSS
AVSS
AN0 AN1 AN2 AN3 AN4 AN5 AN6
PA7 10
PB0 11
PB1 12
PB2 13
PB3 14
PB4 15
PB5 16
PB6 17
PB7 18
PC0/TxD 19
PC1/RxD 20
PC2/SCK 21
PC3/INT2 22
272829 30313233343536373839404142 43
987654321686766 6564636261 PD1
PD0
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
ALE
WR
RD
60
59
58
57
56
55
54
53
52
51
50
49
48
µ
PD78C14L(A)-XXX
IC 23
PC4/TO 24
PC5/CI 25
PC6/CO0 26
AVDD
47 IC
46 VAREF
45 AN7
44
*

4
µ
PD78C14(A)
Block Diagram
PF7-0/AB15-8
PD7-0/AD7-0
PC7-0
PB7-0
PA7-0
8
8
8
8
8
PORT A PORT B PORT C PORT D PORT F
8
8
8
8
8
8
8
8
8
16
16
6
8
16
14
16
16
16
16
8
8
8
8
8
8
8/16
8
INST.REG
INST.
DECODER
DATA
MEMORY
(256-BYTE)
PROGRAM
MEMORY
(16 K-BYTE)
MAIN
G.R
ALT
G.R
INTERNAL DATA BUS
ALU
(8/16)
PSWLATCHLATCH
8
STANDBY
CONTROL
SYSTEM
CONTROL
READ/WRITE
CONTROL
VSSVDD
STOPRESET MODE1 MODE0
ALE
WR
RD
LATCH
INC/DEC
PC
SP
EA
V
B
D
H
A
C
E
L
EA'
V'
B'
D'
H'
A'
C'
E'
L'
BUFFER
OSC
SERIAL I/O
INT.
CONTROL
TIMER
TIMER
EVENT
COUNTER
A/D
CONVERTER
X1
X2
PC0/TxD
PC1/RxD
PC2/SCK
NMI
INT1
PC3/INT2/TI
PC4/TO
PC5/CI
AVSS
PC7/CO1
PC6/CO0
AN7-0 8
VAREF
VDD
Note
Note DATA MEMORY can only be used when RAE bit of MM register is set to 1.
External memory is necessary when 0 is set.
4
*

µ PD78C14(A)
5
CONTENTS
1. DIFFERENCES BETWEEN µ PD78C14(A) AND µ PD78C14 ...................................................6
2. PIN FUNCTIONS ......................................................................................................................7
2.1 Pin Function List.........................................................................................................................7
2.2 Pin Input/Output Circuits ...........................................................................................................9
2.3 Recommended Connections for Unused Pins.......................................................................13
3. INSTRUCTION SET................................................................................................................14
3.1 Operand Expression Format/Description Method.................................................................14
3.2 Instruction Code Description ..................................................................................................16
3.3 Instruction Execution Time......................................................................................................17
4. LIST OF MODE REGISTERS .................................................................................................29
5. ELECTRICAL SPECIFICATIONS ..........................................................................................30
6. CHARACTERISTIC CURVES (reference value)...................................................................41
7. PACKAGE DRAWINGS .........................................................................................................44
8. RECOMMENDED SOLDERING CONDITIONS .....................................................................47
APPENDIX DEVELOPMENT TOOLS............................................................................................49
*

6
µ PD78C14(A)
1. DIFFERENCES BETWEEN µ PD78C14(A) AND µ PD78C14
Part number µ PD78C14(A) µ PD78C14
Item
Quality grade Special Standard
Electrical Input leakage current Input leakage current
specifications (AN7-0; ±1 µ A (MAX.) AN7-0; ±10 µ A (MAX.)
Package • 64-pin plastic QUIP • 64-pin plastic shrink DIP
• 64-pin plastic QFP • 64-pin plastic QUIP
(14 x 20 mm, thickness: 2.05 mm) • 64-pin plastic QUIP (straight)
• 68-pin plastic QFJ • 64-pin plastic QFP
(14 x 20 mm, thickness: 2.05 mm)
• 64-pin plastic QFP
(14 x 20 mm, thickness: 2.70 mm)
• 68-pin plastic QFJ
*

µ PD78C14(A)
7
2. PIN FUNCTIONS
2.1 Pin Function List
Pin Input/Output Function
PA7-PA0 Input/Output These 8 pins constitute an 8-bit I/O port and input/output can be specified in bit
(Port A) units.
PB7-PB0 Input/Output These 8 pins constitute an 8-bit I/O port and input/output can be specified in bit
(Port B) units.
PC0/TxD Input/Output, Port C Transmit Data
Output These 8 pins constitute an 8-bit I/O This pin outputs serial data.
PC1/RxD Input/Output, port and input/output can be specified Receive Data
Input in bit units. This pin inputs serial data.
PC2/SCK Input/Output, Serial Clock
Input/Output This pin inputs/outputs serial clock. It be-
comes an output pin when an internal
clock is used or an input pin when an
external clock is used.
PC3/INT2/TI Input/Output, Interrupt Request/Timer Input
Input, Input This pin inputs edge triggering (falling
edge) maskable interrupt or external
clock for timer. This pin is also shared
with zero-cross detection pin for AC input.
PC4/TO Input/Output, Timer Output
Output This pin outputs square waves in which
one cycle of the internal clock forms a
half cycle, indicating the timer’s counting
time.
PC5/CI Input/Output, Counter Input
Input This pin inputs external pulse for timer/
event counter.
PC6/CO0 Input/Output, Counter Output 0,1
PC7/CO1 Output This pin outputs programmable square
wave by timer/event counter.
PD7-PD0/ Input/Output, Port D Address/Data Bus
AD7-AD0 Input/Output These 8 pins constitute an 8-bit I/O These pins function as multiplexed
port and input/output can be address/data bus when using an
specified in byte units. external memory.
PF7-PF0/ Input/Output, Port F Address Bus
AB15-AB8 Output These 8 pins constitute an 8-bit I/O These pins function as address bus when
port and input/output can be specified using an external memory.
in bit units.
WR Output This is a strobe signal output to write data in external memory. This signal
(Write becomes high level except during the data write machine cycle for external memory.
Strobe) This signal becomes output high impedance when the RESET signal is low or in
the hardware STOP mode.
*

8
µ PD78C14(A)
(Continued)
Pin Input/Output Function
RD Output This is a strobe signal output to read data from external memory. This signal
(Read becomes high level except during the data read machine cycle for external memory.
Strobe) This signal becomes output high impedance when the RESET signal is low or in
the hardware STOP mode.
ALE Output This is a strobe signal to externally latch the low-order address information
(Address output to pins PD7-PD0 to access the external memory. This signal becomes
Latch output high impedance when the RESET signal is low or in the hardware STOP
Enable) mode.
MODE0 Input/Output Set the MODE0 pin to 0 (low level) and MODE1 pin to 1 (high level)Note.
MODE1 When both pins MODE0 and MODE1 are set to 1Note, these pins synchronize to
(Mode) the ALE and a control signal is output.
NMI Input This pin inputs the edge triggering (falling edge) nonmaskable interrupt.
(Non-
Maskable
Interrupt)
INT1 Input This pin inputs edge triggering (rising edge) maskable interrupt. This pin is also
(Interrupt shared with zero-cross detection pin for AC input.
Request)
AN7-AN0 Input These eight pins input analog signals for the A/D converter. Pins AN7-AN4 can
(Analog be used as edge detection (falling edge) input.
Input)
VAREF Input This pin inputs the reference voltage for the A/D converter and controls the
(Reference operation for the A/D converter.
Voltage)
AVDD Power supply pin for the A/D converter
(Analog
VDD)
AVSS Ground pin for the A/D converter
(Analog
VSS)
X1, X2 These are crystal connecting pins for the system clock oscillation. When a clock
(Crystal) is externally supplied, input it through pin X1. Input the clock to X1 and its reverse
phase to X2.
RESET Input This pin inputs the active-low reset input signal.
(Reset)
STOP Input This pin inputs control signal of the hardware STOP mode. When the low level
(Stop) of this signal is input, the oscillator stops to operate.
VDD Positive power supply pin
VSS Ground pin
Note Pull-up with the following external resistor:
4 (kΩ) ≤R ≤0.4 tCYC (kΩ)tCYC (unit: ns)
Example 4 (kΩ) ≤R ≤26 (kΩ): tCYC = 66 (ns) at 15 MHz
4 (kΩ) ≤R ≤33 (kΩ): tCYC = 83 (ns) at 12 MHz
*

µ PD78C14(A)
9
2.2 Pin Input/Output Circuits
Schematic input/output circuits of the pins are shown in Table 2-1 and figures from (1) to (11).
Table 2-1. Name of Type No.
Pin Type No. Pin Type No.
PA0-7 5 RESET 2
PB0-7 5 RD 4
PC0-1 5 WR 4
PC2/SCK 8 ALE 4
PC3/INT2 10 STOP 2
PC4-7 5 MODE0 11
PD0-7 5 MODE1 11
PF0-7 5 AN0-3 7
NMI 2 AN4-7 12
INT1 9 VAREF 13
*

10
µ PD78C14(A)
Type 4 IN/OUT
output data
output disable
Type 1
IN
P-ch
VDD
OUT
N-ch
output data
output disable
N-ch
P-ch
VDD
IN
(1) Type 1
(2) Type 2
(3) Type 4
(4) Type 5
*

µ PD78C14(A)
11
IN/OUT
Type 5
Type 9
N-ch
N-ch
MCC
output data
output disable
self bias
enable
IN/OUT
Type 5
Type 2
output data
output disable
N-ch
N-ch
MCC
+
–
AVSS
AVDD
AVSS
AVDD
IN P-ch
N-ch
sampling
C
reference voltage
(from voltage tap of serial resistor string)
(5) Type 7
(6) Type 8
(7) Type 9
(8) Type 10
IN
Type 1
self bias
enable
data
*

12
µ PD78C14(A)
Type 1
IN
AVSS
STOP Mode P-ch
(9) Type 11
(10) Type 12
(11) Type 13
Type 7
Type 2
IN
edge detection circuit
output data
Type 1
N-ch
IN/OUT
*

µ PD78C14(A)
13
2.3 Recommended Connections for Unused Pins
Pin Recommended connection
PA7-0
PB7-0
PC7-0 Connect to VDD or VSS via resistor.
PD7-0
PF7-0
RD
WR Leave unconnected.
ALE
STOP VDD
INT1, NMI Connect to VDD or VSS.
AVDD Connect to VDD.
VAREF Connect to VSS.
AVSS
AN7-0 Connect to AVSS or AVDD.
*

14
µ PD78C14(A)
3. INSTRUCTION SET
3.1 Operand Expression Format/Description Method
Expression format Description method
r V, A, B, C, D, E, H, L
r1 EAH, EAL, B, C, D, E, H, L
r2 A, B, C
sr PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, SML, EOM, ETMM, TMM, MM, MCC, MA, MB,
MC, MF, TXB, TM0, TM1, ZCM
sr1 PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB, CR0, CR1, CR2, CR3
sr2 PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM
sr3 ETM0, ETM1
sr4 ECNT, ECPT
rp SP, B, D, H
rp1 V, B, D, H, EA
rp2 SP, B, D, H, EA
rp3 B, D, H
rpa B, D, H, D+, H+, D–, H–
rpa1 B, D, H
rpa2 B, D, H, D+, H+, D–, H–, D+byte, H+A, H+B, H+EA, H+byte
rpa3 D, H, D++, H++, D+byte, H+A, H+B, H+EA, H+byte
wa 8-bit immediate data
word 16-bit immediate data
byte 8-bit immediate data
bit 3-bit immediate data
f CY, HC, Z
irf NMI Note, FT0, FT1, F1, F2, FE0, FE1, FEIN, FAD, FSR, FST, ER, OV, AN4, AN5, AN6, AN7,
SB
Note NMI can be also described as FNMI.
*

µ PD78C14(A)
15
Remarks
1. sr to sr4 (special register) 2. rp to rp3 (register pair) 4. f (flag)
PA : PORT A ETMM : TIMER/EVENT SP : STACK POINTER CY : CARRY
PB : PORT B COUNTER MODE B : BC HC : HALF CARRY
PC : PORT C EOM : TIMER/EVENT D : DE Z : ZERO
PD : PORT D COUNTER OUTPUT H : HL
PF : PORT F MODE V : VA 5. irf (interrupt flag)
MA : MODE A ANM : A/D CHANNEL MODE EA : EXTENDED NMI : NMI INPUT
MB : MODE B CR0 : A/D CONVERSION ACCUMULATOR FT0 : INTFT0
MC : MODE C to RESULT 0 to 3 FT1 : INTFT1
MCC : MODE CONTROL C CR3 3. rpa to rpa3 (rp addressing) F1 : INTF1
MF : MODE F TXB : Tx BUFFER B : (BC) F2 : INTF2
MM : MEMORY MAPPING RXB : Rx BUFFER D : (DE) FE0 : INTFE0
TM0 : TIMER REG0 SMH : SERIAL MODE High H : (HL) FE1 : INTFE1
TM1 : TIMER REG1 SML : SERIAL MODE Low D+ : (DE)+ FEIN: INTFEIN
TMM : TIMER MODE MKH : MASK High H+ : (HL)+ FAD : INTFAD
ETM0 : TIMER/EVENT MKL : MASK Low D– : (DE)– FSR : INTFSR
COUNTER REG0 ZCM : ZERO CROSS MODE H– : (HL)– FST : INTFST
ETM1 : TIMER/EVENT D++ : (DE)++ ER : ERROR
COUNTER REG1 H++ : (HL)++ OV : OVERFLOW
ECNT : TIMER/EVENT D+byte: (DE+byte) AN4 : ANALOG INPUT
COUNTER UPCOUNTER H+A : (HL+A) to 4 to 7
ECPT : TIMER/EVENT H+B : (HL+B) AN7
COUNTER CAPTURE H+EA : (HL+EA) SB : STANDBY
H+byte: (HL+byte)
*

16
µ PD78C14(A)
r
R2R1R0reg
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
V
A
B
C
D
E
H
L
r1
T2T1T0reg
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
EAH
EAL
B
C
D
E
H
L
rpa
A3A2A1addressing
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
0
1
1
(BC)
(DE)
(HL)
(DE)+
(HL)+
(DE)–
(HL)–
(DE+byte)
(HL+A)
(HL+B)
(HL+EA)
(HL+byte)
A0
0
1
0
1
0
1
0
1
1
0
1
0
1
rpa
rpa1
rpa2
r2
sr
S5S4S3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
S2
0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
Special-reg
PA
PB
PC
PD
PF
MKH
MKL
ANM
SMH
SML
EOM
ETMM
TMM
MM
MCC
MA
MB
MC
MF
TXB
RXB
TM0
TM1
CR0
CR1
CR2
CR3
ZCM
S1
0
0
1
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0
S0
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
sr1 sr2
r
rpa3
C3C2C1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
1
1
0
0
1
0
0
1
1
C0
0
1
0
1
1
0
1
0
1
addressing
(DE)
(HL)
(DE)++
(HL)++
(DE+byte)
(HL+A)
(HL+B)
(HL+EA)
(HL+byte)
irf
I3I2I1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
I0
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
INTF
NMI
FT0
FT1
F1
F2
FE0
FE1
FEIN
FAD
FSR
FST
ER
OV
AN4
AN5
AN6
AN7
SB
I4
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
sr3
U0
0
1
Special-reg
ETM0
ETM1
sr4
V0
0
1
Special-reg
ECNT
ECPT
P2P1P0reg-pair
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
SP
BC
DE
HL
EA
rp
Q2Q1Q0reg-pair
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
VA
BC
DE
HL
EA
rp1
F2F1F0flag
0
0
0
1
0
1
1
0
0
0
1
0
—
CY
HC
Z
f
rp rp2 rp3
sr
3.2 Instruction Code Description
*

µ PD78C14(A)
17
3.3 Instruction Execution Time
Inthefollowingtable,onestateconsistsofthreeclockcycles. So,whenthe15MHzclockisused,onestatebecomes
200 ns (= 3 x 1/15
µ s). Execution time of the 4-state instruction, the shortest instruction, becomes 0.8 µ s.
*

18
µ
PD78C14(A)
Instruc- tion group
Instruction code
Mnemonic Operand State Operation
Skip
condition
B1 B2 B3 B4
r1, A 0 0 0 1 1 T
2 T 1 T 0 4r1 ←A
A, r1 0 0 0 0 1 T
2 T 1 T 0 4A←r1
*
*
1 1 S
5 S 4 S 3 S 2 S 1 S 0
sr, A 0 1 0 0 1 1 0 1 10 sr ←A
MOV A, sr1
r, word
word, r
1 1 S
5 S 4 S 3 S 2 S 1 S 0
0 1 0 0 1 1 0 0
0 1 1 0 1 R
2 R 1 R 0
0 1 1 1 0 0 0 0
0 1 1 1 1 R
2 R 1 R 0
0 1 1 1 0 0 0 0
Data
Low Adrs
Low Adrs
High Adrs
High Adrs
10 A←sr1
17 r←(word)
17 (word) ←r
8-bit data transfer
16-bit data transfer
MVI
MVIW
MVIX
STAW
LDAW
STAX
LDAX
EXX
EXA
EXH
BLOCK
DMOV
*
*
*
*
*
*
*
r, byte 0 1 1 0 1 R
2 R 1 R 0
sr2, byte 0 1 1 0 0 1 0 0
wa, byte 0 1 1 1 0 0 0 1
rpa1, byte 0 1 0 0 1 0 A
1 A 0
0 1 1 0 0 0 1 1
wa
0 0 0 0 0 0 0 1
wa
A
3 0 1 1 1 A 2 A 1 A 0
rpa2
A
3 0 1 0 1 A 2 A 1 A 0
rpa2
0 0 0 1 0 0 0 1
0 0 0 1 0 0 0 0
0 1 0 1 0 0 0 0
0 0 1 1 0 0 0 1
1 0 1 1 0 1 P
1 P 0
1 0 1 0 0 1 P 1 P 0
S 3 0 0 0 0 S 2 S 1 S 0
Offset
Data
Offset
Offset
Data
Data
Note 1
Note 1
Data
Data
7
14
13
10
10
10
7/13
7/13
4
4
4
13
(C+1)
4
4
Note 3
Note 3
r←byte
sr2 ←byte
(V. wa) ←byte
(rpa1) ←byte
(V. wa) ←A
A←(V. wa)
(rpa2) ←A
A←(rpa2)
B↔B', C ↔C', D ↔D'
E↔E', H ↔H', L ↔L'
V, A ↔V', A', EA ↔EA'
H, L ↔H', L'
(DE)+←(HL)+, C←C–1
End if borrow
rp3
L ←EAL, rp3 H ←EAH
EAL ←rp3
L , EAH ←rp3 H
{
rp3, EA
EA, rp3
*

µ
PD78C14(A)
19
Instruc- tion group
Instruction code
Mnemonic Operand State Operation
Skip
condition
B1 B2 B3 B4
sr3, EA 0 1 0 0 1 0 0 0 14 sr3 ←EA
EA, sr4 1 1 0 0 0 0 0 V
0 14 EA ←sr4
0 0 0 1 1 1 1 0
word 0 1 1 1 0 0 0 0 20 (word) ←C, (word+1) ←B
SBCD
word
word
word
0 0 1 0 1 1 1 0
0 0 1 1 1 1 1 0
0 0 0 0 1 1 1 0
Low Adrs High Adrs
20 (word) ←E, (word+1) ←D
20 (word) ←L, (word+1) ←H
20 (word) ←SP
L , (word+1) ←SP H
16-bit data transfer
8-bit arithmetic operation (register)
STEAX
LDED
LHLD
LSPD
LDEAX
PUSH
POP
LXI
TABLE
ADD
ADC
*
rpa3 0 1 0 0 1 0 0 0
word 0 1 1 1 0 0 0 0
word
word
word
0 1 0 0 1 0 0 0
rpa3
1 0 1 1 0 Q
2 Q 1 Q 0
rp1
1 0 1 0 0 Q
2 Q 1 Q 0
rp1
0 P
2 P 1 P 0 0 1 0 0
0 1 0 0 1 0 0 0
0 1 1 0 0 0 0 0
0 1 0 0
1 1 0 1
0 1 0 1
0 0 0 1 1 1 1 1
Low Byte
Data 14/20
20
20
20
20
14/20
13
10
10
17
8
8
8
8
Note 3
(rpa3) ←EAL, (rpa3+1) ←EAH
C←(word), B ←(word+1)
E←(word), D ←(word+1)
L←(word), H ←(word+1)
SP
L ←(word), SP H ←(word+1)
EAL ←(rpa3), EAH ←(rpa3+1)
(SP–1)←rp1
H , (SP–2)←rp1 L
SP ←SP–2
rp1 L ←(SP), rp1 H ←(SP+1)
SP ←SP+2
rp2 ←word
C←(PC+3+A)
B←(PC+3+A+1)
A←A+r
r←r+A
A←A+r+CY
r←r+A+CY
DMOV
SDED
SHLD
SSPD
LBCD
rp2, word
A, r
r, A
A, r
r, A
1 1 0 1 0 0 1 U
0
1 1 0 0 0 R 2 R 1 R 0
1 0 1 0 1 0 0 0
1 0 0 0 C
3 C 2 C 1 C 0
0 0 1 0 1 1 1 1
0 0 1 1 1 1 1 1
0 0 0 0 1 1 1 1
1 0 0 1 C
3 C 2 C 1 C 0Note 2
Low Adrs
Data
Note 2
High Adrs
High Byte
Note 3
*

20
µ
PD78C14(A)
Instruc- tion group
Instruction code
Mnemonic Operand State Operation
Skip
condition
B1 B2 B3 B4
A, r 0 1 1 0 0 0 0 0 8 A←A+r
r, A 0 0 1 0 8 r←r+A
1 1 1 0
A, r 8A←A–r
r, A
A, r
r, A
0 1 1 0
1 1 1 1
0 1 1 1
8r←r–A
8A←A–r–CY
8r←r–A–CY
8-bit arithmetic operation (register)
ANA
ORA
XRA
GTA
LTA
NEA
A, r
r, A
A, r
r, A
A, r
r, A
1 0 0 1 0 R
2 R 1 R 0
A, r
0 0 0 1
r, A
0 0 1 1
1 1 1 0
0 1 1 0
0 0 1 1
8
8
8
8
8
8
8
8
8
8
8
8
8
8
A←A–r
r←r–A
A←A r
r←r A
A←A r
r←r A
A←A r
r←r A
A–r–1
r–A–1
A–r
r–A
A–r
r–A
ADDNC
SUB
SBB
SUBNB
A, r
A, r
r, A
A, r
r, A
1 0 1 0 0 R
2 R 1 R 0
1 0 1 1
0 0 1 0
0 0 0 1
1 0 0 0 1 R
2 R 1 R 0
0 0 0 0
1 0 0 1
1 0 1 1
1 0 1 0 1 R 2 R 1 R 0
No Zero
r, A
<<>>>>
No Zero
Borrow
Borrow
No
Borrow
No
Borrow
No
Borrow
No
Carry
No
Carry
No
Borrow
*