NEC mPD789101 User manual

User’s Manual
Printed in Japan
©
8-bit Single-chip Microcontrollers
µ PD789101 µ PD789121
µ PD789102 µ PD789122
µ PD789104 µ PD789124
µ PD789111 µ PD789131
µ PD789112 µ PD789132
µ PD789114 µ PD789134
µ PD78F9116 µ PD78F9136
Document No. U13045EJ2V0UM00 (2nd edition)
Date Published July 1999 N CP(K)
1998
µ PD789104, 789114, 789124,
789134 Subseries

2User’s Manual U13045EJ2V0UM00
[MEMO]

User’s Manual U13045EJ2V0UM00 3
EEPROM is a trademark of NEC Corporation.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in
the United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun-Microsystems, Inc.
OSF/Motif is a trademark of Open Software Foundation, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
TRON is an abbreviation of The Realtime Operating System Nucleus.
ITRON is an abbreviation of Industrial TRON.
1
NOTES FOR CMOS DEVICES
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimatelydegradethedeviceoperation. Stepsmustbetakentostopgenerationofstaticelectricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulatorsthateasilybuildstaticelectricity. Semiconductordevicesmustbestoredandtransported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wriststrap. Semiconductordevicesmustnotbetouchedwithbarehands. Similar precautionsneed
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
totheinputpins, it is possible that aninternalinputlevelmaybegenerated due to noise, etc., hence
causingmalfunction. CMOSdevicesbehave differentlythanBipolarorNMOS devices. Inputlevels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

4User’s Manual U13045EJ2V0UM00
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
Licence not needed: µ PD78F9116, 78F9136
The customer must judge the need for license:
µ PD789101, 789102, 789104
µ PD789111, 789112, 789114
µ PD789121, 789122, 789124
µ PD789131, 789132, 789134
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7D 98.12

User’s Manual U13045EJ2V0UM00 5
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
Device availability
•
Ordering information
•
Product release schedule
•
Availability of related technical literature
•
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: [phone]
800-366-9782
Fax: [phone]
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: [phone]
Fax: [phone]
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: [phone]
Fax: [phone]
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: [phone]
Fax: [phone]
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: [phone]
Fax: [phone]
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: [phone]
Fax: [phone]
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: [phone]
Fax: [phone]
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: [phone]
Fax: [phone]
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: [phone]
Fax: [phone]
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: [phone]
Fax: [phone]
J99.1

6User’s Manual U13045EJ2V0UM00
Major Revisions in This Edition
Page Description
Throughout Deletion of 28-pin plastic shrink DIP
Addition of 30-pin plastic shrink DIP in the “in planning“ status
Deletion of description “under development” from mask ROM versions and the µ PD78F9116
Addition of MC-5A4 type to the packages
Modification of the minimum power-supply voltage from 1.8 V to 2.7 V
p. 44 Modification of Table 3-1 Types of Pin I/O Circuits and Recommended Connection of Unused Pins
p. 81 Addition of caution when using port 5 as an input pin to 5.2.4 Port 5
pp. 95 to 101 Modification of system clock oscillation frequency to 2.0 to 4.0 MHz in CHAPTER 7 CLOCK GENERATOR
( µ PD789124, 789134 SUBSERIES)
p. 110 Addition of caution regarding rewrite of CR20 in section 8.4.1 Operation as timer interrupt
p. 117 Addition of caution regarding rewrite of CR80 in section 9.2 (1) 8-bit compare register 80 (CR80)
p. 120 Addition of explanation regarding settings in section 9.4.1 Operation as interval timer
p. 122 Addition of explanation regarding settings in section 9.4.2 Operation as external event counter
p. 123 Addition of explanation regarding settings in section 9.4.3 Operation as square wave output
p. 125 Addition of explanation regarding settings in section 9.4.4 Operation as PWM output
p. 170 Modification enabling 1-bit memory manipulation instruction in 13.3 (3) Asynchronous serial interface
status register 20 (ASIS20)
p. 235 Addition of 18.1.3 (b) Connection between µ PD78F9136 and Flashpro III
p. 237 Addition of 18.1.4 Example of settings for Flashpro III (PG-FP3)
p. 251 APPENDIX A DEVELOPMENT TOOLS
Revised throughout: supporting IE-78K0S-NS
p. 257 Addition of MX78K0S part number to APPENDIX B EMBEDDED SOFTWARE
p. 263 Addition of APPENDIX D REVISION HISTORY
The mark shows major revised points.

7User’s Manual U13045EJ2V0UM00
INTRODUCTION
Target Readers This manual is intended for users who wish to understand the functions of the
µ PD789104,789114,789124,789134Subseriesandtodesignanddevelopapplication
systems and programs using these microcontrollers.
The target devices are shown as follows:
•
µ PD789104 Subseries: µ PD789101, 789102, 789104
•
µ PD789114 Subseries: µ PD789111, 789112, 789114, 78F9116
•
µ PD789124 Subseries: µ PD789121, 789122, 789124
•
µ PD789134 Subseries: µ PD789131, 789132, 789134, 78F9136
Unlessotherwisespecified,the
µ PD789134Subseriesistreatedastherepresentative
product in this manual.
The oscillation frequency of the system clock is regarded as fXfor ceramic/crystal
oscillation (
µ PD789104 and 789114 Subseries), and regarded as fCC for an RC
oscillation (
µ PD789124 and 789134 Subseries).
Purpose This manual is intended for users to understand the functions described in the
organization below.
Organization The
µ PD789104, 789114, 789124, 789134 Subseries User's Manual is divided into
two parts: this manual and instructions (common to the 78K/0S Series).
µ PD789104, 789114, 789124, 78K/0S Series
789134 Subseries User’s Manual
User’s Manual (This manual) Instructions
• Pin functions • CPU function
• Internal block functions • Instruction set
• Interrupt • Instruction description
• Other internal peripheral functions
How to Read This Manual It is assumed that the readers of this manual have general knowledge in the fields
of electrical engineering, logic circuits, and microcontrollers.
To understand the overall functions of the µ PD789104, 789114, 789124, 789134
Subseries
→Read this manual in the order of the CONTENTS.
How to interpret register formats
→The name of a bit whose number is encircled is reserved for the assembler and
is defined for the C compiler by the header file sfrbit.h.
To learn the detailed functions of a register whose register name is known
→Refer to APPENDIX C REGISTER INDEX.
To learn the details of the instruction functions of the 78K/0S Series
→Refer to 78K/0S Series User’s Manual Instructions (U11047E).

8User’s Manual U13045EJ2V0UM00
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representation: ××× (overscore over pin or signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representation: Binary ... ×××× or ××××B
Decimal ... ××××
Hexadecimal ... ××××H
Related Documents Therelateddocumentsindicatedinthispublicationmayincludepreliminaryversions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
English Japanese
µ PD789101, 789102, 789104 Preliminary Product Information U12815E U12815J
µ PD789111, 789112, 789114 Preliminary Product Information U13013E U13013J
µ PD789121, 789122, 789124 Preliminary Product Information U13025E U13025J
µ PD789131, 789132, 789134 Preliminary Product Information U13015E U13015J
µ PD78F9116 Preliminary Product Information U13037E U13037J
µ PD78F9136 Preliminary Product Information U13036E U13036J
µ PD789104, 789114, 789124, 789134 Subseries User’s Manual This manual U13045J
78K/0S Series User’s Manual Instruction U11047E U11047J
Documents Related to Development Tools (User’s Manuals)
Document Name Document No.
English Japanese
RA78K0S Assembler Package Operation U11622E U11622J
Assembly Language U11599E U11599J
Structured Assembly Language U11623E U11623J
CC78K0S C Compiler Operation U11816E U11816J
Language U11817E U11817J
SM78K0S System Simulator WindowsTM Based Reference U11489E U11489J
SM78K Series System Simulator External components user open U10092E U10092J
interface specification
ID78K0S-NS Integrated Debugger Reference U12901E U12901J
Windows Based
IE-78K0S-NS In-Circuit Emulator U13549E U13549J
IE-789136-NS-EM1 Emulation Board To be prepared To be prepared
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.

9User’s Manual U13045EJ2V0UM00
Document Related to Embedded Software (User’s Manual)
Document Name Document No.
English Japanese
78K/0S Series OS MX78K0S Basics To be prepared U12938J
Other Documents
Document Name Document No.
English Japanese
SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) X13769X
Semiconductor Device Mounting Technology Manual C10535E C10535J
Quality Grades on NEC Semiconductor Devices C11531E C11531J
NEC Semiconductor Device Reliability/Quality Control System C10983E C10983J
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E C11892J
Guide to Microcomputer-Related Products by Third Party U11416J
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.

10 User’s Manual U13045EJ2V0UM00
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User’s Manual U13045EJ2V0UM00 11
CONTENTS
CHAPTER 1 GENERAL ( µ PD789104, 789114 SUBSERIES)........................................................ 23
1.1 Features............................................................................................................................... 23
1.2 Applications ........................................................................................................................ 23
1.3 Ordering Information ......................................................................................................... 24
1.4 Pin Configuration (Top View) ........................................................................................... 25
1.5 78K/0S Series Lineup ........................................................................................................ 27
1.6 Block Diagram .................................................................................................................... 29
1.7 Outline of Functions.......................................................................................................... 30
CHAPTER 2 GENERAL ( µ PD789124, 789134 SUBSERIES)........................................................ 31
2.1 Features............................................................................................................................... 31
2.2 Applications ........................................................................................................................ 31
2.3 Ordering Information ......................................................................................................... 32
2.4 Pin Configuration (Top View) ........................................................................................... 33
2.5 78K/0S Series Lineup ........................................................................................................ 35
2.6 Block Diagram .................................................................................................................... 37
2.7 Outline of Functions.......................................................................................................... 38
CHAPTER 3 PIN FUNCTIONS ......................................................................................................... 39
3.1 Pin Function List................................................................................................................ 39
3.2 Description of Pin Functions ........................................................................................... 41
3.2.1 P00 to P03 (Port 0) .................................................................................................................. 41
3.2.2 P10, P11 (Port 1)...................................................................................................................... 41
3.2.3 P20 to P25 (Port 2) .................................................................................................................. 41
3.2.4 P50 to P53 (Port 5) .................................................................................................................. 42
3.2.5 P60 to P63 (Port 6) .................................................................................................................. 42
3.2.6 RESET ...................................................................................................................................... 42
3.2.7 X1, X2 (
µ PD789104, 789114 Subseries) ................................................................................ 42
3.2.8 CL1, CL2 (
µ PD789124, 789134 Subseries) ........................................................................... 42
3.2.9 AVDD ............................................................................................................................................................................................................... 42
3.2.10 AVSS ............................................................................................................................................................................................................. 42
3.2.11 VDD................................................................................................................................................................................................................ 42
3.2.12 VSS ................................................................................................................................................................................................................ 42
3.2.13 VPP (
µ PD78F9116, 78F9136 only) ......................................................................................... 43
3.2.14 IC0 (pin No.20) (mask ROM version only)............................................................................ 43
3.2.15 IC0 (pins No.10 and No.21)................................................................................................... 43
3.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ............. 44
CHAPTER 4 CPU ARCHITECTURE ................................................................................................ 47
4.1 Memory Space .................................................................................................................... 47
4.1.1 Internal program memory space.............................................................................................. 51
4.1.2 Internal data memory (internal high-speed RAM) space........................................................ 52
4.1.3 Special function register (SFR) area ....................................................................................... 52
4.1.4 Data memory addressing......................................................................................................... 52
4.2 Processor Registers .......................................................................................................... 56

User’s Manual U13045EJ2V0UM00
12
4.2.1 Control registers ....................................................................................................................... 56
4.2.2 General registers...................................................................................................................... 59
4.2.3 Special function registers (SFRs)............................................................................................ 60
4.3 Instruction Address Addressing ...................................................................................... 63
4.3.1 Relative addressing.................................................................................................................. 63
4.3.2 Immediate addressing.............................................................................................................. 64
4.3.3 Table indirect addressing ......................................................................................................... 65
4.3.4 Register addressing ................................................................................................................. 65
4.4 Operand Address Addressing.......................................................................................... 66
4.4.1 Direct addressing ..................................................................................................................... 66
4.4.2 Short direct addressing ............................................................................................................ 67
4.4.3 Special function register (SFR) addressing ............................................................................ 68
4.4.4 Register addressing ................................................................................................................. 69
4.4.5 Register indirect addressing .................................................................................................... 70
4.4.6 Based addressing..................................................................................................................... 71
4.4.7 Stack addressing...................................................................................................................... 71
CHAPTER 5 PORT FUNCTIONS..................................................................................................... 73
5.1 Functions of Ports ............................................................................................................. 73
5.2 Port Configuration ............................................................................................................. 75
5.2.1 Port 0 ........................................................................................................................................ 75
5.2.2 Port 1 ........................................................................................................................................ 76
5.2.3 Port 2 ........................................................................................................................................ 77
5.2.4 Port 5 ........................................................................................................................................ 81
5.2.5 Port 6 ........................................................................................................................................ 82
5.3 Port Function Control Registers...................................................................................... 83
5.4 Operation of Port Functions............................................................................................. 85
5.4.1 Writing to I/O port ..................................................................................................................... 85
5.4.2 Reading from I/O port .............................................................................................................. 85
5.4.3 Arithmetic operation of I/O port................................................................................................ 85
CHAPTER 6 CLOCK GENERATOR ( µ PD789104, 789114 SUBSERIES)..................................... 87
6.1 Function of Clock Generator............................................................................................ 87
6.2 Configuration of Clock Generator ................................................................................... 87
6.3 Register Controlling Clock Generator ............................................................................ 88
6.4 System Clock Oscillator.................................................................................................... 89
6.4.1 System clock oscillator............................................................................................................. 89
6.4.2 Divider....................................................................................................................................... 92
6.5 Operation of Clock Generator .......................................................................................... 92
6.6 Changing Setting of CPU Clock....................................................................................... 93
6.6.1 Time required for switching CPU clock ................................................................................... 93
6.6.2 Switching CPU clock ................................................................................................................ 93
CHAPTER 7 CLOCK GENERATOR ( µ PD789124, 789134 SUBSERIES) .................................... 95
7.1 Function of Clock Generator............................................................................................ 95
7.2 Configuration of Clock Generator ................................................................................... 95
7.3 Register Controlling Clock Generator ............................................................................ 96

User’s Manual U13045EJ2V0UM00 13
7.4 System Clock Oscillator.................................................................................................... 97
7.4.1 System clock oscillator............................................................................................................. 97
7.4.2 Divider....................................................................................................................................... 100
7.5 Operation of Clock Generator .......................................................................................... 100
7.6 Changing Setting of CPU Clock....................................................................................... 101
7.6.1 Time required for switching CPU clock ................................................................................... 101
7.6.2 Switching CPU clock ................................................................................................................ 101
CHAPTER 8 16-BIT TIMER COUNTER............................................................................................ 103
8.1 16-Bit Timer Counter Functions....................................................................................... 104
8.2 16-Bit Timer Counter Configuration ................................................................................ 105
8.3 Registers Controlling 16-Bit Timer Counter .................................................................. 107
8.4 16-Bit Timer Counter Operation....................................................................................... 110
8.4.1 Operation as timer interrupt..................................................................................................... 110
8.4.2 Operation as timer output ........................................................................................................ 112
8.4.3 Capture operation..................................................................................................................... 113
8.4.4 16-bit timer register 20 readout ............................................................................................... 114
CHAPTER 9 8-BIT TIMER/EVENT COUNTER ............................................................................... 115
9.1 Functions of 8-Bit Timer/Event Counter......................................................................... 115
9.2 8-Bit Timer/Event Counter Configuration....................................................................... 116
9.3 8-Bit Timer/Event Counter Control Registers ................................................................ 118
9.4 Operation of 8-Bit Timer/Event Counter ......................................................................... 120
9.4.1 Operation as interval timer....................................................................................................... 120
9.4.2 Operation as external event counter ....................................................................................... 122
9.4.3 Operation as square wave output ........................................................................................... 123
9.4.4 Operation as PWM output........................................................................................................ 125
9.5 Notes on Using 8-Bit Timer/Event Counter.................................................................... 127
CHAPTER 10 WATCHDOG TIMER.................................................................................................. 129
10.1 Functions of Watchdog Timer........................................................................................ 129
10.2 Configuration of Watchdog Timer ................................................................................. 130
10.3 Watchdog Timer Control Register ................................................................................. 131
10.4 Operation of Watchdog Timer........................................................................................ 133
10.4.1 Operation as watchdog timer................................................................................................. 133
10.4.2 Operation as interval timer .................................................................................................... 134
CHAPTER 11 8-BIT A/D CONVERTER ( µ PD789104, 789124 SUBSERIES) ............................... 135
11.1 8-Bit A/D Converter Functions ....................................................................................... 135
11.2 8-Bit A/D Converter Configuration................................................................................. 135
11.3 Registers Controlling 8-Bit A/D Converter ................................................................... 138
11.4 8-Bit A/D Converter Operation ....................................................................................... 140
11.4.1 Basic operation of 8-bit A/D converter................................................................................... 140
11.4.2 Input voltage and conversion result....................................................................................... 141
11.4.3 Operation mode of 8-bit A/D converter.................................................................................. 143
11.5 Cautions Related to 8-Bit A/D Converter ...................................................................... 144

User’s Manual U13045EJ2V0UM00
14
CHAPTER 12 10-BIT A/D CONVERTER ( µ PD789114, 789134 SUBSERIES) ............................. 149
12.1 10-Bit A/D Converter Functions..................................................................................... 149
12.2 10-Bit A/D Converter Configuration .............................................................................. 149
12.3 Registers Controlling 10-Bit A/D Converter................................................................. 152
12.4 10-Bit A/D Converter Operation ..................................................................................... 154
12.4.1 Basic operation of 10-bit A/D converter ................................................................................ 154
12.4.2 Input voltage and conversion result ...................................................................................... 155
12.4.3 Operation mode of 10-bit A/D converter ............................................................................... 157
12.5 Cautions Related to 10-Bit A/D Converter.................................................................... 158
CHAPTER 13 SERIAL INTERFACE 20 ........................................................................................... 163
13.1 Functions of Serial Interface 20..................................................................................... 163
13.2 Serial Interface 20 Configuration................................................................................... 163
13.3 Serial Interface 20 Control Registers............................................................................. 167
13.4 Serial Interface 20 Operation ......................................................................................... 174
13.4.1 Operation stop mode.............................................................................................................. 174
13.4.2 Asynchronous serial interface (UART) mode........................................................................ 176
13.4.3 3-wire serial I/O mode............................................................................................................ 189
CHAPTER 14 MULTIPLIER.............................................................................................................. 199
14.1 Multiplier Function........................................................................................................... 199
14.2 Multiplier Configuration .................................................................................................. 199
14.3 Multiplier Control Register ............................................................................................. 201
14.4 Multiplier Operation ......................................................................................................... 202
CHAPTER 15 INTERRUPT FUNCTIONS ........................................................................................ 203
15.1 Interrupt Function Types................................................................................................. 203
15.2 Interrupt Sources and Configuration ............................................................................ 203
15.3 Interrupt Function Control Registers............................................................................ 206
15.4 Interrupt Processing Operation ..................................................................................... 211
15.4.1 Non-maskable interrupt request acknowledgement operation............................................. 211
15.4.2 Maskable interrupt request acknowledgement operation..................................................... 213
15.4.3 Multiple interrupt processing.................................................................................................. 215
15.4.4 Interrupt request reserve ....................................................................................................... 217
CHAPTER 16 STANDBY FUNCTION .............................................................................................. 219
16.1 Standby Function and Configuration............................................................................ 219
16.1.1 Standby function..................................................................................................................... 219
16.1.2 Standby function control register (
µ PD789104, 789114 Subseries).................................... 220
16.2 Operation of Standby Function...................................................................................... 221
16.2.1 HALT mode ............................................................................................................................. 221
16.2.2 STOP mode ............................................................................................................................ 224
CHAPTER 17 RESET FUNCTION ................................................................................................... 227
CHAPTER 18 µ PD78F9116, 78F9136 ............................................................................................. 231
18.1 Flash Memory Programming .......................................................................................... 232

User’s Manual U13045EJ2V0UM00 15
18.1.1 Selecting communication mode............................................................................................. 232
18.1.2 Function of flash memory programming................................................................................ 233
18.1.3 Flashpro III connection example ........................................................................................... 233
18.1.4 Example of settings for Flashpro III (PG-FP3)....................................................................... 237
CHAPTER 19 MASK OPTION (MASK ROM VERSION) ................................................................ 239
CHAPTER 20 INSTRUCTION SET .................................................................................................. 241
20.1 Operation........................................................................................................................... 241
20.1.1 Operand identifiers and description methods ....................................................................... 241
20.1.2 Description of “operation” column ......................................................................................... 242
20.1.3 Description of “flag operation” column .................................................................................. 242
20.2 Operation List................................................................................................................... 243
20.3 Instructions Listed by Addressing Type....................................................................... 248
APPENDIX A DEVELOPMENT TOOLS........................................................................................... 251
A.1 Language Processing Software ...................................................................................... 253
A.2 Flash Memory Writing Tools ............................................................................................ 254
A.3 Debugging Tools................................................................................................................ 254
A.3.1 Hardware .................................................................................................................................. 254
A.3.2 Software ................................................................................................................................... 255
APPENDIX B EMBEDDED SOFTWARE ......................................................................................... 257
APPENDIX C REGISTER INDEX ...................................................................................................... 259
C.1 Register Name Index (Alphabetic Order) ....................................................................... 259
C.2 Register Symbol Index (Alphabetic Order).................................................................... 261
APPENDIX D REVISION HISTORY ................................................................................................. 263

User’s Manual U13045EJ2V0UM00
16
[MEMO]

User’s Manual U13045EJ2V0UM00 17
LIST OF FIGURES (1/4)
Figure No. Title Page
3-1. Pin Input/Output Circuits .................................................................................................................... 45
4-1. Memory Map ( µ PD789101, 789111, 789121, 789131) ..................................................................... 47
4-2. Memory Map (
µ PD789102, 789112, 789122, 789132) ..................................................................... 48
4-3. Memory Map (
µ PD789104, 789114, 789124, 789134) ..................................................................... 49
4-4. Memory Map (
µ PD78F9116, 78F9136) ............................................................................................. 50
4-5. Data Memory Addressing (
µ PD789101, 789111, 789121, 789131) ................................................. 52
4-6. Data Memory Addressing (
µ PD789102, 789112, 789122, 789132)................................................. 53
4-7. Data Memory Addressing (
µ PD789104, 789114, 789124, 789134)................................................. 54
4-8. Data Memory Addressing (
µ PD78F9116, 78F9136) ......................................................................... 55
4-9. Program Counter Configuration ......................................................................................................... 56
4-10. Program Status Word Configuration .................................................................................................. 56
4-11. Stack Pointer Configuration................................................................................................................ 58
4-12. Data to be Saved to Stack Memory................................................................................................... 58
4-13. Data to be Restored from Stack Memory .......................................................................................... 58
4-14. General Register Configuration.......................................................................................................... 59
5-1. Port Types ........................................................................................................................................... 73
5-2. Block Diagram of P00 to P03............................................................................................................. 75
5-3. Block Diagram of P10 and P11 .......................................................................................................... 76
5-4. Block Diagram of P20......................................................................................................................... 77
5-5. Block Diagram of P21......................................................................................................................... 78
5-6. Block Diagram of P22, P23, and P25 ................................................................................................ 79
5-7. Block Diagram of P24......................................................................................................................... 80
5-8. Block Diagram of P50 to P53............................................................................................................. 81
5-9. Block Diagram of P60 to P63............................................................................................................. 82
5-10. Port Mode Register Format ................................................................................................................ 84
5-11. Pull-Up Resistor Option Register 0 Format ....................................................................................... 84
5-12. Pull-Up Resistor Option Register B2 Format..................................................................................... 84
6-1. Block Diagram of Clock Generator .................................................................................................... 87
6-2. Processor Clock Control Register Format ......................................................................................... 88
6-3. External Circuit of System Clock Oscillator....................................................................................... 89
6-4. Examples of Incorrect Resonator Connection................................................................................... 90
6-5. Switching CPU Clock.......................................................................................................................... 93
7-1. Block Diagram of Clock Generator .................................................................................................... 95
7-2. Processor Clock Control Register Format ......................................................................................... 96
7-3. External Circuit of System Clock Oscillator....................................................................................... 97
7-4. Examples of Incorrect Resonator Connection................................................................................... 98
7-5. Switching CPU Clock.......................................................................................................................... 101

User’s Manual U13045EJ2V0UM00
18
LIST OF FIGURES (2/4)
Figure No. Title Page
8-1. Block Diagram of 16-Bit Timer Counter ............................................................................................. 105
8-2. 16-Bit Timer Mode Control Register 20 Format ................................................................................ 108
8-3. Port Mode Register 2 Format............................................................................................................. 109
8-4. Settings of 16-Bit Timer Mode Control Register 20 at Timer Interrupt Operation ........................... 110
8-5. Timing of Timer Interrupt Operation................................................................................................... 111
8-6. Settings of 16-Bit Timer Mode Control Register 20 at Timer Output Operation .............................. 112
8-7. Timer Output Timing ........................................................................................................................... 112
8-8. Settings of 16-Bit Timer Mode Control Register 20 at Capture Operation ...................................... 113
8-9. Capture Operation Timing (Both Edges of CPT20 Pin Are Specified) ............................................. 113
8-10. 16-Bit Timer Register 20 Readout Timing ......................................................................................... 114
9-1. Block Diagram of 8-Bit Timer/Event Counter 80 ............................................................................... 117
9-2. 8-Bit Timer Mode Control Register 80 Format .................................................................................. 118
9-3. Port Mode Register 2 Format............................................................................................................. 119
9-4. Interval Timer Operation Timing......................................................................................................... 121
9-5. External Event Counter Operation Timing (with Rising Edge Specified) ......................................... 122
9-6. Square Wave Output Timing .............................................................................................................. 124
9-7. PWM Output Timing............................................................................................................................ 126
9-8. Start Timing of 8-Bit Timer Register................................................................................................... 127
9-9. External Event Counter Operation Timing ......................................................................................... 127
10-1 Block Diagram of Watchdog Timer..................................................................................................... 130
10-2 Timer Clock Select Register 2 Format............................................................................................... 131
10-3 Format of Watchdog Timer Mode Register........................................................................................ 132
11-1. Block Diagram of 8-Bit A/D Converter ............................................................................................... 136
11-2. Format of A/D Converter Mode Register 0 ........................................................................................ 138
11-3. Format of A/D Input Select Register 0 ............................................................................................... 139
11-4. Basic Operation of 8-Bit A/D Converter ............................................................................................. 141
11-5. Relationships between Analog Input Voltage and A/D Conversion Result ...................................... 142
11-6. Software-Started A/D Conversion ...................................................................................................... 143
11-7. How to Reduce Current Consumption in Standby Mode .................................................................. 144
11-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ...................... 145
11-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value) ........................... 145
11-10. Analog Input Pin Treatment................................................................................................................ 146
11-11. A/D Conversion End Interrupt Request Generation Timing.............................................................. 147
11-12. AVDD Pin Treatment ............................................................................................................................ 147
12-1. Block Diagram of 10-Bit A/D Converter ............................................................................................. 150
12-2. Format of A/D Converter Mode Register 0........................................................................................ 152
12-3. Format of A/D Input Select Register 0............................................................................................... 153
12-4. Basic Operation of 10-Bit A/D Converter........................................................................................... 155
12-5. Relationships between Analog Input Voltage and A/D Conversion Result ...................................... 156

User’s Manual U13045EJ2V0UM00 19
LIST OF FIGURES (3/4)
Figure No. Title Page
12-6. Software-Started A/D Conversion ...................................................................................................... 157
12-7. How to Reduce Current Consumption in Standby Mode .................................................................. 158
12-8. Conversion Result Readout Timing (When Conversion Result Is Undefined Value) ...................... 159
12-9. Conversion Result Readout Timing (When Conversion Result Is Normal Value) ........................... 159
12-10. Analog Input Pin Treatment................................................................................................................ 160
12-11. A/D Conversion End Interrupt Request Generation Timing.............................................................. 161
12-12. AVDD Pin Treatment ............................................................................................................................ 161
13-1. Serial Interface 20 Block Diagram ..................................................................................................... 164
13-2. Baud Rate Generator Block Diagram ................................................................................................ 165
13-3. Serial Operating Mode Register 20 Format....................................................................................... 167
13-4. Asynchronous Serial Interface Mode Register 20 Format................................................................ 168
13-5. Asynchronous Serial Interface Status Register 20 Format............................................................... 170
13-6. Baud Rate Generator Control Register 20 Format ........................................................................... 171
13-7. Asynchronous Serial Interface Transmit/Receive Data Format........................................................ 183
13-8. Asynchronous Serial Interface Transmission Completion Interrupt Timing ..................................... 185
13-9. Asynchronous Serial Interface Reception Completion Interrupt Timing........................................... 186
13-10. Receive Error Timing .......................................................................................................................... 187
13-11. 3-Wire Serial I/O Mode Timing ........................................................................................................... 192
14-1. Block Diagram of Multiplier ................................................................................................................ 200
14-2. Multiplier Control Register 0 Format .................................................................................................. 201
14-3. Multiplier Operation Timing................................................................................................................. 202
15-1. Basic Configuration of Interrupt Function .......................................................................................... 205
15-2. Interrupt Request Flag Register Format ............................................................................................ 207
15-3. Interrupt Mask Flag Register Format ................................................................................................. 208
15-4. External Interrupt Mode Register 0 Format ....................................................................................... 209
15-5. Program Status Word Configuration .................................................................................................. 210
15-6. Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgement....................... 212
15-7. Timing of Non-Maskable Interrupt Request Acknowledgement........................................................ 212
15-8. Acknowledging Non-Maskable Interrupt Request ............................................................................. 212
15-9. Interrupt Acknowledgement Program Algorithm ................................................................................ 214
15-10. Interrupt Request Acknowledgement Timing (Example of MOV A,r)................................................ 215
15-11. Interrupt Request Acknowledgement Timing ..................................................................................... 215
(When Interrupt Request Flag Is Generated at the Last Clock During Instruction Execution) ....... 215
15-12. Example of Multiple Interrupts ........................................................................................................... 216
16-1. Oscillation Stabilization Time Select Register Format ...................................................................... 220
16-2. Releasing HALT Mode by Interrupt .................................................................................................... 222
16-3. Releasing HALT Mode by RESET Input ............................................................................................ 223
16-4. Releasing STOP Mode by Interrupt ................................................................................................... 225
16-5. Releasing STOP Mode by RESET Input ........................................................................................... 226

User’s Manual U13045EJ2V0UM00
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LIST OF FIGURES (4/4)
Figure No. Title Page
17-1. Block Diagram of Reset Function ...................................................................................................... 227
17-2. Reset Timing by RESET Input ........................................................................................................... 228
17-3. Reset Timing by Overflow in Watchdog Timer .................................................................................. 228
17-4. Reset Timing by RESET Input in STOP Mode .................................................................................. 228
18-1. Communication Mode Selection Format............................................................................................ 232
18-2. Flashpro III Connection in 3-Wire Serial I/O Mode ........................................................................... 233
18-3. Flashpro III Connection in UART Mode............................................................................................. 234
18-4. Flashpro III Connection in Pseudo 3-Wire Mode (When P0 Is Used).............................................. 234
18-5. Flashpro III Connection in 3-Wire Serial I/O Mode ........................................................................... 235
18-6. Flashpro III Connection in UART Mode............................................................................................. 235
18-7. Flashpro III Connection in Pseudo 3-Wire Mode (When P0 Is Used).............................................. 236
A-1. Development Tool Configuration ........................................................................................................ 252