NEC V850E/PH2 User manual

User’s Manual
V850E/PH2TM
32-Bit Single-Chip Microcontroller
Hardware
μPD70F3187
μPD70F3447
Document No. U16580EE3V1UD00
Date Published January 2007
©NEC Electronics Corporation 2007
Printed in Germany

2User’s Manual U16580EE3V1UD00
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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL (MAX) and V IH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL (MAX) and
V
IH (MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
All (other) product, brand, or trade names used in this pamphlet are the trademarks or
registered trademarks of their respective owners.
Product specifications are subject to change without notice. To ensure that you have
the latest product data, please contact your local NEC Electronics sales office.

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User’s Manual U16580EE3V1UD00
The information in this document is current as of October, 2006. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
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redundancy, fire-containment and anti-failure features.
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Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
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•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
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Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
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for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":

4User’s Manual U16580EE3V1UD00
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User’s Manual U16580EE3V1UD00
Preface
Readers This manual is intended for users who want to understand the functions of the
V850E/PH2 (PHOENIX-F).
Purpose This manual presents the hardware manual of V850E/PH2.
Organization This system specification describes the following sections:
•Pin function
•CPU function
•Internal peripheral function
•Flash memory
Legend Symbols and notation are used as follows:
Weight in data notation : Left is high-order column, right is low order column
Active low notation : xxx (pin or signal name is over-scored) or
/xxx (slash before signal name)
Memory map address: : High order at high stage and low order at low stage
Note : Explanation of (Note) in the text
Caution : Item deserving extra attention
Remark : Supplementary explanation to the text
Numeric notation : Binary... XXXX or XXXB
Decimal...
XXXX
Hexadecimal... XXXXH or 0x XXXX
Prefixes representing powers of 2 (address space, memory capacity)
K (kilo): 210 = 1024
M (mega): 220 = 10242= 1,048,576
G (giga): 230 = 10243= 1,073,741,824

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Preface
User’s Manual U16580EE3V1UD00

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User’s Manual U16580EE3V1UD00
Table of Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.1 Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.2 Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.5 Pin Configuration (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.6 Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.6.1 Internal block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.6.2 On-chip units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Chapter 2 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.1 List of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.2 Pin Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3 Description of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.4 Pin I/O Circuits and Recommended Connection of Unused Pins . . . . . . . . . . . . . . . 76
2.5 Noise Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Chapter 3 CPU Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.2 CPU Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.2.1 Program register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.2.2 System register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.2.3 Floating point arithmetic unit register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.3.1 Operating modes outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.3.2 Operation mode specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.4.1 CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.4.2 Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.4.3 Wrap-around of CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.4.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3.4.5 Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.4.6 Peripheral I/O registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.4.7 Programmable peripheral I/O area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
3.4.8 Specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
3.4.9 System wait control register (VSWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
3.4.10 DMA wait control registers 0 and 1 (DMAWC0, DMAWC1) . . . . . . . . . . . . . . . 142
3.4.11 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Chapter 4 Bus Control Function (μPD70F3187 only) . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.2 Bus Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.3 Memory Block Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
4.3.1 Chip select control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
4.4 Bus Cycle Type Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
4.4.1 Bus cycle type configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
4.5 Bus Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
4.5.1 Number of access clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.5.2 Bus sizing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
4.5.3 Endian control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
4.5.4 Bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.6 Wait Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
4.6.1 Programmable wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

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4.7 Idle State Insertion Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
4.8 Bus Priority Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
4.9 Boundary Operation Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
4.9.1 Program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
4.9.2 Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Chapter 5 Memory Access Control Function (μPD70F3187 only). . . . . . . . . . . . . . . 181
5.1 SRAM, External ROM, External I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.1.2 SRAM connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.1.3 SRAM, external ROM, external I/O access . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Chapter 6 DMA Functions (DMA Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.2 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.3 DMA Channel Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.4 DMA Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.4.1 DMA transfer of A/D converter result registers (ADC0, ADC1) . . . . . . . . . . . . 200
6.4.2 DMA transfer of PWM timer reload (TMR0, TMR1) . . . . . . . . . . . . . . . . . . . . . 204
6.4.3 DMA transfer of serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.4.4 Forcible termination of DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6.5 DMA Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Chapter 7 Interrupt/Exception Processing Function . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.2 Non-maskable Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
7.2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
7.2.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
7.2.3 Non-maskable interrupt status flag (NP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.2.4 Edge Detection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.3 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.3.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.3.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
7.3.3 Priorities of maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
7.3.4 Interrupt control register (PICn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
7.3.5 Interrupt mask registers 0 to 6 (IMR0 to IMR6) . . . . . . . . . . . . . . . . . . . . . . . . 240
7.3.6 In-service priority register (ISPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
7.3.7 Maskable interrupt status flag (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
7.3.8 Interrupt trigger mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
7.4 Software Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
7.4.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
7.4.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
7.4.3 Exception status flag (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
7.5 Exception Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
7.5.1 Illegal opcode definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
7.6 Periods in Which CPU Does Not Acknowledge Interrupts. . . . . . . . . . . . . . . . . . . . 254
Chapter 8 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
8.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
8.3 Power Save Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
8.3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
8.3.2 HALT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Chapter 9 16-Bit Timer/Event Counter P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
9.2 Function Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

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9.4 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
9.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
9.5.1 Anytime rewrite and reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
9.5.2 Interval timer mode (TPnMD2 to TPnMD0 = 000B) . . . . . . . . . . . . . . . . . . . . . 279
9.5.3 External event count mode (TPnMD2 to TPnMD0 = 001B) . . . . . . . . . . . . . . . 282
9.5.4 External trigger pulse output mode (TPnMD2 to TPnMD0 = 010B) . . . . . . . . . 286
9.5.5 One-shot pulse mode (TPnMD2 to TPnMD0 = 011B) . . . . . . . . . . . . . . . . . . . 289
9.5.6 PWM mode (TPnMD2 to TPnMD0 = 100B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
9.5.7 Free-running mode (TPnMD2 to TPnMD0 = 101B) . . . . . . . . . . . . . . . . . . . . . 297
9.5.8 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110B) . . . . . . . . . . . 304
9.5.9 Counter synchronous operation function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Chapter 10 16-bit Inverter Timer/Counter R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
10.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
10.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
10.4 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
10.4.1 Basic counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
10.4.2 Compare register rewrite operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
10.4.3 List of outputs in each mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
10.5 Match Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
10.5.1 Compare match interrupt related cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
10.6 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
10.6.1 Up count flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
10.6.2 Normal phase/inverted phase simultaneous active detection flag . . . . . . . . . . 369
10.6.3 Reload hold flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
10.7 Interrupt Thinning Out Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
10.7.1 Operation of interrupt thinning out function. . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
10.7.2 Operation examples when peak interrupts and valley interrupts
occur alternately 374
10.7.3 Interrupt thinning out function during counter saw tooth wave operation . . . . . 375
10.8 A/D Conversion Trigger Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
10.8.1 A/D conversion trigger operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
10.9 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
10.9.1 Error interrupt and error signal output functions . . . . . . . . . . . . . . . . . . . . . . . . 380
10.10 Operation in Each Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
10.10.1 Interval timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Chapter 10 16-bit Inverter Timer/Counter R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
10.10.2 External event count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
10.10.3 External trigger pulse output mode (TMR1 only) . . . . . . . . . . . . . . . . . . . . . . . 394
10.10.4 One-shot pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
10.10.5 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
10.10.6 Free-running mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
10.10.7 Pulse width measurement mode (TMR1 only) . . . . . . . . . . . . . . . . . . . . . . . . . 415
10.10.8 Triangular wave PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
10.10.9 High-accuracy T-PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
10.10.10 PWM mode with dead time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Chapter 11 16-bit Timer/Event Counter T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
11.2 Function Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
11.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .458
11.4 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
11.5 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
11.5.1 Basic counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
11.5.2 Method for writing to compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
11.6 Operation in Each Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

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11.6.1 Interval timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
11.6.2 External event count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
11.6.3 External trigger pulse output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
11.6.4 One-shot pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
11.6.5 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
11.6.6 Free-running mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
11.6.7 Pulse width measurement mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
11.6.8 Triangular wave PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
11.6.9 Encoder count function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
11.6.10 Offset trigger generation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose
Timer (TMENC10) (μPD70F3187 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
12.2 Function Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
12.3 Basic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
12.4 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
12.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
12.5.1 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
12.5.2 Operation in general-purpose timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
12.5.3 Operation in UDC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
12.6 Supplementary Description of Internal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 566
12.6.1 Clearing of count value in UDC mode B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
12.6.2 Clearing of count value upon occurrence of compare match . . . . . . . . . . . . . . 567
12.6.3 Transfer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
12.6.4 Interrupt signal output upon compare match . . . . . . . . . . . . . . . . . . . . . . . . . . 568
12.6.5 TM1UBD flag (bit 0 of STATUS register) operation . . . . . . . . . . . . . . . . . . . . . 568
Chapter 13 Auxiliary Frequency Output Function (AFO) . . . . . . . . . . . . . . . . . . . . . . . 569
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
13.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .569
13.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
13.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
13.4.1 Auxiliary frequency output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
13.4.2 Auxiliary frequency generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
13.4.3 Interval timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Chapter 14 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
14.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .574
14.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
14.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
14.4.1 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
14.4.2 Operation mode and trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
14.5 Operation in A/D Trigger Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
14.5.1 Select mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
14.5.2 Scan mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
14.6 Operation in Timer Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
14.6.1 Select mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
14.6.2 Scan mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
14.7 Operation in External Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
14.7.1 Select mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
14.7.2 Scan mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
14.8 Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Chapter 15 Asynchronous Serial Interface C (UARTC) . . . . . . . . . . . . . . . . . . . . . . . . 609
15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
15.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .610

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15.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612
15.4 Interrupt Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
15.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
15.5.1 Data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
15.5.2 SBF transmission/reception format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
15.5.3 SBF transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630
15.5.4 SBF receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631
15.5.5 UART transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632
15.5.6 Continuous transmit operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633
15.5.7 UART receive operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635
15.5.8 Receive error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636
15.5.9 Parity types and operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637
15.5.10 Receive data noise filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638
15.6 Dedicated Baud Rate Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
15.6.1 Baud rate generator configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639
15.6.2 Baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
15.6.3 Baud rate error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640
15.6.4 Baud rate setting example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641
15.6.5 Allowable baud rate range during reception . . . . . . . . . . . . . . . . . . . . . . . . . . . 642
15.6.6 Baud rate during continuous transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644
Chapter 16 Clocked Serial Interface B (CSIB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645
16.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .645
16.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649
16.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655
16.4.1 Single transfer mode (master mode, transmission/reception mode) . . . . . . . . 655
16.4.2 Single transfer mode (master mode, transmission mode) . . . . . . . . . . . . . . . . 656
16.4.3 Single transfer mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . 657
16.4.4 Continuous mode (master mode, transmission/reception mode) . . . . . . . . . . . 658
16.4.5 Continuous mode (master mode, transmission mode) . . . . . . . . . . . . . . . . . . . 659
16.4.6 Continuous mode (master mode, reception mode) . . . . . . . . . . . . . . . . . . . . . 660
16.4.7 Continuous reception mode (error). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661
16.4.8 Continuous mode (slave mode, transmission/reception mode) . . . . . . . . . . . . 662
16.4.9 Continuous mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . . . . 663
16.4.10 Clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664
16.5 Output Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666
16.6 Operation Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667
16.7 Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
16.7.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673
16.7.2 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674
16.7.3 Baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
16.8 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676
Chapter 17 Clocked Serial Interface 3 (CSI3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677
17.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .678
17.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680
17.4 Dedicated Baud Rate Generator 3n (BRG3n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693
17.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
17.5.1 Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695
17.5.2 Function of CSI data buffer register (CSIBUFn) . . . . . . . . . . . . . . . . . . . . . . . . 696
17.5.3 Data transfer direction specification function . . . . . . . . . . . . . . . . . . . . . . . . . . 697
17.5.4 Transfer data length changing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699
17.5.5 Function to select serial clock and data phase . . . . . . . . . . . . . . . . . . . . . . . . . 700
17.5.6 Master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701
17.5.7 Slave mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702
17.5.8 Transfer clock selection function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703

12 User’s Manual U16580EE3V1UD00
17.5.9 Single mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703
17.5.10 Consecutive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705
17.5.11 Transmission mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
17.5.12 Reception mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
17.5.13 Transmission/reception mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707
17.5.14 Delay control of transmission/reception completion interrupt (INTC3n) . . . . . . 708
17.5.15 Transfer wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709
17.5.16 Output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712
17.5.17 CSIBUFn overflow interrupt signal (INTC3nOVF) . . . . . . . . . . . . . . . . . . . . . . 713
17.6 Operating Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
17.6.1 Single mode (master mode, transmission mode) . . . . . . . . . . . . . . . . . . . . . . . 714
17.6.2 Single mode (master mode, reception mode). . . . . . . . . . . . . . . . . . . . . . . . . . 716
17.6.3 Single mode (master mode, transmission/reception mode) . . . . . . . . . . . . . . . 718
17.6.4 Single mode (slave mode, transmission mode) . . . . . . . . . . . . . . . . . . . . . . . . 720
17.6.5 Single mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 722
17.6.6 Single mode (slave mode, transmission/reception mode) . . . . . . . . . . . . . . . . 724
17.6.7 Consecutive mode (master mode, transmission mode) . . . . . . . . . . . . . . . . . . 726
17.6.8 Consecutive mode (master mode, reception mode). . . . . . . . . . . . . . . . . . . . . 728
17.6.9 Consecutive mode (master mode, transmission/reception mode) . . . . . . . . . . 730
17.6.10 Consecutive mode (slave mode, transmission mode) . . . . . . . . . . . . . . . . . . . 732
17.6.11 Consecutive mode (slave mode, reception mode) . . . . . . . . . . . . . . . . . . . . . . 734
17.6.12 Consecutive mode (in slave mode and transmission/reception mode) . . . . . . 736
17.7 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738
Chapter 18 AFCAN Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739
18.1.1 Overview of functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
18.1.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741
18.2 CAN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .742
18.2.1 Frame format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742
18.2.2 Frame types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
18.2.3 Data frame and remote frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743
18.2.4 Error frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750
18.2.5 Overload frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751
18.3 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
18.3.1 Determining bus priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
18.3.2 Bit stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752
18.3.3 Multi masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
18.3.4 Multi cast. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
18.3.5 CAN sleep mode/CAN stop mode function. . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
18.3.6 Error control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753
18.3.7 Baud rate control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759
18.4 Connection with Target System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763
18.5 Internal Registers of CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764
18.5.1 CAN module register and message buffer addresses . . . . . . . . . . . . . . . . . . . 764
18.5.2 CAN Controller configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765
18.5.3 CAN registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766
18.5.4 Register bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767
18.6 Bit Set/Clear Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771
18.7 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773
18.8 CAN Controller Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
18.8.1 Initialization of CAN module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
18.8.2 Initialization of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
18.8.3 Redefinition of message buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807
18.8.4 Transition from Initialization Mode to Operation Mode . . . . . . . . . . . . . . . . . . . 808
18.8.5 Resetting error counter CnERC of CAN module . . . . . . . . . . . . . . . . . . . . . . . 809
18.9 Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
18.9.1 Message reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810

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User’s Manual U16580EE3V1UD00
18.9.2 Receive Data Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810
18.9.3 Receive history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811
18.9.4 Mask function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813
18.9.5 Multi buffer receive block function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814
18.9.6 Remote frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815
18.10 Message Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
18.10.1 Message transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816
18.10.2 Transmit history list function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817
18.10.3 Automatic block transmission (ABT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819
18.10.4 Transmission abort process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820
18.10.5 Remote frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821
18.11 Power Saving Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
18.11.1 CAN sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822
18.11.2 CAN stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824
18.11.3 Example of using power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825
18.12 Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827
18.13 Diagnosis Functions and Special Operational Modes . . . . . . . . . . . . . . . . . . . . . . . 828
18.13.1 Receive-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828
18.13.2 Single-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
18.13.3 Self-test mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829
18.13.4 Receive/Transmit Operation in Each Operation Mode . . . . . . . . . . . . . . . . . . . 830
18.14 Time Stamp Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
18.14.1 Time stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831
18.15 Baud Rate Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
18.15.1 Baud rate setting conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832
18.15.2 Representative examples of baud rate settings . . . . . . . . . . . . . . . . . . . . . . . . 836
18.16 Operation of CAN Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840
Chapter 19 Random Number Generator (μPD70F3187 only) . . . . . . . . . . . . . . . . . . . . 865
19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865
19.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .865
19.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
19.3.1 Access timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866
Chapter 20 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867
20.2 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868
20.2.1 Function of each port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869
20.2.2 Port types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870
20.2.3 Peripheral registers of I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 893
20.2.4 Peripheral registers of valid edge control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 896
20.3 Port Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
20.3.1 Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897
20.3.2 Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 898
20.3.3 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 902
20.3.4 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 906
20.3.5 Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910
20.3.6 Port 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 913
20.3.7 Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 918
20.3.8 Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 924
20.3.9 Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 928
20.3.10 Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 932
20.3.11 Port 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 936
20.3.12 Port AL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 939
20.3.13 Port AH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 943
20.3.14 Port DL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945
20.3.15 Port DH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 949
20.3.16 Port CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 953

14 User’s Manual U16580EE3V1UD00
20.3.17 Port CT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955
20.3.18 Port CM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 958
20.3.19 Port CD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 961
20.4 Noise Elimination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 965
Chapter 21 Reset Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 971
21.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .971
21.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 972
Chapter 22 Internal RAM Parity Check Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
22.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 973
22.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 974
Chapter 23 On-Chip Debug Function (OCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
23.1 Function Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
23.1.1 On-chip debug unit type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
23.1.2 Debug function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 977
23.2 Connection with N-Wire Type Emulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
23.2.1 KEL connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 979
23.3 Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 983
Chapter 24 Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 985
24.2 Memory Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 986
24.3 Functional Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 988
24.4 Rewriting by Dedicated Flash Programmer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
24.4.1 Programming environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 991
24.4.2 Communication mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 992
24.4.3 Flash memory control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 995
24.4.4 Selection of communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 996
24.4.5 Communication commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 997
24.4.6 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 998
24.5 Rewriting by Self Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
24.5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1003
24.5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1004
Chapter 25 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
25.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1007
25.2 General Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
25.2.1 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
25.2.2 Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1008
25.2.3 Oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1009
25.3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1010
25.4 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
25.4.1 External asynchronous memory access read timing . . . . . . . . . . . . . . . . . . . 1012
25.4.2 External asynchronous memory access write timing . . . . . . . . . . . . . . . . . . . 1014
25.4.3 Reset Timing (Power Up/Down Sequence) . . . . . . . . . . . . . . . . . . . . . . . . . . 1016
25.4.4 Interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1017
25.5 Peripheral Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
25.5.1 Timer characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1018
25.5.2 Serial interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1021
25.5.3 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1030
25.6 Flash Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1031
Chapter 26 Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1033

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User’s Manual U16580EE3V1UD00
Chapter 27 Recommended Soldering Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 1035
Appendix A Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1037
Appendix B Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1047

16 User’s Manual U16580EE3V1UD00

17
User’s Manual U16580EE3V1UD00
List of Figures
Figure 1-1: Pin Configuration 208-pin Plastic LQFP ...................................................................... 37
Figure 1-2: Pin Configuration 256-pin Plastic BGA (21 × 21) ........................................................ 38
Figure 1-3: Internal Block Diagram of mPD70F3187..................................................................... 44
Figure 1-4: Internal Block Diagram of mPD70F3447..................................................................... 45
Figure 2-1: Pin I/O Circuits ............................................................................................................ 80
Figure 2-2: Noise Removal Time Control Register (1/2) .............................................................. 82
Figure 3-1: CPU Register Set ........................................................................................................ 86
Figure 3-2: Program Counter (PC) ............................................................................................... 87
Figure 3-3: Interrupt Status Saving Registers (EIPC, EIPSW) ..................................................... 89
Figure 3-4: NMI Status Saving Registers (FEPC, FEPSW) .......................................................... 90
Figure 3-5: Interrupt Source Register (ECR) ............................................................................... 90
Figure 3-6: Program Status Word (PSW) .................................................................................... 91
Figure 3-7: CALLT Execution Status Saving Registers (CTPC, CTPSW) .................................... 92
Figure 3-8: Exception/Debug Trap Status Saving Registers (DBPC, DBPSW) ............................ 93
Figure 3-9: CALLT Base Pointer (CTBP) ...................................................................................... 93
Figure 3-10: Floating Point Arithmetic Control Register (ECT) ....................................................... 94
Figure 3-11: Floating Point Arithmetic Status Register (EFG) ........................................................ 95
Figure 3-12: CPU Address Space ...................................................................................................98
Figure 3-13: Address Space Image .................................................................................................99
Figure 3-14: Program Space ......................................................................................................... 100
Figure 3-15: Data Space................................................................................................................ 100
Figure 3-16: Memory Map of μPD70F3187 ................................................................................... 101
Figure 3-17: Memory Map of μPD70F3447 ................................................................................... 102
Figure 3-18: Internal ROM / Internal Flash Memory Area of μPD70F3187 ................................... 103
Figure 3-19: Internal ROM / Internal Flash Memory Area of μPD70F3447 .................................. 104
Figure 3-20: Internal RAM Area of μPD70F3187........................................................................... 105
Figure 3-21: Internal RAM Area of μPD70F3447........................................................................... 105
Figure 3-22: On-Chip Peripheral I/O Area ..................................................................................... 106
Figure 3-23: Programmable Peripheral I/O Area (Outline) ............................................................ 121
Figure 3-24: Programmable Peripheral Area Control Register BPC ............................................. 122
Figure 3-25: Processor Command Register (PRCMD).................................................................. 140
Figure 3-26: System Status Register Format PHS ...................................................................... 141
Figure 4-1: Memory Block Function............................................................................................. 146
Figure 4-2: Chip Area Select Control Registers 0, 1 (1/2) ......................................................... 147
Figure 4-3: Bus Cycle Configuration Registers 0, 1 (BCT0, BCT1) ........................................... 150
Figure 4-4: Bus Size Configuration Register (BSC) .................................................................... 152
Figure 4-5: Big Endian Addresses within Word ........................................................................... 153
Figure 4-6: Little Endian Addresses within Word ......................................................................... 153
Figure 4-7: Endian Configuration Register (BEC) ....................................................................... 154
Figure 4-8: Data Wait Control Registers 0, 1 (DWC0, DWC1) Format ..................................... 174
Figure 4-9: Address Wait Control Register (AWC) ..................................................................... 175
Figure 4-10: Bus Cycle Control Register (BCC) ........................................................................... 177
Figure 4-11: Bus Clock Dividing Control Register (DVC) .............................................................. 178
Figure 5-1: Examples of Connection to SRAM (1/2).................................................................... 182
Figure 5-2: SRAM, External ROM, External I/O Access Timing (1/8).......................................... 184
Figure 6-1: DMA Transfer Memory Start Address Registers 0 to 7 (MAR0 to MAR7) ................ 194
Figure 6-2: DMA Transfer SFR Start Address Registers 2, 3 (SAR2, SAR3) ............................. 195
Figure 6-3: DMA Transfer Count Registers 0 to 7 (DTCR0 to DTCR7) ...................................... 196
Figure 6-4: DMA Mode Control Register (DMAMC) .................................................................... 197
Figure 6-5: DMA Status Register (DMAS) .................................................................................. 197
Figure 6-6: DMA Data Size Control Register (DMDSC) ............................................................. 198
Figure 6-7: DMA Trigger Factor Registers 4 to 7 (DTFR4 to DTFR7) ........................................ 199
Figure 6-8: Initialization of DMA Transfer for A/D Conversion Result.......................................... 201
Figure 6-9: Operation of DMA Channel 0/1 ................................................................................. 202
Figure 6-10: DMA Channel 0 and 1 Trigger Signal Timing ............................................................ 203
Figure 6-11: Initialization of DMA Transfer for TMRn Compare Registers .................................... 205

18 User’s Manual U16580EE3V1UD00
Figure 6-12: Operation of DMA Channel 2/3 ................................................................................. 206
Figure 6-13: DMA Channel 2 and 3 Trigger Signal Timing ............................................................ 207
Figure 6-14: Initialization of DMA Transfer for Serial Data Reception ........................................... 209
Figure 6-15: Operation of DMA Channel 4/5 ................................................................................. 210
Figure 6-16: DMA Channel 4 and 5 Trigger Signal Timing ............................................................ 211
Figure 6-17: Initialization of DMA Transfer for Serial Data Transmission ...................................... 213
Figure 6-18: DMA Channel 6 and 7 Trigger Signal Timing ............................................................ 214
Figure 6-19: Operation of DMA Channel 6/7 ................................................................................. 215
Figure 6-20: CPU and DMA Controller Processing of DMA Transfer Termination (Example)....... 216
Figure 6-21: Correlation between Serial I/O Interface Interrupts and DMA Completion Interrupts 218
Figure 7-1: Processing Configuration of Non-Maskable Interrupt................................................ 225
Figure 7-2: Acknowledging Non-Maskable Interrupt Request ..................................................... 226
Figure 7-3: RETI Instruction Processing ...................................................................................... 227
Figure 7-4: Non-maskable Interrupt Status Flag (NP) ................................................................ 228
Figure 7-5: NMI Edge Detection Specification: Interrupt Mode Register 0 (INTM0) .................. 228
Figure 7-6: Maskable Interrupt Processing .................................................................................. 230
Figure 7-7: RETI Instruction Processing ...................................................................................... 231
Figure 7-8: Example of Processing in which Another Interrupt Request Is Issued
while an Interrupt is being Processed (1/2) ............................................................... 233
Figure 7-9: Example of Processing Interrupt Requests Simultaneously Generated.................... 235
Figure 7-10: Interrupt Control Register (PICn) .............................................................................. 236
Figure 7-11: Interrupt Mask Registers 0 to 2 (IMR0 to IMR2) ....................................................... 240
Figure 7-12: Interrupt Mask Registers 3 to 6 (IMR3 to IMR6) ....................................................... 241
Figure 7-13: Interrupt Service Priority Register (ISPR) ................................................................. 242
Figure 7-14: Maskable interrupt status flag (ID) ............................................................................ 243
Figure 7-15: Interrupt Mode Register 0 (INTM0) .......................................................................... 245
Figure 7-16: Interrupt Mode Register 1 (INTM1) .......................................................................... 246
Figure 7-17: Interrupt Mode Register 2 (INTM2) .......................................................................... 247
Figure 7-18: Interrupt Mode Register 3 (INTM3) .......................................................................... 248
Figure 7-19: Software Exception Processing................................................................................. 249
Figure 7-20: RETI Instruction Processing ...................................................................................... 250
Figure 7-21: Exception Status Flag (EP) ...................................................................................... 251
Figure 7-22: Illegal Opcode............................................................................................................ 252
Figure 7-23: Exception Trap Processing........................................................................................ 253
Figure 7-24: Restore Processing from Exception Trap.................................................................. 253
Figure 8-1: Clock Generator ........................................................................................................ 255
Figure 8-2: Power Save Mode State Transition Diagram ............................................................ 256
Figure 9-1: Block Diagram of Timer P.......................................................................................... 260
Figure 9-2: TMPn Capture/Compare Register 0 (TPnCCR0) ..................................................... 261
Figure 9-3: TMPn Capture/Compare Register 1 (TPnCCR1) ..................................................... 262
Figure 9-4: TMPn Counter Register (TPnCNT) .......................................................................... 263
Figure 9-5: TMPn Control Register 0 (TPnCTL0) ...................................................................... 264
Figure 9-6: TMPn Control Register 1 (TPnCTL1) (1/2)............................................................... 265
Figure 9-7: TMPn I/O Control Register 0 (TPnIOC0) .................................................................. 267
Figure 9-8: TMPn I/O Control Register 1 (TPnIOC1) .................................................................. 268
Figure 9-9: TMPn I/O Control Register 2 (TPnIOC2) .................................................................. 269
Figure 9-10: TMPn Option Register 0 (TPnOPT0) ........................................................................ 270
Figure 9-11: TMPn Input Control Register 0 (TPIC0) .................................................................. 271
Figure 9-12: TMP Input Control Register 1 (TPIC1) .................................................................... 272
Figure 9-13: TMP Input Control Register 1 (TPIC1) .................................................................... 273
Figure 9-14: Basic Operation Flow for Anytime Write.................................................................... 275
Figure 9-15: Timing Diagram for Anytime Write............................................................................. 276
Figure 9-16: Basic Operation Flow for Reload (Batch Rewrite) ..................................................... 277
Figure 9-17: Timing Chart for Reload ............................................................................................ 278
Figure 9-18: Flowchart of Basic Operation in Interval Timer Mode................................................ 279
Figure 9-19: Basic Operation Timing in Interval Timer Mode (1/2) ................................................ 280
Figure 9-20: Flowchart of Basic Operation in External Event Count Mode.................................... 283
Figure 9-21: Basic Operation Timing in External Event Count Mode (1/2) .................................... 284

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User’s Manual U16580EE3V1UD00
Figure 9-22: Flowchart of Basic Operation in External Trigger Pulse Output Mode ...................... 287
Figure 9-23: Basic Operation Timing in External Trigger Pulse Output Mode ............................... 288
Figure 9-24: Flowchart of Basic Operation in One-Shot Pulse Mode ............................................ 290
Figure 9-25: Timing of Basic Operation in One-Shot Pulse Mode................................................. 291
Figure 9-26: Flowchart of Basic Operation in PWM Mode (1/2) .................................................... 293
Figure 9-27: Basic Operation Timing in PWM Mode (1/2) ............................................................. 295
Figure 9-28: Flowchart of Basic Operation in Free-Running Mode................................................ 299
Figure 9-29: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 0) ...... 300
Figure 9-30: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 1, TPnCCS0 = 1) ...... 301
Figure 9-31: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 1, TPnCCS0 = 0) ...... 302
Figure 9-32: Basic Operation Timing in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 1) ...... 303
Figure 9-33: Flowchart of Pulse Period Measurement .................................................................. 305
Figure 9-34: Basic Operation Timing of Pulse Period Measurement............................................. 306
Figure 9-35: Flowchart of Alternating Pulse Width and Pulse Space Measurement ..................... 307
Figure 9-36: Basic Operation Timing of Alternating Pulse Width and Pulse Space Measurement 308
Figure 9-37: Flowchart of Simultaneous Pulse Width and Pulse Space Measurement................. 309
Figure 9-38: Basic Operation Timing of Simultaneous Pulse Width
and Pulse Space Measurement ................................................................................ 310
Figure 10-1: Timer Rn Block Diagram ........................................................................................... 315
Figure 10-2: TMRn Capture/Compare Register 0 (TRnCCR0) ..................................................... 316
Figure 10-3: TMRn Capture/Compare Register 1 (TRnCCR1) ..................................................... 317
Figure 10-4: TMRn Capture/Compare Register 2 (TRnCCR2) ..................................................... 318
Figure 10-5: TMRn Capture/Compare Register 3 (TRnCCR3) ..................................................... 319
Figure 10-6: TMRn Compare Register 4 (TRnCCR4) ................................................................... 320
Figure 10-7: TMRn Compare Register 5 (TRnCCR5) ................................................................... 321
Figure 10-8: TMRn Counter Read Register (TRnCNT) ................................................................ 322
Figure 10-9: TMRn Sub-Counter Read Register (TRnSBC) ......................................................... 322
Figure 10-10: TMRn Dead Time Setting Register 0 (TRnDTC0) .................................................... 323
Figure 10-11: TMRn Dead Time Setting Register 1 (TRnDTC1) .................................................... 323
Figure 10-12: TMRn Control Register 0 (TRnCTL0) (1/2) .............................................................. 324
Figure 10-13: TMRn Control Register 1 (TRnCTL1) (1/2) ............................................................... 326
Figure 10-14: TMRn I/O Control Register 0 (TRnIOC0) ................................................................. 328
Figure 10-15: TMR1 I/O Control Register 1 (TR1IOC1) ................................................................. 329
Figure 10-16: TMR1 I/O Control Register 2 (TR1IOC2) ................................................................. 330
Figure 10-17: TMRn I/O Control Register 3 (TRnIOC3) ................................................................. 331
Figure 10-18: TMRn I/O Control Register 4 (TRnIOC4) ................................................................. 332
Figure 10-19: TMRn Option Register 0 (TRnOPT0) (1/2)................................................................ 333
Figure 10-20: TMRn Option Register 1 (TRnOPT1) (1/2)................................................................ 335
Figure 10-21: TMRn Option Register 2 (TRnOPT2) (1/2)................................................................ 337
Figure 10-22: TMRn Option Register 3 (TRnOPT3) (1/2)................................................................ 339
Figure 10-23: TMRn Option Register 6 (TRnOPT6) ....................................................................... 341
Figure 10-24: TMRn Option Register 7 (TRnOPT7) ....................................................................... 342
Figure 10-25: Anytime Rewrite Timing ............................................................................................ 347
Figure 10-26: Basic Operation Flow during Batch Rewrite.............................................................. 352
Figure 10-27: Batch Rewrite Timing (1/2) ........................................................................................ 353
Figure 10-28: TORn7 Pin Output Timing 1 ...................................................................................... 360
Figure 10-29: Interrupt Signal Output Example (1/2)....................................................................... 364
Figure 10-30: Up Count Flags Timings (1/2) ................................................................................... 368
Figure 10-31: Normal Phase/Inverted Phase Simultaneous Active Detection Flag Timing ............. 369
Figure 10-32: Reload Hold Flag Timings ......................................................................................... 370
Figure 10-33: Interrupt Thinning Out Operations (1/2) .................................................................... 372
Figure 10-34: Examples when Peak Interrupts and Valley Interrupts Occur Alternately (1/2)......... 374
Figure 10-35: A/D Conversion Trigger Output Controller................................................................. 376
Figure 10-36: A/D Conversion Trigger Timings (1/2)....................................................................... 378
Figure 10-37: Error Interrupt (INTTRnER) and Error Signal (TRnER) Output Controller................. 380
Figure 10-38: Error Interrupt and Error Signal Output Controller in PWM mode ............................. 381
Figure 10-39: Error Interrupt and Error Signal Output Controller in triangular wave PWM mode.... 382
Figure 10-40: Error Interrupt and Error Signal Output Controller

20 User’s Manual U16580EE3V1UD00
in High-Accuracy T-PWM Mode / PWM Mode with Dead Time ................................ 383
Figure 10-41: Basic Operation Flow in Interval Timer Mode............................................................ 384
Figure 10-42: Basic Timing in Interval Timer Mode (1/2)................................................................. 386
Figure 10-43: Basic Operation Timing in External Event Count Mode (1/4) .................................... 390
Figure 10-44: Basic Operation Flow in External Trigger Pulse Output Mode .................................. 396
Figure 10-45: Basic Operation Timing in External Trigger Pulse Output Mode ............................... 397
Figure 10-46: Basic Operation Flow in One-Shot Pulse Mode ........................................................ 400
Figure 10-47: Basic Operation Timing in One-Shot Pulse Mode ..................................................... 401
Figure 10-48: Basic Operation Mode in PWM Mode (1/2) ............................................................... 404
Figure 10-49: Basic Operation Timing in PWM Mode (1/2) ............................................................. 406
Figure 10-50: Basic Operation Flow in Free-Running Mode............................................................ 408
Figure 10-51: Basic Operation Timing in Free-Running Mode (Compare Function) ....................... 411
Figure 10-52: Basic Operation Timing in Free-Running Mode (Capture Function) ......................... 412
Figure 10-53: Basic Operation Timing in Free-Running Mode (Compare/Capture Function).......... 413
Figure 10-54: Basic Operation Timing in Pulse Width Measurement Mode .................................... 415
Figure 10-55: Basic Operation Timing in Triangular Wave PWM Mode .......................................... 419
Figure 10-56: High-Accuracy T-PWM Mode Block Diagram............................................................ 420
Figure 10-57: Counter Operation in High-Accuracy T-PWM Mode.................................................. 424
Figure 10-58: Sub-Counter Operation in High-Accuracy T-PWM Mode .......................................... 424
Figure 10-59: Timer Output Example When TRnCE = 1 Is Set (Initial)
(High-Accuracy T-PWM Mode).................................................................................. 425
Figure 10-60: Timer Output Example During Operation (High-Accuracy T-PWM Mode) ................ 426
Figure 10-61: TORn1 Pin Output Example When Performing Additional Pulse Control.................. 427
Figure 10-62: TORn1 Pin Output Example When Additional Pulse Control Is Not Performed ........ 428
Figure 10-63: Timings of Timer Output in High-accuracy T-PWM mode (1/3)................................. 429
Figure 10-64: Timer Output Change after Compare Register Updating Timings (1/3) .................... 433
Figure 10-65: Compare Register Value After Trough Reload Timing (1/3)...................................... 436
Figure 10-66: Compare Register Value After Trough Reload (TRnDTC1 < TRnDTC0) (1/3) ......... 439
Figure 10-67: Compare Register Value After Trough Reload (1/3) ................................................. 442
Figure 10-68: Output Waveform Example When Dead Time Is Set ................................................ 445
Figure 10-69: Dead Time Control in High-Accuracy T-PWM Mode ................................................. 446
Figure 10-70: Operation Example Setting Is Out of Range ............................................................. 447
Figure 10-71: Error Interrupt Operation Example ............................................................................ 448
Figure 10-72: Block Diagram in PWM Mode With Dead Time......................................................... 449
Figure 10-73: Output Waveform Example in PWM Mode with Dead Time...................................... 451
Figure 10-74: Timer Output Example When TRnCE = 1 Is Set (Initial)
(PWM mode with Dead Time) ................................................................................... 454
Figure 10-75: Output Waveform Example in PWM Mode with Dead Time...................................... 455
Figure 10-76: Error Interrupt (INTTRnER) in PWM Mode with Dead Time...................................... 456
Figure 11-1: Block Diagram of Timer T.......................................................................................... 460
Figure 11-2: TMTn Capture/Compare Register 0 (TTnCCR0) ...................................................... 461
Figure 11-3: TMTn Capture/Compare Register 1 (TTnCCR1) ...................................................... 462
Figure 11-4: TMTn Counter Write Buffer Register (TTnTCW) ...................................................... 464
Figure 11-5: TMTn Counter Read Buffer Register (TTnCNT) ....................................................... 464
Figure 11-6: TMTn Control Register 0 (TTnCTL0) (1/2) ................................................................ 465
Figure 11-7: TMTn Control Register 1 (TTnCTL1) (1/2) ................................................................ 467
Figure 11-8: TMTn Control Register 2 (TTnCTL2) (1/2) ................................................................ 469
Figure 11-9: TMTn I/O Control Register 0 (TTnIOC0) .................................................................. 471
Figure 11-10: TMTn I/O Control Register 1 (TTnIOC1) .................................................................. 472
Figure 11-11: TMTn I/O Control Register 2 (TTnIOC2) .................................................................. 473
Figure 11-12: TMTn I/O Control Register 3 (TTnIOC3) (1/2)........................................................... 474
Figure 11-13: TMTn Option Register 0 (TTnOPT0) ........................................................................ 476
Figure 11-14: TMTn Option Register 1 (TTnOPT1) (1/2)................................................................. 477
Figure 11-15: TMTn Option Register 2 (TTnOPT2) ......................................................................... 479
Figure 11-16: Basic Operation Flow for Anytime Rewrite................................................................ 483
Figure 11-17: Basic Anytime Rewrite Operation Timing .................................................................. 484
Figure 11-18: Basic Operation Flow for Reload (Batch Rewrite) ..................................................... 485
Figure 11-19: Basic Reload Operation Timing................................................................................. 486