NEC V850E/PH2 User manual

User’s Manual
V850E/PH2TM
32-Bit Single-Chip Microcontroller
Hardware
μPD70F3187
μPD70F3447
Document No. U16580EE3V1UD00
Date Published January 2007
©NEC Electronics Corporation 2007
Printed in Germany

2User’s Manual U16580EE3V1UD00
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VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL (MAX) and V IH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL (MAX) and
V
IH (MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
All (other) product, brand, or trade names used in this pamphlet are the trademarks or
registered trademarks of their respective owners.
Product specifications are subject to change without notice. To ensure that you have
the latest product data, please contact your local NEC Electronics sales office.

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User’s Manual U16580EE3V1UD00
The information in this document is current as of October, 2006. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
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or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
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responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
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redundancy, fire-containment and anti-failure features.
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Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
•
•
•
•
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•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
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Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
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for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":

4User’s Manual U16580EE3V1UD00
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User’s Manual U16580EE3V1UD00
Preface
Readers This manual is intended for users who want to understand the functions of the
V850E/PH2 (PHOENIX-F).
Purpose This manual presents the hardware manual of V850E/PH2.
Organization This system specification describes the following sections:
•Pin function
•CPU function
•Internal peripheral function
•Flash memory
Legend Symbols and notation are used as follows:
Weight in data notation : Left is high-order column, right is low order column
Active low notation : xxx (pin or signal name is over-scored) or
/xxx (slash before signal name)
Memory map address: : High order at high stage and low order at low stage
Note : Explanation of (Note) in the text
Caution : Item deserving extra attention
Remark : Supplementary explanation to the text
Numeric notation : Binary... XXXX or XXXB
Decimal...
XXXX
Hexadecimal... XXXXH or 0x XXXX
Prefixes representing powers of 2 (address space, memory capacity)
K (kilo): 210 = 1024
M (mega): 220 = 10242= 1,048,576
G (giga): 230 = 10243= 1,073,741,824

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Preface
User’s Manual U16580EE3V1UD00

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User’s Manual U16580EE3V1UD00
Table of Contents
Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chapter 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.1 Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.2 Device Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.4 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.5 Pin Configuration (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.6 Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.6.1 Internal block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.6.2 On-chip units. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Chapter 2 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.1 List of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
2.2 Pin Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
2.3 Description of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
2.4 Pin I/O Circuits and Recommended Connection of Unused Pins . . . . . . . . . . . . . . . 76
2.5 Noise Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Chapter 3 CPU Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
3.2 CPU Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.2.1 Program register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.2.2 System register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.2.3 Floating point arithmetic unit register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.3 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.3.1 Operating modes outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.3.2 Operation mode specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
3.4 Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.4.1 CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.4.2 Images . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
3.4.3 Wrap-around of CPU address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.4.4 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3.4.5 Areas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.4.6 Peripheral I/O registers list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.4.7 Programmable peripheral I/O area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
3.4.8 Specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
3.4.9 System wait control register (VSWC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
3.4.10 DMA wait control registers 0 and 1 (DMAWC0, DMAWC1) . . . . . . . . . . . . . . . 142
3.4.11 Cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Chapter 4 Bus Control Function (μPD70F3187 only) . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.2 Bus Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
4.3 Memory Block Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
4.3.1 Chip select control function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
4.4 Bus Cycle Type Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
4.4.1 Bus cycle type configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
4.5 Bus Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
4.5.1 Number of access clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
4.5.2 Bus sizing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
4.5.3 Endian control function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
4.5.4 Bus width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
4.6 Wait Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
4.6.1 Programmable wait function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174

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4.7 Idle State Insertion Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
4.8 Bus Priority Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
4.9 Boundary Operation Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
4.9.1 Program space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
4.9.2 Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Chapter 5 Memory Access Control Function (μPD70F3187 only). . . . . . . . . . . . . . . 181
5.1 SRAM, External ROM, External I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
5.1.2 SRAM connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
5.1.3 SRAM, external ROM, external I/O access . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Chapter 6 DMA Functions (DMA Controller) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
6.2 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
6.3 DMA Channel Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.4 DMA Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
6.4.1 DMA transfer of A/D converter result registers (ADC0, ADC1) . . . . . . . . . . . . 200
6.4.2 DMA transfer of PWM timer reload (TMR0, TMR1) . . . . . . . . . . . . . . . . . . . . . 204
6.4.3 DMA transfer of serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6.4.4 Forcible termination of DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
6.5 DMA Interrupt Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Chapter 7 Interrupt/Exception Processing Function . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
7.2 Non-maskable Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
7.2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
7.2.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
7.2.3 Non-maskable interrupt status flag (NP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.2.4 Edge Detection Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228
7.3 Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.3.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
7.3.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
7.3.3 Priorities of maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232
7.3.4 Interrupt control register (PICn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236
7.3.5 Interrupt mask registers 0 to 6 (IMR0 to IMR6) . . . . . . . . . . . . . . . . . . . . . . . . 240
7.3.6 In-service priority register (ISPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
7.3.7 Maskable interrupt status flag (ID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
7.3.8 Interrupt trigger mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
7.4 Software Exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
7.4.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
7.4.2 Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
7.4.3 Exception status flag (EP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
7.5 Exception Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
7.5.1 Illegal opcode definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252
7.6 Periods in Which CPU Does Not Acknowledge Interrupts. . . . . . . . . . . . . . . . . . . . 254
Chapter 8 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
8.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .255
8.3 Power Save Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
8.3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
8.3.2 HALT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
Chapter 9 16-Bit Timer/Event Counter P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
9.2 Function Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260

9
User’s Manual U16580EE3V1UD00
9.4 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264
9.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
9.5.1 Anytime rewrite and reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274
9.5.2 Interval timer mode (TPnMD2 to TPnMD0 = 000B) . . . . . . . . . . . . . . . . . . . . . 279
9.5.3 External event count mode (TPnMD2 to TPnMD0 = 001B) . . . . . . . . . . . . . . . 282
9.5.4 External trigger pulse output mode (TPnMD2 to TPnMD0 = 010B) . . . . . . . . . 286
9.5.5 One-shot pulse mode (TPnMD2 to TPnMD0 = 011B) . . . . . . . . . . . . . . . . . . . 289
9.5.6 PWM mode (TPnMD2 to TPnMD0 = 100B) . . . . . . . . . . . . . . . . . . . . . . . . . . . 292
9.5.7 Free-running mode (TPnMD2 to TPnMD0 = 101B) . . . . . . . . . . . . . . . . . . . . . 297
9.5.8 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110B) . . . . . . . . . . . 304
9.5.9 Counter synchronous operation function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Chapter 10 16-bit Inverter Timer/Counter R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313
10.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314
10.3 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
10.4 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
10.4.1 Basic counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
10.4.2 Compare register rewrite operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
10.4.3 List of outputs in each mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
10.5 Match Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364
10.5.1 Compare match interrupt related cautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
10.6 Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
10.6.1 Up count flags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
10.6.2 Normal phase/inverted phase simultaneous active detection flag . . . . . . . . . . 369
10.6.3 Reload hold flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
10.7 Interrupt Thinning Out Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
10.7.1 Operation of interrupt thinning out function. . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
10.7.2 Operation examples when peak interrupts and valley interrupts
occur alternately 374
10.7.3 Interrupt thinning out function during counter saw tooth wave operation . . . . . 375
10.8 A/D Conversion Trigger Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
10.8.1 A/D conversion trigger operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
10.9 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .380
10.9.1 Error interrupt and error signal output functions . . . . . . . . . . . . . . . . . . . . . . . . 380
10.10 Operation in Each Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
10.10.1 Interval timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
Chapter 10 16-bit Inverter Timer/Counter R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385
10.10.2 External event count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388
10.10.3 External trigger pulse output mode (TMR1 only) . . . . . . . . . . . . . . . . . . . . . . . 394
10.10.4 One-shot pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
10.10.5 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
10.10.6 Free-running mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408
10.10.7 Pulse width measurement mode (TMR1 only) . . . . . . . . . . . . . . . . . . . . . . . . . 415
10.10.8 Triangular wave PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
10.10.9 High-accuracy T-PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
10.10.10 PWM mode with dead time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Chapter 11 16-bit Timer/Event Counter T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
11.2 Function Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457
11.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .458
11.4 Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465
11.5 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
11.5.1 Basic counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
11.5.2 Method for writing to compare register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
11.6 Operation in Each Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487

10 User’s Manual U16580EE3V1UD00
11.6.1 Interval timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487
11.6.2 External event count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490
11.6.3 External trigger pulse output mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
11.6.4 One-shot pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498
11.6.5 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501
11.6.6 Free-running mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505
11.6.7 Pulse width measurement mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
11.6.8 Triangular wave PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512
11.6.9 Encoder count function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
11.6.10 Offset trigger generation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532
Chapter 12 16-bit 2-Phase Encoder Input Up/Down Counter/General Purpose
Timer (TMENC10) (μPD70F3187 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
12.2 Function Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535
12.3 Basic Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537
12.4 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
12.5 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
12.5.1 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554
12.5.2 Operation in general-purpose timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555
12.5.3 Operation in UDC mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558
12.6 Supplementary Description of Internal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 566
12.6.1 Clearing of count value in UDC mode B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
12.6.2 Clearing of count value upon occurrence of compare match . . . . . . . . . . . . . . 567
12.6.3 Transfer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
12.6.4 Interrupt signal output upon compare match . . . . . . . . . . . . . . . . . . . . . . . . . . 568
12.6.5 TM1UBD flag (bit 0 of STATUS register) operation . . . . . . . . . . . . . . . . . . . . . 568
Chapter 13 Auxiliary Frequency Output Function (AFO) . . . . . . . . . . . . . . . . . . . . . . . 569
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569
13.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .569
13.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570
13.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
13.4.1 Auxiliary frequency output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
13.4.2 Auxiliary frequency generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
13.4.3 Interval timer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572
Chapter 14 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
14.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .574
14.3 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576
14.4 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
14.4.1 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585
14.4.2 Operation mode and trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586
14.5 Operation in A/D Trigger Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
14.5.1 Select mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591
14.5.2 Scan mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594
14.6 Operation in Timer Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
14.6.1 Select mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596
14.6.2 Scan mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600
14.7 Operation in External Trigger Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
14.7.1 Select mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602
14.7.2 Scan mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 606
14.8 Precautions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608
Chapter 15 Asynchronous Serial Interface C (UARTC) . . . . . . . . . . . . . . . . . . . . . . . . 609
15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609
15.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .610