NEC uPD78F4225Y User manual

MOS INTEGRATED CIRCUIT
µ PD78F4225Y
16/8-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The µ PD78F4225Y is a product in the µ PD784225Y subseries in the 78K/IV series.
The µ PD78F4225YhasaflashmemoryintheplaceoftheinternalROMofthe µ PD784225Y. Datacanbewritten
toorerasedfromtheflashmemoryofthe µ PD78F4225Fwiththemicrocontrollermountedonaprintedwiringboard.
The
µ PD78F4225Y is based on the µ PD78F4225 with an I2C bus control function appended, and is ideal for
applications in audio visual.
The functions are explained in detail in the following user’s manuals. Be sure to read this manual when
designing your system.
µ PD784225, 784225Y Subseries User’s Manual - Hardware : Planned
78K/IV Series User’s Manual - Instruction : U10905E
FEATURES
•I
2
C bus serial interface supporting multi task
• Pin-compatible with mask ROM model (except VPP pin)
• Flash memory: 128K bytes
• Internal RAM : 4352 bytes
• Same operating voltage as mask ROM model: VDD = 1.8 to 5.5 V
ORDERING INFORMATION
Part Number Package
µ PD78F4225YGC-8BT 80-pin plastic QFP (14 ×14 mm)
µ PD78F4225YGK-BE9 80-pin plastic TQFP (fine pitch) (12 ×12 mm)
Document No. U12377EJ1V0PM00 (1st edition)
Date Published May 1997 N
Printed in Japan
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
©
1997
PRELIMINARY PRODUCT INFORMATION

2
µ PD78F4225Y
78K/IV Series Product Development
PD784026
µ
PD784038Y
µ
PD784038
µ
PD784915
µ
PD784928
µ
PD784928Y
µ
PD784054
µ
PD784216
µ
PD784225
µ
PD784216Y
µ
PD784225Y
µ
PD784046
µ
PD784908
µ
PD78F4943
µ
Enhaced A/D, 16-bit timer,
power management
Enhanced internal memory capacity,
pin-compatible with PD784026
µ
I2C bus compatible model
: Under mass production
: Under development
Multi-master I2C bus
compatible model Multi-master I2C bus compatible model
100 pins, enhanced I/O
and internal memory capacity80 pins
Enhanced functions of
PD784915
µ
With 10-bit A/D
For CD-ROM,
Flash memory: 56 KB
With software servo control,
analog circuit for VCRs,
enhanced timer
With IEBusTM controller

3
µ PD78F4225Y
FUNCTIONS
Item Function
Number of basic instructions 113
(mnemonics)
General-purpose register 8 bits ×16 registers ×8 banks, or 16 bits ×8 registers ×8 banks (memory mapping)
Minimum instruction execution • 160 ns/320 ns/640 ns/1280 ns/2560 ns (main system clock: fXX = 12.5 MHz)
time • 61 µ s (subsystem clock: fXX = 32.768 KHz)
Internal Flash memory 128 KBytes
memory RAM 4352 Bytes
Memory space 1 MB with program and data spaces combined
I/O port Total 67
CMOS Input 8
CMOS I/O 59
Pins with pull-up 57
resistor
LEDs direct 16
drive output
Real-time output port 4 bits ×2, or 8 bits ×1
Timer/counter 16-bit timer/counter : timer register ×1 Pulse output
Capture/compare register ×2 • PWM/PPG output
• Square wave output
• One-shot pulse output
8-bit timer/counter 1 : timer register ×1 Pulse output
Compare register ×1 • PWM output
• Square wave output
8-bit timer/counter 2 : timer register ×1 Pulse output
Compare register ×1 • PWM output
• Square wave output
8-bit timer/counter 5 : timer register ×1
Compare register ×1
8-bit timer/counter 6 : timer register ×1
Compare register ×1
Serial interface UART/IOE (3-wire serial I/O): 2 channels ( on-chip baud rate generator )
CSI (3-wire serial I/O, I2C bus supporting multi master): 1 channel
A/D converter 8-bit resolution ×8 channels
D/A converter 8-bit resolution ×2 channels
Clock output Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT
Buzzer output Selectable from fXX/210, fXX/211, fXX/212, fXX/213
Watch timer 1 channel
Watchdog timer 1 channel
Standby • HALT/STOP/IDLE mode
• In power-saving mode (with subsystem clock): HALT/IDLE mode
Interrupt Hardware 25 (internal: 18, external: 7)
Software BRK instruction, BRKCS instruction, operand error
Non-maskable Internal: 1, external: 1
Maskable Internal: 17, external: 6
• 4 programmable priority levels
• 3 service modes: vectored interrupt/macro service/context switching
Supply voltage VDD = 1.8 to 5.5 V
Package • 80-pin plastic QFP (14 ×14 mm)
• 80-pin plastic TQFP (fine pitch) (12 ×12 mm)
Note The pins with ancillary functions are included in the I/O pins.
Pins with
ancillary
functionsNote

4
µ PD78F4225Y
CONTENTS
1. DIFFERENCES AMONG MODELS IN µ PD784225Y SUBSERIES............................................. 5
2. PIN CONFIGURATION (Top View)............................................................................................... 6
3. BLOCK DIAGRAM ......................................................................................................................... 8
4. PIN FUNCTION............................................................................................................................... 9
4.1 Port Pins................................................................................................................................................ 9
4.2 Pins Other Than Port Pins .................................................................................................................. 11
4.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins ........... 13
5. INTERNAL MEMORY SIZE SELECT REGISTER (IMS).............................................................. 16
6. FLASH MEMORY PROGRAMMING ............................................................................................. 17
6.1 Selecting Communication Mode ........................................................................................................ 17
6.2 Flash Memory Programming Function ............................................................................................. 18
6.3 Connecting Flashpro II ........................................................................................................................ 18
7. PACKAGE DRAWINGS ................................................................................................................. 20
APPENDIX A. DEVELOPMENT TOOLS............................................................................................. 22
APPENDIX B. RELATED DOCUMENTS ............................................................................................ 24

5
µ PD78F4225Y
1. DIFFERENCES AMONG MODELS IN µ PD784225Y SUBSERIES
The only difference among the µ PD784224Y and 784225Y lies in the internal memory capacity.
The µ PD78P4225Yisprovidedwitha128-KBflashmemoryinsteadofthemaskROMoftheabovemodels. These
differences are summarized in Table 1-1.
Table 1-1. Differences among Models in
µ PD784225Y Subseries
Part Number
µ PD784224Y µ PD784225Y µ PD78F4225Y
Item
Internal ROM 96 KBytes 128 KBytes 128 KBytes
(mask ROM) (mask ROM) (flash memory)
Internal RAM 3584 Bytes 4352 Bytes
Internal memory size None Provided
switching register (IMS)
VPP pin None Provided

6
µ PD78F4225Y
2. PIN CONFIGURATION (Top View)
• 80-pin plastic QFP (14 ×14 mm)
µ PD78F4225YGC-8BT
• 80-pin plastic TQFP (fine pitch) (12 ×12 mm)
µ PD78F4225YGK-BE9
Notes 1. Directly connect the TEST/VPP pin to VSS0 in normal operation mode.
2. Connect the AVSS pin to VSS0.
Remark When using in applications where noise from inside the microcomputer has to be reduced, it is
recommended to take countermeasures against noise such as supplying power to VDD0 and VDD1
independently, and connecting VSS0 and VSS1 to different ground lines.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
P15/ANI5
P16/ANI6
P17/ANI7
AVSS
P130/ANO0
P131/ANO1
AVREF1
P70/SI2/RxD2
P71/SO2/TxD2
P72/SCK2/ASCK2
P20/SI1/RxD1
P21/SO1/TxD1
P22/SCK1/ASCK1
P23/PCL
P24/BUZ
P25/SI0/SDA0
P26/SO0
P27/SCK0/SCL0
P40/AD0
P41/AD1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RESET
P127/RTP7
P126/RTP6
P125/RTP5
P124/RTP4
P123/RTP3
P122/RTP2
P121/RTP1
P120/RTP0
P37/EXA
P36/TI01
P35/TI00
P34/TI2
P33/TI1
P32/TO2
P31/TO1
P30/TO0
P67/ASTB
P66/WAIT
P65/WR
P42/AD2 P43/AD3 P44/AD4 P45/AD5 P46/AD6 P47/AD7
P50/A8 P51/A9
P52/A10 P53/A11 P54/A12 P55/A13
VSS1
P56/A14 P57/A15 P60/A16 P61/A17 P62/A18 P63/A19
P64/RD
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P14/ANI4 P13/ANI3 P12/ANI2 P11/ANI1 P10/ANI0 AVDD VDD0 XT1 XT2 TEST/VPP X1 X2 VDD1 VSS0 P05/INTP5 P04/INTP4 P03/INTP3 P02/INTP2/NMI P01/INTP1 P00/INTP0
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

7
µ PD78F4225Y
A8-A19 : Address Bus
AD0-AD7 : Address/Data Bus
ANI0-ANI7 : Analog Input
ANO0, ANO1 : Analog Output
ASCK1, ASCK2 : Asynchronous Serial Clock
ASTB : Address Strobe
AVDD : Analog Power Supply
AVREF1 : Analog Reference Voltage
AVSS : Analog Ground
BUZ : Buzzer Clock
EXA : External Access Status Output
INTP0-INTP5 : Interrupt from Peripherals
NMI : Non-maskable Interrupt
P00-P05 : Port0
P10-P17 : Port1
P20-P27 : Port2
P30-P37 : Port3
P40-P47 : Port4
P50-P57 : Port5
P60-P67 : Port6
P70-P72 : Port7
P120-P127 : Port12
P130, P131 : Port13
PCL : Programmable Clock
RD : Read Strobe
RESET : Reset
RTP0-RTP7 : Real-time Output Port
RxD1, RxD2 : Receive Data
SCK0-SCK2 : Serial Clock
SCL0 : Serial Clock
SDA0 : Serial Data
SI0-SI2 : Serial Input
SO0-SO2 : Serial Output
TEST : Test
TI00, TI01, TI1-TI2 : Timer Input
TO0-TO2 : Timer Output
TxD1, TxD2 : Transmit Data
VDD0, VDD1 : Power Supply
VPP : Programming Power Supply
VSS0, VSS1 : Ground
WAIT : Wait
WR : Write Strobe
X1, X2 : Crystal (Main System Clock)
XT1, XT2 : Crystal (Subsystem Clock)

8
µ PD78F4225Y
3. BLOCK DIAGRAM
INTP2/NMI
INTP0, INTP1,
INTP3-INTP6
PROGRAMMABLE
INTERRUPT
CONTROLLER
REAL-TIME
OUTPUT PORT
TIMER/COUNTER6
(8 BITS)
TIMER/COUNTER5
(8 BITS)
TIMER/COUNTER2
(8 BITS)
TIMER/COUNTER1
(8 BITS)
TIMER/COUNTER
(16 BITS)
WATCH TIMER
WATCHDOG TIMER
TI00
TI01
TO0
TI1
TO1
TI2
TO2
RTP0-RTP7
CLOCK OUTPUT
CONTROL
A/D
CONVERTER
AV DD
AV SS
PCL
BUZ
ANI0-ANI7
D/A
CONVERTER
ANO0
AV SS
AV REF1
ANO1
78K/IV
CPU CORE
FLASH
MEMORY
RAM
BAUD-RATE
GENERATOR
RxD1/SI1
TxD1/SO1
ASCK1/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
SI0/SDA0
SO0
SCK0/SCL0
BUS I/F
UART/IOE1
RD
ASTB
WR
WAIT
AD0-AD7
A8-A15
A16-A19
PORT1 P10-P17
PORT0 P00-P05
PORT2 P20-P27
PORT3 P30-P37
PORT4 P40-P47
PORT5 P50-P57
PORT6 P60-P67
PORT7 P70-P72
PORT12 P120-P127
PORT13 P130,P131
BUZZER OUTPUT
SYSTEM CONTROL
RESET
XT2
X1
XT1
X2
V SS0 , V SS1
V DD0 , V DD1
TEST/V PP
CLOCKED
SERIAL
INTERFACE
BAUD-RATE
GENERATOR
UART/IOE2
EXA

9
µ PD78F4225Y
4. PIN FUNCTION
4.1 Port Pins (1/2)
Pin Name I/O Alternate Function Function
P00 I/O INTP0
P01 INTP1
P02 INTP2/NMI
P03 INTP3
P04 INTP4
P05 INTP5
P10-P17 Input ANI0-ANI7
P20 I/O RxD1/SI1
P21 TxD1/SO1
P22 ASCK1/SCK1
P23 PCL
P24 BUZ
P25 SI0/SDA0
P26 SO0
P27 SCK0/SCL0
P30 I/O TO0
P31 TO1
P32 TO2
P33 TI1
P34 TI2
P35 TI00
P36 TI01
P37 EXA
P40-P47 I/O AD0-AD7 Port 4 (P4):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• All pins set in input mode can be connected to internal pull-up
resistors by software.
• Can drive LEDs.
P50-P57 I/O A8-A15 Port 5 (P5):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• All pins set in input mode can be connected to internal pull-up
resistors by software.
• Can drive LEDs.
Port 1 (P1):
• 8-bit input port
Port 0 (P0):
• 6-bit I/O port
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up
resistors by software bit-wise.
Port 2 (P2):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up
resistors by software bit-wise.
Port 3 (P3):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up
resistors by software bit-wise.

10
µ PD78F4225Y
4.1 Port Pins (2/2)
Pin Name I/O Alternate Function Function
P60 I/O A16
P61 A17
P62 A18
P64 RD
P65 WR
P66 WAIT
P67 ASTB
P70 I/O RxD2/SI2
P71 TxD2/SO2
P72 ASCK2/SCK2
P120-P127 I/O RTP0-RTP7 Port 12 (P12):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up resistor
by software bit-wise.
P130, P131 I/O ANO0, ANO1 Port 13 (P13):
• 2-bit I/O port
• Can be set in input or output mode bit-wise.
Port 6 (P6):
• 8-bit I/O port
• Can be set in input or output mode bit-wise.
• All pins set in input mode can be connected to internal pull-up
resistors by software.
Port 7 (P7):
• 3-bit I/O port
• Can be set in input or output mode bit-wise.
• Pins set in input mode can be connected to internal pull-up resistor
by software bit-wise.

11
µ PD78F4225Y
4.2 Pins Other Than Port Pins (1/2)
Pin Name I/O Alternate Function Function
TI00 Input P35 External count clock input to 16-bit timer register
TI01 P36 Capture trigger signal input to capture/compare register 00
TI1 P33 External count clock input to 8-bit timer register 1
TI2 P34 External count clock input to 8-bit timer register 2
TO0 Output P30 16-bit timer output (shared by 14-bit PWM output)
TO1 P31 8-bit timer output (shared by 8-bit PWM output)
TO2 P32
RxD1 Input P20/SI1 Serial data input (UART1)
RxD2 P70/SI2 Serial data input (UART2)
TxD1 Output P21/SO1 Serial data output (UART1)
TxD2 P71/SO2 Serial data output (UART2)
ASCK1 Intput P22/SCK1 Baud rate clock input (UART1)
ASCK2 P72/SCK2 Baud rate clock input (UART2)
SI0 Input P25/SDA0 Serial data input (3-wire serial clock I/O0)
SI1 P20/RxD1 Serial data input (3-wire serial clock I/O1)
SI2 P70/RxD2 Serial data input (3-wire serial clock I/O2)
SO0 Output P26 Serial data output (3-wire serial I/O0)
SO1 P21/TxD1 Serial data output (3-wire serial I/O1)
SO2 P71/TxD2 Serial data output (3-wire serial I/O2)
SDA0 I/O P25/SI0 Serial data input/output (I2C bus)
SCK0 I/O P27/SCL0 Serial clock input/output (3-wire serial I/O0)
SCK1 P22/ASCK1 Serial clock input/output (3-wire serial I/O1)
SCK2 P72/ASCK2 Serial clock input/output (3-wire serial I/O2)
SCL0 P27/SCK0 Serial clock input/output (I2C bus)
NMI Input P02/INTP2 Non-maskable interrupt request input
INTP0 P00 External interrupt request input
INTP1 P01
INTP2 P02/NMI
INTP3 P03
INTP4 P04
INTP5 P05
PCL Output P23 Clock output (for trimming main system clock and subsystem clock)
BUZ Output P24 Buzzer output
RTP0-RTP7 Output P120-P127 Real-time output port that outputs data in synchronization with
trigger
AD0-AD7 I/O P40-P47 Low-order address/data bus when external memory is connected
A8-A15 Output P50-P57 Middle-order address bus when external memory is connected
A16-A19 P60-P63 High-order address bus when external memory is connected
RD Output P64 Strobe signal output for read operation of external memory
WR P65 Strobe signal output for write operation of external memory

12
µ PD78F4225Y
4.2 Pins Other Than Port Pins (2/2)
Pin Name I/O Alternate Function Function
WAIT Input P66 To insert wait state(s) when external memory is accessed
ASTB Output P67 Strobe output to externally latch address information output to ports
4 through 6 to access external memory
EXA Output P37 External access status output
RESET Input — System reset input
X1 Input — To connect main system clock oscillation crystal
X2 —
XT1 Input — To connect subsystem clock oscillation crystal
XT2 —
ANI0-ANI7 Input P10-P17 Analog voltage input for A/D converter
ANO0, ANO1 Output P130, P131 Analog voltage output for D/A converter
AVREF1 — — To apply reference voltage for D/A converter
AVDD Positive power supply for A/D converter. Connected to VDD0.
AVSS GND for A/D converter and D/A converter. Connected to VSS0.
VDD0 Positive power supply for port block
VSS0 GND potential for port block
VDD1 Positive power supply (except port block)
VSS1 GND potential (except port block)
TEST VPP Directly connect this pin to VSS (this pin is for IC test).
VPP TEST Sets flash memory programming mode.
To apply a high voltage when program is written or verified.

13
µ PD78F4225Y
4.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins
Table4-1 shows symbols indicating the I/O circuit types of the respective pins andthe recommended connection
of unused pins.
For the circuit diagram of each type of I/O circuit, refer to Figure 4-1.
Table 4-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (1/2)
Pin Name I/O Circuit Type I/O Recommended Connections of Unused Pins
P00/INTP0 8-C I/O Input : Individually connected to VSS0 via resistor
P01/INTP1 Output: Open
P02/INTP2/NMI
P03/INTP3-P05/INTP5
P10/ANI0-P17/ANI7 9 Input Connected to VSS0 or VDD0
P20/RxD1/SI1 10-B I/O Input : Individually connected to VSS0 via resistor
P21/TxD1/SO1 Output: Open
P22/ASCK1/SCK1
P23/PCL
P24/BUZ
P25/SDA0/SI0
P26/SO0
P27/SCL0/SCK0
P30/TO0-P32/TO2 8-C
P33/TI1, P34/TI2
P35/TI00, P36/TI01
P37/EXA
P40/AD0-P47/AD7 5-H
P50/A8-P57/A15
P60/A16-P63/A19
P64/RD
P65/WR
P66/WAIT
P67/ASTB
P70/RxD2/SI2 8-C
P71/TxD2/SO2
P72/ASCK2/SCK2
P120/RTP0-P127/RTP7
P130/ANO0, P131/ANO1 12-C

14
µ PD78F4225Y
Table 4-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (2/2)
Pin Name I/O Circuit Type I/O Recommended Connections of Unused Pins
RESET 2 Input —
XT1 16 Connected to VSS0
XT2 — Open
AVREF1 — Connected to VDD0
AVDD
AVSS Connected to VSS0
TEST/VPP Directly connected to VSS0
Remark Because the circuit type numbers are standardized among the 78K series products, they are not
sequential in some models (i.e., some circuits are not provided).

15
µ PD78F4225Y
Figure 4-1. Types of Pin I/O Circuits
Type 2
IN
Schmitt trigger input with hysteresis characteristics
Type 5-H
pullup
enable
data
output
disable
input
enable
V
DD0
P-ch
V
DD0
P-ch
IN/OUT
N-ch
Type 8-C
pullup
enable
data
output
disable
V
DD0
P-ch
V
DD0
P-ch
IN/OUT
N-ch
Type 9
pullup
enable
data
open drain
output disable
V DD0
P-ch
V
DD0
P-ch
IN/OUT
N-ch
Type 10-B
Type 12-C
pullup
enable
data
output
disable
input
enable Analog output
voltage
V
DD0
P-ch
V
DD0
P-ch
IN/OUT
N-ch
P-ch
N-ch
Type 16
feedback
cut-off
P-ch
XT1 XT2
IN Comparator
+
–
V REF
(threshold voltage)
P-ch
N-ch
input
enable
V SS0
V SS0
V SS0
V SS0
V SS0

16
µ PD78F4225Y
5. INTERNAL MEMORY SIZE SELECT REGISTER (IMS)
The IMS is a register that prevents by software a part of the internal memory from being used. By using this
register,the memory of the µ PD78F4225Ycan be mapped inthe same manneras a mask ROMmodel with different
internal memory (ROM and RAM) capacity.
This register is set by using an 8-bit memory manipulation instruction.
Its value is set to FFH by RESET input.
Figure 5-1. Format of Internal Memory Size Select Register (IMS)
Caution IMS is not provided on the mask ROM models (
µ PD784224Y and 784225Y).
The value to be set to the IMS to map the memory of the
µ PD78F4225Y in the same manner as the mask ROM
model is shown in Table 5-1.
Table 5-1. Set Value of Internal Memory Size Select Register (IMS)
Mask ROM Model Set Value of IMS
µ PD784225Y EEH
µ PD784226Y FFH
1 1 ROM1 ROM0 1 1 RAM1 RAM0
76543210
ROM1
0
0
1
1
ROM0
0
1
0
1
Selects internal ROM capacity
48K bytes
64K bytes
96K bytes
128K bytes
RAM1
0
0
1
1
RAM0
0
1
0
1
Selects peripheral RAM capacity
1536 bytes
2304 bytes
3072 bytes
3840 bytes
Address: 0FFFCH
IMS
At reset: FFH W

17
µ PD78F4225Y
6. PROGRAMMING FLASH MEMORY
The flash memory can be written with the µ PD78F4225Y mounted on the target board (on-board). To do so,
connect a dedicated flash writer (Flashpro II) to the host machine and target system.
Remark Flashpro II is a product of Naito Densei Machida Mfg. Co., Ltd.
6.1 Selecting Communication Mode
To write the flash memory, use Flashpro II and serial communication. Select a serial communication mode from
those listed in Table 6-1 in the format shown in Figure 6-1. Each communication mode is selected by the number
of VPP pulses shown in Table 6-1.
Table 6-1. Communication Modes
Communication Mode Number of Channels Pins Used Number of VPP Pulses
3-wire serial I/O 3 SCK0/SCL0/P27 0
SO0/P26
SI0/SDA0/P25
SCK1/ASCK1/P22 1
SO1/TxD1/P21
SI1/RxD1/P20
SCK2/ASCK2/P72 2
SO2/TxD2/P71
SI2/RxD2/P70
I2C bus 1 SCL0/SCK0/P27 4
SDA0/SI0/P25
UART 2 TxD1/SO1/P21 8
RxD1/SI1/P20
TxD2/SO2/P71 9
RxD2/SI2/P70
Psendo-3-wire serial 1 P32/TO2 12
I/ONote (serial clock I/O)
P31/TO1
(serial data output)
P30/TO0
(serial data output)
Note Performs serial transfer by controlling port by software.
Caution Be sure to select a communication mode with the number of VPP pulses shown in Table 6-1.
Figure 6-1. Communication Mode Selecting Format
12 n
10 V
V
DD
V SS
V PP
V DD
V SS
RESET

18
µ PD78F4225Y
6.2 Flash Memory Programming Function
The flash memory is written by transferring or receiving commands and data in a selected communication mode.
The major functions of flush memory programming are listed in Table 6-2.
Table 6-2. Major Functions of Flash Memory Programming
Function Description
Batch erasure Erases all contents of memory.
Block erasure Erases contents of specified memory block.
Batch blank check Checks erased status of entire memory.
Block blank check Checks erased status of specified block
Data write Writes flash memory based on write start address and number of data to be
written (in bytes).
Batch verify Compares all contents of memory with input data.
Block verify Compares contents of specified memory block with input data.
6.3 Connecting Flashpro II
The Flashpro II and µ PD78F4225Y are connected differently depending on the selected communication mode.
Figures 6-2 through 6-5 show the connections in the respective communication modes.
Figure 6-2. Connection of Flashpro II in 3-Wire Serial I/O Mode (When Using 3-Wire Serial I/O 0)
Flashpro II PD78F4225Y µ
V PP n
Note
V DD
V SS
RESET
SCK
SO
SI
V PP
V DD0 , V DD1
V SS0 , V SS1
RESET
SCK0
SI0
SO0
Note n = 1
,
2

19
µ PD78F4225Y
Figure 6-3. Connection of Flashpro II in I2C Bus Mode
Figure 6-4. Connection of Flashpro II in UART Mode (When Using UART1)
Figure 6-5. Connection of Flashpro II in Pseudo-3-Wire Serial I/O Mode
Flashpro II PD78F4225Y µ
V PP n
Note
V DD
V SS
RESET
SCK
SI
V PP
V DD0 , V DD1
V SS0 , V SS1
RESET
SCL0
SDA0
Note n = 1
,
2
Flashpro II PD78F4225Y µ
V PP n
Note
V DD
V SS
RESET
SO
SI
V PP
V DD0 , V DD1
V SS0 , V SS1
RESET
R X D1
Note n = 1
,
2
T X D1
Flashpro II PD78F4225Y µ
V PP n
Note
V DD
V SS
RESET
SCK
SO
SI
V PP
V DD0 , V DD1
V SS0 , V SS1
RESET
P32 (serial clock)
P30 (serial input)
P31 (serial output)
Note n = 1, 2

20
µ PD78F4225Y
7. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14×14)
ITEM MILLIMETERS INCHES
NOTE
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
P80GC-65-8BT
F 0.825 0.032
B 14.00±0.20 0.551+0.009
–0.008
S 1.70 MAX. 0.067 MAX.
M 0.17 0.007+0.001
–0.003
+0.03
–0.07
+0.009
–0.008
C 14.00±0.20 0.551+0.009
–0.008
A 17.20±0.20 0.677±0.008
G 0.825 0.032
H 0.32±0.06 0.013+0.002
–0.003
I 0.13 0.005
J 0.65 (T.P.) 0.026 (T.P.)
K 1.60±0.20 0.063±0.008
L 0.80±0.20 0.031+0.009
–0.008
N 0.10 0.004
P 1.40±0.10 0.055±0.004
Q 0.125±0.075 0.005±0.003
R3°3°
+7°
–3°
+7°
–3°
D 17.20±0.20 0.677±0.008
4160 4061
2180 201
M
S
QR
KM
L
A
B
C D
J
HI
F
G
P
N
detail of lead end