NEC mPD780973 Series User manual

µ PD780973 Subseries
8-Bit Single-Chip Microcontrollers
µ PD780973(A)
µ PD78F0974
Document No. U12406EJ2V0UM00 (2nd edition)
Date Published May 1998 N CP(K)
1997
Preliminary User’s Manual
Printed in Japan
©

2
[MEMO]

3
EEPROM, FIP, and IEBus are trademarks of NEC Corporation.
Windows and WindowsNT are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
Ethernet is a trademark of Xerox Corporation.
NEWS and NEWS-OS are trademarks of Sony Corporation.
OSF/Motif is a trademark of OpenSoftware Foundation, Inc.
TRON is an abbreviation of The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimatelydegradethedeviceoperation. Stepsmustbetakentostopgenerationofstaticelectricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulatorsthateasilybuildstaticelectricity. Semiconductordevicesmustbestoredandtransported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wriststrap. Semiconductordevicesmustnotbetouchedwith barehands. Similar precautionsneed
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
totheinputpins, it is possible that aninternalinputlevelmaybegenerated due to noise, etc., hence
causingmalfunction. CMOSdevicesbehave differentlythan BipolarorNMOSdevices. Inputlevels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

4
The information in this document is subject to change without notice.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
fromuseofsuchdevice. Nolicense,eitherexpress,impliedorotherwise,isgrantedunderanypatents,copyrights
or other intellectual property rights of NEC Corporation or others.
WhileNECCorporationhas beenmaking continuousefforttoenhancethereliabilityof itssemiconductordevices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
adevice depend on its qualitygrade, as indicated below. Customers mustcheck the quality grade ofeach device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M7 96.5
This product is produced and sold based on the licensed agreement with CP8 Transac concerning EEPROM-
contained microcontroller.
This product cannot be used for an IC card (SMART CARD).
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
License not needed : µ PD78F0974GF-3B9
The customer must judge the need for license :
µ PD780973GF(A)-×××-3B9
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products
may be prohibited without governmental license. To export or re-export some or all of these products from a country other than
Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

5
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: [phone]
800-366-9782
Fax: [phone]
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: [phone]
Fax: [phone]
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: [phone]
Fax: [phone]
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: [phone]
Fax: [phone]
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel:[phone]
Fax: [phone]
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: [phone]
Fax: [phone]
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel:[phone]
Fax: [phone]
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: [phone]
Fax: [phone]
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil
Tel: [phone]
Fax: [phone]
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel:[phone]
Fax: [phone]
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel:[phone]
Fax: [phone]
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: [phone]
Fax: [phone]
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: [phone]
Fax: [phone]
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
J98. 2

6
MAJOR REVISIONS IN THIS EDITION (1/2)
Page Description
p.38 Table 2-1. Pin Input/Output Circuit Types
Correction of ports 8 and 9 input/output circuit types
p.40 Figure 2-1. I/O Circuits of Pins
Change of type 17-A to type 17-G
p.54 Addition of oscillator mode register to Table 3-5. Special Function Register List
p.67 4.1 EEPROM Functions
Change of the number of rewrite frequency per 1 byte as follows:
10,000 times →100,000 times
p.77 5.2.3 Port 2
• Correction of description
• Correction of Figure 5-4. P20 to P27 Block Diagram
p.78 5.2.4 Port 3
• Correction of description
• Correction of Figure 5-5. P30 to P37 Block Diagram
p.82 5.2.8 Port 8
• Correction of description
• Addition of Figure 5-9. P81 Block Diagram
• Correction of Figure 5-10. P82 to P87 Block Diagram
p.83 5.2.9 Port 9
• Correction of description
• Correction of Figure 5-11. P90 to P97 Block Diagram
p.85 Table 5-3. Port Mode Register and Output Latch Settings when Using Alternate Functions
• Change of P×× setting values of P20 to P27 and P30 to P37 from 0 to ×
• Change of Note 2
p.86 Addition of Note in Figure 5-13. Port Mode Register (PM2, PM3) Format
p.89 CHAPTER 6 CLOCK GENERATOR
• Addition of oscillator mode register to Table 6-1. Clock Generator Configuration
• Change of Figure 6-1. Clock Generator Block Diagram
• Addition of (2) Oscillator mode register (OSCM) to 6.3 Clock Generator Control Register
• Addition of explanation of oscillator mode register to 6.5 Operation of Clock Generator
p.163 13.6 Cautions on Emulation
Change of in-circuit emulator of (1) D/A converter mode register (DAM1) as follows:
IE-78001-R-A →IE78K0-NS
Addition of (2) A/D converter of IE-780974-NS-EM1
p.203 16.9 Cautions on Emulation
Change of in-circuit emulator of (1) LCD timer control register (LCDTM) as follows:
IE-78001-R-A →IE78K0-NS
p.205 17.1 Sound Generator Function
Correction of description on (1) Basic cycle output signal (with/without amplitude)
p.214 18.2 Meter Controller/Driver Configuration
Addition of Cautions to (1) Free running up counter (MCNT)
p.247 Table 20-1. HALT Mode Operating Status
Correction of HALT mode operating status of A/D converter
Operable →Operation stops
The mark shows major revised points.

7
MAJOR REVISIONS IN THIS EDITION (2/2)
Page Description
p.255 Addition of oscillator mode register to Table 21-1. Hardware Status after Reset
p.257 Change of Note in Table 22-1. Differences between µ PD78F0974 and µ PD780973(A)
p.279 APPENDIX A DEVELOPMENT TOOLS
• Support of in-circuit emulator IE-78K0-NS
• Change in supported OS
• Addition of A.4 Upgrading Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A
• Deletion of OS for IBM PC from previous edition
• Deletion of Development Environment when Using IE-78000-R-A from previous edition
p.291 APPENDIX B EMBEDDED SOFTWARE
• Change in supported OS
• Deletion of Fuzzy Inference Development Support System from previous edition
The mark shows major revised points.

8
INTRODUCTION
Readers Thismanual has been prepared foruser engineers who want tounderstand the functions
of the µ PD780973 Subseries and design and develop its application systems and
programs.
Purpose This manual is designed to help users understand the following functions using the
organization below.
Organization The
µ PD780973 Subseries manual is separated into two parts: this manual and the
instruction edition (common to the 78K/0 Series).
µ PD780973 Subseries 78K/0 Series
User’s Manual User’s Manual
(This Manual) Instructions
• Pin functions • CPU functions
• Internal block functions • Instruction set
• Interrupt • Explanation of each instruction
• Other on-chip peripheral functions
How to Read This Manual This manual assumes general knowledge of electric engineering, logic circuits, and
microcontrollers.
• To understand the functions of the
µ PD780973(A) and 78F0974 in general:
→Read this manual in the order of the CONTENTS.
• How to read register formats:
→The name of a bit whose number is enclosed in square is reserved for the RA78K/
0 and is defined for the CC78K/0 by the header file sfrbit.h.
• To learn the detailed functions of a register whose register name is known:
→Refer to APPENDIX C REGISTER INDEX.
The application examples in this manual are for the “standard” model for general-
purpose electronic systems. If the examples in this manual are to be used for
applications where a quality higher than that of the “special” model is required, study
the quality grade of the respective components and circuits actually used.
Conventions Data significance : Higher digits on the left and lower digits on the right
Active low representation : ××× (overscore over pin or signal name)
Note : Footnote for item marked with Note in the text
Caution : Information requiring particular attention
Remark : Supplementary information
Numerical representation : Binary ··· ×××× or ××××B
Decimal ··· ××××
Hexadecimal ··· ××××H

9
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
• Related documents for
µ PD780973 Subseries
Document Name Document No.
Japanese English
µ PD780973(A) Preliminary Product Information U12759J U12759E
µ PD78F0974 Preliminary Product Information U12646J U12646E
µ PD780973 Subseries User’s Manual U12406J This manual
78K/0 Series User’s Manual Instructions U12326J U12326E
78K/0 Series Instruction Table U10903J —
78K/0 Series Instruction Set U10904J —
µ PD780973 Subseries Special Function Register Table U12748J —
• Related documents for development tool (User’s Manual)
Document Name Document No.
Japanese English
RA78K0 Assembler Package Operation U11802J U11802E
Assembly Language U11801J U11801E
Structured Assembly Language U11789J U11789E
RA78K Series Structured Assembler Preprocessor EEU-817 EEU-1402
CC78K0 C Compiler Operation U11517J U11517E
Language U11518J U11518E
CC78K/0 C Compiler Application Note Programming Know-how U13034J EEA-1208
CC78K Series Library Source File U12322J —
IE-78K0-NS To be prepared To be prepared
IE-78001-R-A To be prepared To be prepared
SM78K0 System Simulator WindowsTM Base Reference U10181J U10181E
SM78K Series System Simulator External Part User Open U10092J U10092E
Interface Specifications
ID78K0-NS Integrated Debugger PC Base Reference U12900J To be prepared
ID78K0 Integrated Debugger EWS Base Reference U11151J —
ID78K0 Integrated Debugger PC Base Reference U11539J U11539E
ID78K0 Integrated Debugger Windows Base Guide U11649J U11649E
Caution The above documents are subject to change without prior notice. Be sure to use the latest
version of a document when starting design.

10
• Related documents for embedded software (User’s Manual)
Document Name Document No.
Japanese English
78K/0 Series Real-Time OS Basics U11537J U11537E
Installation U11536J U11536E
78K/0 Series OS MX78K0 Basics U12257J U12257E
• Other related documents
Document Name Document No.
Japanese English
IC Package Manual C10943X
Semiconductor Device Mounting Technology Manual C10535J C10535E
Quality Grades on NEC Semiconductor Devices C11531J C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983J C10983E
Guide to Prevent Damage for Semiconductor Devices by Electro Static Discharge (ESD) C11892J C11892E
Guide to Quality Assurance for Semiconductor Devices — MEI-1202
Microcomputer Product Series Guide U11416J —
Caution The above documents are subject to change without prior notice. Be sure to use the latest
version of a document when starting design.

11
CONTENTS
CHAPTER 1 OUTLINE .................................................................................................................... 23
1.1 Features................................................................................................................................ 23
1.2 Applications ......................................................................................................................... 23
1.3 Ordering Information........................................................................................................... 24
1.4 Quality Grade ....................................................................................................................... 24
1.5 Pin Configuration (Top View) ............................................................................................. 25
1.6 78K/0 Series Product Development ................................................................................... 27
1.7 Block Diagram...................................................................................................................... 29
1.8 Outline of Function.............................................................................................................. 30
CHAPTER 2 PIN FUNCTION.......................................................................................................... 31
2.1 Pin Function List.................................................................................................................. 31
2.2 Description of Pin Functions.............................................................................................. 33
2.2.1 P00 to P07 (Port 0) ..................................................................................................................... 33
2.2.2 P10 to P14 (Port 1) ..................................................................................................................... 33
2.2.3 P20 to P27 (Port 2) ..................................................................................................................... 33
2.2.4 P30 to P37 (Port 3) ..................................................................................................................... 34
2.2.5 P40 to P44 (Port 4) ..................................................................................................................... 34
2.2.6 P50 to P54 (Port 5) ..................................................................................................................... 34
2.2.7 P60, P61 (Port 6) ........................................................................................................................ 35
2.2.8 P81 to P87 (Port 8) ..................................................................................................................... 35
2.2.9 P90 to P97 (Port 9) ..................................................................................................................... 36
2.2.10 COM0 to COM3 .......................................................................................................................... 36
2.2.11 VLCD............................................................................................................................................. 36
2.2.12 AVREF .......................................................................................................................................... 36
2.2.13 AVSS ............................................................................................................................................ 36
2.2.14 RESET........................................................................................................................................ 36
2.2.15 X1 and X2 ................................................................................................................................... 36
2.2.16 SMVDD......................................................................................................................................... 36
2.2.17 SMVSS ......................................................................................................................................... 36
2.2.18 VDD .............................................................................................................................................. 36
2.2.19 VSS .............................................................................................................................................. 36
2.2.20 VPP (
µ PD78F0974)......................................................................................................................37
2.2.21 IC (
µ PD780973(A)) ..................................................................................................................... 37
2.3 Input/output Circuits and Recommended Connection of Unused Pins ......................... 38
CHAPTER 3 CPU ARCHITECTURE .............................................................................................. 41
3.1 Memory Spaces ................................................................................................................... 41
3.1.1 Internal program memory space................................................................................................. 43
3.1.2 Internal data memory space ....................................................................................................... 44
3.1.3 Special function register (SFR) area........................................................................................... 44
3.1.4 Data memory addressing............................................................................................................ 45
3.2 Processor Registers............................................................................................................ 47
3.2.1 Control registers ......................................................................................................................... 47
3.2.2 General registers ........................................................................................................................ 50

12
3.2.3 Special function registers (SFRs) ............................................................................................... 51
3.3 Instruction Address Addressing ........................................................................................ 55
3.3.1 Relative addressing .................................................................................................................... 55
3.3.2 Immediate addressing ................................................................................................................ 56
3.3.3 Table indirect addressing ............................................................................................................ 57
3.3.4 Register addressing.................................................................................................................... 57
3.4 Operand Address Addressing............................................................................................ 58
3.4.1 Implied addressing...................................................................................................................... 58
3.4.2 Register addressing.................................................................................................................... 59
3.4.3 Direct addressing........................................................................................................................ 60
3.4.4 Short direct addressing............................................................................................................... 61
3.4.5 Special-function register (SFR) addressing ................................................................................ 62
3.4.6 Register indirect addressing ....................................................................................................... 63
3.4.7 Based addressing ....................................................................................................................... 64
3.4.8 Based indexed addressing ......................................................................................................... 64
3.4.9 Stack addressing ........................................................................................................................ 65
CHAPTER 4 EEPROM..................................................................................................................... 67
4.1 EEPROM Functions .............................................................................................................67
4.2 EEPROM Configuration....................................................................................................... 68
4.3 EEPROM Control Register .................................................................................................. 69
4.4 EEPROM Reading ................................................................................................................ 70
4.5 EEPROM Writing.................................................................................................................. 71
4.6 EEPROM Control-Related Interrupt ................................................................................... 71
4.7 Cautions regarding EEPROM Writing................................................................................ 72
CHAPTER 5 PORT FUNCTIONS ................................................................................................... 73
5.1 Port Functions ..................................................................................................................... 73
5.2 Port Configuration ............................................................................................................... 75
5.2.1 Port 0 .......................................................................................................................................... 75
5.2.2 Port 1 .......................................................................................................................................... 76
5.2.3 Port 2 .......................................................................................................................................... 77
5.2.4 Port 3 .......................................................................................................................................... 78
5.2.5 Port 4 .......................................................................................................................................... 79
5.2.6 Port 5 .......................................................................................................................................... 80
5.2.7 Port 6 .......................................................................................................................................... 81
5.2.8 Port 8 .......................................................................................................................................... 82
5.2.9 Port 9 .......................................................................................................................................... 83
5.3 Port Function Control Registers ........................................................................................ 84
5.4 Port Function Operations ................................................................................................... 88
5.4.1 Writing to input/output port.......................................................................................................... 88
5.4.2 Reading from input/output port ................................................................................................... 88
5.4.3 Operations on input/output port .................................................................................................. 88
CHAPTER 6 CLOCK GENERATOR .............................................................................................. 89
6.1 Clock Generator Functions................................................................................................. 89
6.2 Clock Generator Configuration .......................................................................................... 89
6.3 Clock Generator Control Register...................................................................................... 90

13
6.4 System Clock Oscillator......................................................................................................92
6.4.1 Main system clock oscillator ....................................................................................................... 92
6.4.2 Divider circuit .............................................................................................................................. 94
6.5 Operation of Clock Generator ............................................................................................ 95
6.6 Changing Setting of CPU Clock ......................................................................................... 96
6.6.1 Time required for switching CPU clock ....................................................................................... 96
6.6.2 Switching CPU clock................................................................................................................... 97
CHAPTER 7 16-BIT TIMER 0 TM0............................................................................................... 99
7.1 Outline of Internal Timer of µ PD780973 Subseries........................................................... 99
7.2 16-Bit Timer 0 Functions..................................................................................................... 100
7.3 16-Bit Timer 0 Configuration .............................................................................................. 102
7.4 16-Bit Timer 0 Control Registers........................................................................................ 103
7.5 16-Bit Timer 0 Operations ................................................................................................... 106
7.5.1 Pulse width measurement operations......................................................................................... 106
7.6 16-Bit Timer 0 Cautions....................................................................................................... 109
CHAPTER 8 8-BIT TIMER 1 TM1................................................................................................. 111
8.1 8-Bit Timer 1 Functions....................................................................................................... 111
8.2 8-Bit Timer 1 Configuration ................................................................................................ 112
8.3 8-Bit Timer 1 Control Registers.......................................................................................... 113
8.4 8-Bit Timer 1 Operations ..................................................................................................... 115
8.4.1 8-bit interval timer operation ....................................................................................................... 115
8.5 8-Bit Timer 1 Cautions......................................................................................................... 118
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 2, 3 TM2, TM3 .............................................. 119
9.1 8-Bit Timer/Event Counters 2 and 3 Functions................................................................. 119
9.2 8-Bit Timer/Event Counters 2 and 3 Configurations ........................................................ 121
9.3 8-Bit Timer/Event Counters 2 and 3 Control Registers.................................................... 122
9.4 8-Bit Timer/Event Counters 2 and 3 Operations ............................................................... 125
9.4.1 8-bit interval timer operation ....................................................................................................... 125
9.4.2 External event counter operation................................................................................................ 127
9.4.3 Square-wave output operation (8-bit resolution)......................................................................... 128
9.4.4 8-bit PWM output operation ........................................................................................................ 129
9.5 8-Bit Timer/Event Counters 2 and 3 Cautions................................................................... 132
CHAPTER 10 WATCH TIMER.......................................................................................................... 133
10.1 Watch Timer Functions ....................................................................................................... 133
10.2 Watch Timer Configuration................................................................................................. 134
10.3 Watch Timer Control Register ............................................................................................ 135
10.4 Watch Timer Operations ..................................................................................................... 136
10.4.1 Watch timer operation................................................................................................................. 136
10.4.2 Interval timer operation ............................................................................................................... 136
CHAPTER 11 WATCHDOG TIMER ................................................................................................. 139
11.1 Watchdog Timer Functions ................................................................................................ 139
11.2 Watchdog Timer Configuration .......................................................................................... 141
11.3 Watchdog Timer Control Registers ................................................................................... 141

14
11.4 Watchdog Timer Operations............................................................................................... 143
11.4.1 Watchdog timer operation........................................................................................................... 143
11.4.2 Interval timer operation ............................................................................................................... 144
CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT .................................................................. 145
12.1 Clock Output Control Circuit Functions ............................................................................ 145
12.2 Clock Output Control Circuit Configuration ..................................................................... 145
12.3 Clock Output Control Circuit Control Registers ............................................................... 146
12.4 Clock Output Control Circuit Operation ............................................................................ 148
12.4.1 Clock output operation................................................................................................................ 148
CHAPTER 13 A/D CONVERTER ..................................................................................................... 149
13.1 A/D Converter Functions .................................................................................................... 149
13.2 A/D Converter Configuration .............................................................................................. 150
13.3 A/D Converter Control Registers ....................................................................................... 152
13.4 A/D Converter Operations................................................................................................... 155
13.4.1 Basic operations of A/D converter .............................................................................................. 155
13.4.2 Input voltage and conversion results .......................................................................................... 157
13.4.3 A/D converter operation mode.................................................................................................... 158
13.5 A/D Converter Cautions ...................................................................................................... 160
13.6 Cautions on Emulation........................................................................................................ 163
CHAPTER 14 SERIAL INTERFACE UART .................................................................................... 165
14.1 UART Functions................................................................................................................... 165
14.2 UART Configuration ............................................................................................................ 166
14.3 UART Control Registers...................................................................................................... 167
14.4 UART Operations ................................................................................................................. 171
14.4.1 Operation stop mode .................................................................................................................. 171
14.4.2 Asynchronous serial interface (UART) mode ............................................................................. 171
CHAPTER 15 SERIAL INTERFACE SIO3 ...................................................................................... 183
15.1 SIO3 Functions .................................................................................................................... 183
15.2 SIO3 Configuration .............................................................................................................. 184
15.3 SIO3 Control Register ......................................................................................................... 185
15.4 SIO3 Operations................................................................................................................... 186
15.4.1 Operation stop mode .................................................................................................................. 186
15.4.2 Three-wire serial I/O mode ......................................................................................................... 187
CHAPTER 16 LCD CONTROLLER/DRIVER ................................................................................... 189
16.1 LCD Controller/Driver Functions........................................................................................ 189
16.2 LCD Controller/Driver Configuration ................................................................................. 190
16.3 LCD Controller/Driver Control Registers........................................................................... 192
16.4 LCD Controller/Driver Settings........................................................................................... 194
16.5 LCD Display Data Memory .................................................................................................. 195
16.6 Common Signals and Segment Signals ............................................................................ 196
16.7 Supplying LCD Drive Voltage VLC0, VLC1, and VLC2 ........................................................... 198
16.8 Display Mode........................................................................................................................ 200
16.8.1 4-time-division display example.................................................................................................. 200

15
16.9 Cautions on Emulation........................................................................................................ 203
CHAPTER 17 SOUND GENERATOR .............................................................................................. 205
17.1 Sound Generator Function ................................................................................................. 205
17.2 Sound Generator Configuration ......................................................................................... 206
17.3 Sound Generator Control Registers .................................................................................. 207
17.4 Sound Generator Operations ............................................................................................. 212
17.4.1 To output basic cycle signal SGOF (without amplitude) ............................................................. 212
17.4.2 To output basic cycle signal SGO (with amplitude)..................................................................... 212
CHAPTER 18 METER CONTROLLER/DRIVER .............................................................................. 213
18.1 Meter Controller/Driver Functions ..................................................................................... 213
18.2 Meter Controller/Driver Configuration ............................................................................... 214
18.3 Meter Controller/Driver Control Registers ........................................................................ 216
18.4 Meter Controller/Driver Operations.................................................................................... 220
18.4.1 Basic operation of free-running up counter (MCNT)................................................................... 220
18.4.2 To update PWM data .................................................................................................................. 220
18.4.3 Operation of 1-bit addition circuit ................................................................................................ 221
18.4.4 PWM output operation (output with 1 clock shifted) ................................................................... 222
CHAPTER 19 INTERRUPT FUNCTIONS......................................................................................... 223
19.1 Interrupt Function Types .................................................................................................... 223
19.2 Interrupt Sources and Configuration................................................................................. 223
19.3 Interrupt Function Control Registers................................................................................. 227
19.4 Interrupt Servicing Operations ........................................................................................... 234
19.4.1 Non-maskable interrupt request acknowledge operation ........................................................... 234
19.4.2 Maskable interrupt request acknowledge operation ................................................................... 237
19.4.3 Software interrupt request acknowledge operation .................................................................... 239
19.4.4 Multiple interrupt servicing .......................................................................................................... 240
19.4.5 Interrupt request hold.................................................................................................................. 243
CHAPTER 20 STANDBY FUNCTION .............................................................................................. 245
20.1 Standby Function and Configuration ................................................................................ 245
20.1.1 Standby function ......................................................................................................................... 245
20.1.2 Standby function control register ................................................................................................ 246
20.2 Standby Function Operations ............................................................................................ 247
20.2.1 HALT mode ................................................................................................................................. 247
20.2.2 STOP mode ................................................................................................................................ 250
CHAPTER 21 RESET FUNCTION.................................................................................................... 253
21.1 Reset Function ..................................................................................................................... 253
CHAPTER 22 µ PD78F0974 ............................................................................................................... 257
22.1 Memory Size Switching Register ....................................................................................... 258
22.2 Flash Memory Programming .............................................................................................. 259
22.2.1 Selection of transmission method............................................................................................... 259
22.2.2 Flash memory programming function ......................................................................................... 260
22.2.3 Flashpro II connection ................................................................................................................ 260

16
CHAPTER 23 INSTRUCTION SET................................................................................................... 263
23.1 Legend for Operation List ................................................................................................... 264
23.1.1 Operand identifiers and description formats ............................................................................... 264
23.1.2 Description of “operation” column............................................................................................... 265
23.1.3 Description of “flag operation” column ........................................................................................ 265
23.2 Operation List ...................................................................................................................... 266
23.3 Instructions Listed by Addressing Type ........................................................................... 274
APPENDIX A DEVELOPMENT TOOLS .......................................................................................... 279
A.1 Language Processing Software ......................................................................................... 282
A.2 Flash Memory Writing Tools............................................................................................... 283
A.3 Debugging Tools ................................................................................................................. 284
A.3.1 Hardware .................................................................................................................................... 284
A.3.2 Software...................................................................................................................................... 286
A.4 Upgrading Former In-circuit Emulator for 78K/0 Series to IE-78001-R-A....................... 288
APPENDIX B EMBEDDED SOFTWARE ......................................................................................... 291
APPENDIX C REGISTER INDEX..................................................................................................... 293
C.1 Register Index (In Alphabetical Order with Respect to Register Name) ........................ 293
C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ..................... 296
APPENDIX D REVISION HISTORY .................................................................................................. 299

17
LIST OF FIGURES (1/4)
Figure No. Title Page
2-1. I/O Circuits of Pins ............................................................................................................................ 39
3-1. Memory Map (
µ PD780973(A)).......................................................................................................... 41
3-2. Memory Map (
µ PD78F0974) ............................................................................................................ 42
3-3. Data Memory Addressing (
µ PD780973(A)) ...................................................................................... 45
3-4. Data Memory Addressing (
µ PD78F0974)......................................................................................... 46
3-5. Program Counter Configuration ........................................................................................................ 47
3-6. Program Status Word Configuration ................................................................................................. 47
3-7. Stack Pointer Configuration .............................................................................................................. 49
3-8. Data to be Saved to Stack Memory .................................................................................................. 49
3-9. Data to be Reset from Stack Memory............................................................................................... 49
3-10. General Register Configuration ........................................................................................................ 50
4-1. EEPROM Block Diagram .................................................................................................................. 68
4-2. EEPROM Write Control Register (EEWC) Format ........................................................................... 69
5-1. Port Types......................................................................................................................................... 73
5-2. P00 to P07 Block Diagram................................................................................................................ 76
5-3. P10 to P14 Block Diagram................................................................................................................ 76
5-4. P20 to P27 Block Diagram................................................................................................................ 77
5-5. P30 to P37 Block Diagram................................................................................................................ 78
5-6. P40 to P44 Block Diagram................................................................................................................ 79
5-7. P50 to P54 Block Diagram................................................................................................................ 80
5-8. P60 and P61 Block Diagram............................................................................................................. 81
5-9. P81 Block Diagram ........................................................................................................................... 82
5-10. P82 to P87 Block Diagram................................................................................................................ 82
5-11. P90 to P97 Block Diagram................................................................................................................ 83
5-12. Port Mode Register (PM0, PM4 to PM6, PM8, PM9) Format ........................................................... 86
5-13. Port Mode Register (PM2, PM3) Format .......................................................................................... 86
5-14. Pull-Up Resistor Option Register (PU0) Format ............................................................................... 87
6-1. Clock Generator Block Diagram ....................................................................................................... 89
6-2. Processor Clock Control Register (PCC) Format ............................................................................. 90
6-3. Oscillator Mode Register (OSCM) Format ........................................................................................ 91
6-4. External Circuit of Main System Clock Oscillator.............................................................................. 92
6-5. Incorrect Examples of Resonator Connection ..................................................................................93
6-6. Switching CPU Clock........................................................................................................................ 97
7-1. Timer 0 (TM0) Block Diagram........................................................................................................... 101
7-2. 16-Bit Timer Mode Control Register (TMC0) Format........................................................................ 103
7-3. Capture Pulse Control Register (CRC0) Format .............................................................................. 104
7-4. Prescaler Mode Register (PRM0) Format ........................................................................................ 105
7-5. Configuration Diagram for Pulse Width Measurement by Free-Running Counter ............................ 106
7-6. Timing of Pulse Width Measurement Operation by Free-Running Counter
and One Capture Register (with Both Edges Specified)................................................................... 106

18
LIST OF FIGURES (2/4)
Figure No. Title Page
7-7. CR0m Capture Operation with Rising Edge Specified ..................................................................... 107
7-8. Timing of Pulse Width Measurement Operation by Free-Running Counter
(with Both Edges Specified).............................................................................................................. 108
7-9. 16-Bit Timer Register Start Timing .................................................................................................... 109
7-10. Capture Register Data Retention Timing .......................................................................................... 109
8-1. Timer 1 (TM1) Block Diagram........................................................................................................... 111
8-2. Timer Clock Select Register 1 (TCL1) Format.................................................................................. 113
8-3. 8-Bit Timer Mode Control Register 1 (TMC1) Format ....................................................................... 114
8-4. Interval Timer Operation Timings...................................................................................................... 115
8-5. Timer 1 Start Timing.......................................................................................................................... 118
8-6. Timing after Compare Register Change during Timer Count Operation........................................... 118
9-1. Timer 2 (TM2) Block Diagram........................................................................................................... 119
9-2. Timer 3 (TM3) Block Diagram........................................................................................................... 120
9-3. Timer Clock Select Register 2 (TCL2) Format.................................................................................. 122
9-4. Timer Clock Select Register 3 (TCL3) Format.................................................................................. 123
9-5. 8-Bit Timer Mode Control Register n (TMCn) Format ....................................................................... 124
9-6. Interval Timer Operation Timings...................................................................................................... 125
9-7. External Event Counter Operation Timings (with Rising Edge Specified) ........................................ 128
9-8. PWM Output Operation Timing......................................................................................................... 130
9-9. Timing of Operation by Change of CRn............................................................................................ 131
9-10. Timer n Start Timing.......................................................................................................................... 132
9-11. Timing after Compare Register Change during Timer Count Operation........................................... 132
10-1. Watch Timer Block Diagram ............................................................................................................. 133
10-2. Watch Timer Mode Control Register (WTM) Format ........................................................................ 135
10-3. Operation Timing of Watch Timer/Interval Timer............................................................................... 137
11-1. Watchdog Timer Block Diagram ....................................................................................................... 139
11-2. Watchdog Timer Clock Select Register (WDCS) Format.................................................................. 141
11-3. Watchdog Timer Mode Register (WDTM) Format ............................................................................ 142
12-1. Clock Output Control Circuit Block Diagram ..................................................................................... 145
12-2. Clock Output Selection Register (CKS) Format................................................................................ 146
12-3. Port Mode Register 6 (PM6) Format................................................................................................. 147
12-4. Remote Control Output Application Example ................................................................................... 148
13-1. A/D Converter Block Diagram........................................................................................................... 149
13-2. Power-Fail Detection Function Block Diagram ................................................................................. 150
13-3. A/D Converter Mode Register (ADM1) Format................................................................................. 152
13-4. Analog Input Channel Specification Register (ADS1) Format .......................................................... 153
13-5. Power-Fail Compare Mode Register (PFM) Format ......................................................................... 154
13-6. Basic Operation of 8-Bit A/D Converter ............................................................................................ 156
13-7. Relation between Analog Input Voltage and A/D Conversion Result................................................ 157

19
LIST OF FIGURES (3/4)
Figure No. Title Page
13-8. A/D Conversion................................................................................................................................. 159
13-9. Example of Method of Reducing Current Consumption in Standby Mode ....................................... 160
13-10. Analog Input Pin Connection ............................................................................................................ 161
13-11. A/D Conversion End Interrupt Request Generation Timing.............................................................. 162
13-12. D/A Converter Mode Register (DAM1) Format ................................................................................. 163
14-1. UART Block Diagram........................................................................................................................ 165
14-2. Asynchronous Serial Interface Mode Register (ASIM) Format......................................................... 168
14-3. Asynchronous Serial Interface Status Register (ASIS) Format ........................................................ 169
14-4. Baud Rate Generator Control Register (BRGC) Format .................................................................. 170
14-5. Error Tolerance (when k = 0) including Sampling Errors .................................................................. 176
14-6. Format of Transmit/Receive Data in Asynchronous Serial Interface ................................................ 177
14-7. Timing ofAsynchronous Serial Interface Transmit Completion Interrupt .......................................... 179
14-8. Timing ofAsynchronous Serial Interface Receive Completion Interrupt........................................... 180
14-9. Receive Error Timing ........................................................................................................................ 181
15-1. SIO3 Block Diagram ......................................................................................................................... 183
15-2. Serial Operation Mode Register (CSIM) Format............................................................................... 185
15-3. Serial Operation Mode Register (CSIM) Format............................................................................... 186
15-4. Serial Operation Mode Register (CSIM) Format............................................................................... 187
15-5. Three-Wire Serial I/O Mode Timing .................................................................................................. 188
16-1. LCD Controller/Driver Block Diagram ............................................................................................... 190
16-2. LCD Clock Select Circuit Block Diagram .......................................................................................... 191
16-3. LCD Display Mode Register (LCDM) Format ................................................................................... 192
16-4. LCD Display Control Register (LCDC) Format ................................................................................. 193
16-5. Relationship between LCD Display Data Memory Contents and Segment/Common Outputs ......... 195
16-6. Common Signal Waveform ............................................................................................................... 197
16-7. Common Signal and Segment Signal Voltages and Phases ............................................................ 197
16-8. Example of Connection of LCD Drive Power Supply........................................................................ 199
16-9. 4-Time-Division LCD Display Pattern and Electrode Connections ................................................... 200
16-10. 4-Time-Division LCD Panel Connection Example ............................................................................ 201
16-11. 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) ............................................... 202
16-12. LCD Timer Control Register (LCDTM) Format ................................................................................. 203
17-1. Sound Generator Block Diagram ...................................................................................................... 205
17-2. Concept of Each Signal .................................................................................................................... 206
17-3. Sound Generator Control Register (SGCR) Format ......................................................................... 208
17-4. Sound Generator Buzzer Control Register (SGBR) Format ............................................................. 210
17-5. Sound Generator Amplitude Register (SGAM) Format..................................................................... 211
17-6. Sound Generator Output Operation Timing ...................................................................................... 212
17-7. Sound Generator Output Operation Timing ...................................................................................... 212

20
LIST OF FIGURES (4/4)
Figure No. Title Page
18-1. Meter Controller/Driver Block Diagram ............................................................................................. 213
18-2. 1-Bit Addition Circuit Block Diagram ................................................................................................. 214
18-3. Timer Mode Control Register (MCNTC) Format............................................................................... 216
18-4. Compare Control Register n (MCMPCn) Format.............................................................................. 217
18-5. Port Mode Control Register (PMC) Format ...................................................................................... 218
18-6. Restart Timing after Count Stop (Count Start→Count Stop→Count Start) ...................................... 220
18-7. Timing in 1-BitAddition Circuit Operation ......................................................................................... 221
18-8. Timing of Output with 1 Clock Shifted............................................................................................... 222
19-1. Basic Configuration of Interrupt Function ......................................................................................... 225
19-2. Interrupt Request Flag Register (IF0L, IF0H, IF1L) Format.............................................................. 228
19-3. Interrupt Mask Flag Register (MK0L, MK0H, MK1L) Format............................................................ 229
19-4. Priority Specify Flag Register (PR0L, PR0H, PR1L) Format ............................................................ 230
19-5. External Interrupt Rising Edge Enable Register (EGP),
External Interrupt Falling Edge Enable Register (EGN) Format ....................................................... 231
19-6. Prescaler Mode Register (PRM0) Format ........................................................................................ 232
19-7. Program Status Word Format ........................................................................................................... 233
19-8. Non-Maskable Interrupt Request Generation to Acknowledge Flowchart ........................................ 235
19-9. Non-Maskable Interrupt Request Acknowledge Timing .................................................................... 235
19-10. Non-Maskable Interrupt Request Acknowledge Operation............................................................... 236
19-11. Interrupt Request Acknowledge Processing Algorithm ..................................................................... 238
19-12. Interrupt Request Acknowledge Timing (Minimum Time) ................................................................. 239
19-13. Interrupt Request Acknowledge Timing (Maximum Time) ................................................................ 239
19-14. Multiple Interrupt Examples .............................................................................................................. 241
19-15. Interrupt Request Hold...................................................................................................................... 243
20-1. Oscillation Stabilization Time Select Register (OSTS) Format ......................................................... 246
20-2. HALT Mode Clear upon Interrupt Generation ................................................................................... 248
20-3. HALT Mode Clear upon RESET Input .............................................................................................. 249
20-4. STOP Mode Clear upon Interrupt Generation .................................................................................. 251
20-5. STOP Mode Clear upon RESET Input.............................................................................................. 252
21-1. Reset Function Block Diagram ......................................................................................................... 253
21-2. Timing of Reset by RESET Input ...................................................................................................... 254
21-3. Timing of Reset due to Watchdog Timer Overflow ........................................................................... 254
21-4. Timing of Reset in STOP Mode by RESET Input.............................................................................. 254
22-1. Memory Size Switching Register (IMS) Format ................................................................................ 258
22-2. Transmission Method Selection Format ........................................................................................... 259
22-3. Flashpro II Connection Using 3-Wire Serial I/O Method................................................................... 260
22-4. Flashpro II Connection Using UART Method.................................................................................... 261
22-5. Flashpro II Connection Using Pseudo 3-Wire Serial I/O Method...................................................... 261
A-1. Development Tool Configuration....................................................................................................... 280
A-2. Dimensions of TGF-080RAP (Reference) ........................................................................................ 289