
N720 Hardware User Guide
Copyright © Neoway Technology Co., Ltd v
Table of Figures
Figure 1-1 N720 block diagram............................................................................................................... 3
Figure 2-1 N720 module pin definition (Top View) ................................................................................ 5
Figure 2-2 Current peaks and voltage drops .......................................................................................... 14
Figure 2-3 Capacitors used for the power supply .................................................................................. 15
Figure 2-4 Reference design of power supply control........................................................................... 15
Figure 2-5 Reference design of power supply controlled by p-MOSFET ............................................. 16
Figure 2-6 Reference designs of separated power supply...................................................................... 17
Figure 2-7 Push switch control .............................................................................................................. 18
Figure 2-8 MCU control ........................................................................................................................ 18
Figure 2-9 N720 power-on/off sequence ............................................................................................... 19
Figure 2-10 N720 power-off sequence .................................................................................................. 19
Figure 2-11 Reset controlled by button ................................................................................................. 20
Figure 2-12 Reset circuit with triode separating.................................................................................... 20
Figure 2-13 N720 reset sequence........................................................................................................... 20
Figure 2-14 USB circuit......................................................................................................................... 21
Figure 2-15 Reference design of SIM card interface............................................................................. 22
Figure 2-16 UIM connector encapsulation ............................................................................................ 23
Figure 2-17 Reference design of the UART interface ........................................................................... 24
Figure 2-18 Recommended level shifting circuit 1................................................................................ 25
Figure 2-19 Recommended level shifting circuit 2................................................................................ 26
Figure 2-20 LED indicator driven by transistor..................................................................................... 27
Figure 2-21 RING indicator for incoming call ...................................................................................... 28
Figure 2-22 RING indicator for SMS .................................................................................................... 28
Figure 2-23 PCM connection................................................................................................................. 29
Figure 2-24 PCM synchronization timing ............................................................................................. 29
Figure 2-25 PCM data input timing....................................................................................................... 30
Figure 2-26 PCM data output timing..................................................................................................... 30
Figure 2-27 SDIO connection................................................................................................................ 32
Figure 2-28 SDIO SDR timing .............................................................................................................. 32
Figure 2-29 SDIO DDR timing ............................................................................................................. 33
Figure 2-30 32KHz clock signal timing ................................................................................................ 34
Figure 2-31 Reference design of the fast boot interface ........................................................................ 35