Neoway N20 Installation manual

N720 (Cat1) Hardware User Guide ()
N20 Hardware User Guide
Version 1.0

N20 Hardware User Guide
Copyright © Neoway Technology Co., Ltd
i
Copyright
Copyright © 2017 Neoway Technology Co., Ltd. All rights reserved.
No part of this document may be reproduced or transmitted in any form or by any means without
prior written consent of Neoway Technology Co., Ltd.
is the trademark of Neoway Technology Co., Ltd.
All other trademarks and trade names mentioned in this document are the property of their respective
holders.
Notice
This document provides guide for users to use the N20.
This document is intended for system engineers (SEs), development engineers, and test engineers.
The information in this document is subject to change without notice due to product version update
or other reasons.
Every effort has been made in preparation of this document to ensure accuracy of the contents, but all
statements, information, and recommendations in this document do not constitute a warranty of any
kind, express or implied.
Neoway provides customers complete technical support. If you have any question, please contact
your account manager or email to the following email addresses:
[e-mail]
[e-mail]
Website: http://www.neoway.com

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Revision Record
Issue
Changes
Revised By
Date
V1.0
Initial draft
He Zhizhong
2017-10

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Contents
1 Introduction to N20........................................................................................................... 1
1.1 Overview ............................................................................................................................................ 1
1.2 Block Diagram ................................................................................................................................... 1
1.3 Features .............................................................................................................................................. 2
2 Application Interfaces ...................................................................................................... 4
2.1 Specifications and Pin Definition ....................................................................................................... 4
2.2 Pin Description ................................................................................................................................... 5
2.3 Power and Control Interfaces ........................................................................................................... 10
2.3.1 VBAT ...................................................................................................................................... 10
2.3.2 VDDIO_1P8............................................................................................................................ 13
2.3.3 ON/OFF .................................................................................................................................. 13
2.3.4 RESET_N................................................................................................................................ 16
2.3.5 DTR......................................................................................................................................... 17
2.3.6 NETLIGHT ............................................................................................................................. 18
2.3.7 RING....................................................................................................................................... 18
2.4 USB Interface ................................................................................................................................... 19
2.5 UIM Card Interface .......................................................................................................................... 21
2.6 SDIO Interface ................................................................................................................................. 22
2.7 PCM Interface .................................................................................................................................. 23
2.8 I2C Interface..................................................................................................................................... 26
2.9 SPI Interface ..................................................................................................................................... 26
2.10 UART Interfaces............................................................................................................................. 27
2.11 ADC Interfaces ............................................................................................................................... 29
2.12 GPIO Interfaces .............................................................................................................................. 30
2.13 Commissioning Interface................................................................................................................ 30
2.14 Other Interfaces .............................................................................................................................. 30
3 RF Interface....................................................................................................................... 31
3.1 2G/4G RF Design and PCB Layout ................................................................................................. 31
3.2 GPS RF Design and PCB Layout ..................................................................................................... 33
3.2.1 GPS Impedance ....................................................................................................................... 33
3.2.2 Active GPS Antenna Design.................................................................................................... 33
4 Electrical Features and Reliability ............................................................................... 35
4.1 Electrical Features ............................................................................................................................ 35

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4.2 Temperature...................................................................................................................................... 35
4.3 ESD .................................................................................................................................................. 35
5 RF Features........................................................................................................................ 37
5.1 Operating Band................................................................................................................................. 37
5.2 TX Power and RX Sensitivity .......................................................................................................... 37
6 Mechanical Features........................................................................................................ 40
6.1 Dimensions....................................................................................................................................... 40
6.2 PCB Foot Print ................................................................................................................................. 41
6.3 Recommended PCB Foot Print......................................................................................................... 42
7 Mounting and Packaging............................................................................................... 43
7.1 Mounting the Module onto the Application Board ........................................................................... 43
7.2 Packaging ......................................................................................................................................... 43
8 SMT Temperature Curve ............................................................................................... 44
9 Abbreviations................................................................................................................... 45

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Table of Figures
Figure 1-1 N20 block diagram ................................................................................................................ 2
Figure 2-1 N20 module pin definition (Top View).................................................................................. 4
Figure 2-2 Current peaks and voltage drops ......................................................................................... 10
Figure 2-3 Capacitors used for the power supply...................................................................................11
Figure 2-4 Reference design of power supply control ...........................................................................11
Figure 2-5 Reference design of power supply controlled by p-MOSFET............................................. 12
Figure 2-6 Reference designs of separated power supply ..................................................................... 13
Figure 2-7 Push switch control ............................................................................................................. 14
Figure 2-8 MCU control........................................................................................................................ 14
Figure 2-9 Automatic power on ............................................................................................................ 14
Figure 2-10 N20 power-on timing......................................................................................................... 15
Figure 2-11 N20 power-off timing ........................................................................................................ 15
Figure 2-12 Reset controlled by button................................................................................................. 16
Figure 2-13 Reset circuit with triode separating ................................................................................... 16
Figure 2-14 N20 reset sequence ............................................................................................................ 17
Figure 2-15 LED indicator driven by transistor .................................................................................... 18
Figure 2-16 RING indicator for incoming call...................................................................................... 18
Figure 2-17 RING indicator for SMS ................................................................................................... 19
Figure 2-18 USB connection................................................................................................................. 20
Figure 2-19 USB connection for OTG .................................................................................................. 20
Figure 2-20 Reference design of SIM card interface ............................................................................ 21
Figure 2-21 SDIO SDR timing ............................................................................................................. 22
Figure 2-22 SDIO DDR timing............................................................................................................. 23
Figure 2-23 PCM connection ................................................................................................................ 24
Figure 2-24 I2S connection ................................................................................................................... 24
Figure 2-25 PCM SYN timing .............................................................................................................. 24
Figure 2-26 PCM data input timing ...................................................................................................... 25
Figure 2-27 PCM data output sequence ................................................................................................ 25
Figure 2-28 SPI interface timing........................................................................................................... 26
Figure 2-29 Reference design of the UART interface ........................................................................... 27

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Figure 2-30 Recommended level shifting circuit 1 ............................................................................... 28
Figure 2-31 Recommended level shifting circuit 2 ............................................................................... 29
Figure 2-32 Reference design of the fast boot interface........................................................................ 30
Figure 3-1 Reference designs of antenna matching .............................................................................. 31
Figure 3-2 Recommended RF PCB design ........................................................................................... 32
Figure 3-3 Encapsulation specifications of Murata RF connector ........................................................ 32
Figure 3-4 RF connections .................................................................................................................... 32
Figure 3-5 GPS RF structure................................................................................................................. 33
Figure 3-6 Power supply reference for active antenna .......................................................................... 34
Figure 6-1 Dimensions of N20 (unit: mm)............................................................................................ 40
Figure 6-2 N20 PCB foot print (Top View) (unit: mm) ........................................................................ 41
Figure 6-3 Recommended N20 PCB foot print (unit: mm)................................................................... 42
Figure 8-1 Temperature curve ............................................................................................................... 44

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Table of Tables
Table 1-1 N20 baseband and wireless features ....................................................................................... 2
Table 2-1 N20 dimensions ...................................................................................................................... 4
Table 2-2 IO types and level feature description..................................................................................... 5
Table 2-3 N20 pin description................................................................................................................. 6
Table 2-4 Timing parameters of SDIO interface ................................................................................... 23
Table 2-5 Timing parameters of PCM interface.................................................................................... 25
Table 2-6 Timing parameters of SPI interface ...................................................................................... 26
Table 2-7 GPIO pins ............................................................................................................................. 30
Table 4-1 N20 electric features ............................................................................................................. 35
Table 4-2 Temperature feature .............................................................................................................. 35
Table 4-3 N20 ESD features ................................................................................................................. 36
Table 5-1 N20 operating band............................................................................................................... 37
Table 5-2 N20 RF TX power ................................................................................................................ 37
Table 5-3 N20 GSM RX sensitivity ...................................................................................................... 38
Table 5-4 N20 Cat M1 QPSK RX sensitivity ....................................................................................... 38
Table 5-5 N20 Cat NB1 RX sensitivity ................................................................................................ 39

N20 Hardware User Guide
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1 Introduction to N20
1.1 Overview
N20 is an industrial-grade module developed on Qualcomm platform. Its dimensions are 23.8 mm x 25.8
mm x 2.8 mm. This module has an ultra-wide operating temperature range of -40 °C to +85 °C and
electrostatic capacity of 8kV. N20 is well applicable to develop low-power IoT terminals with the
following features:
ARM Cortex-A7 processors, 1.3 GHz main frequency, 256 KB L2 cache, 28 nm process technology
Cat M1/Cat NB1/GSM/GNSS
USB2.0/UIM/ADC/UART/SPI/I2C/PCM/SDIO/GPIO
N20 series include the following variants to meet the band requirements in different regions:
Module
Version
Network
Mode
Band
GNSS
N20
N20-US-011AS1
Cat M1
HD-FDD:B2,B4,B12, B13(Cat M1)
Support
N20-CN-011AS1
Cat M1/Cat
NB1/GSM
HD-FDD:B1,B3,B5,B8(Cat M1/Cat NB1)
TDD:B39 (Cat M1)
GSM/GPRS/EDGE:900/1800 MHz
Support
N20-CA-011AS1
Cat M1/Cat
NB1
HD-FDD:B1,B3,B5,B8
(Cat M1/Cat NB1)
Support
N20-CB-011AS1
Cat NB1
HD-FDD:B3,B5,B8 (Cat NB1)
Support
N20-EU-011AS1
Cat M1/Cat
NB1/GSM
HD-FDD:B3,B8,B20 (Cat M1/Cat NB1)
GSM/GPRS/EDGE:900/1800 MHz
Support
N20-JP-011AS1
Cat M1/Cat
NB1
HD-FDD :B1, B3, B8, B18, B19, B26
(Cat M1/Cat NB1)
Support
N20-AP-011AS1
Cat M1/Cat
NB1/GSM
HD-FDD:B3,B28(Cat M1/Cat NB1)
GSM/GPRS/EDGE:900/1800 MHz
Support
1.2 Block Diagram
Figure 1-1 shows the block diagram of N20.

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Figure 1-1 N20 block diagram
Baseband
RF transceiver
RF
Power Manager
MCP
VBAT
Interface
ADC
MAIN GNSS
GPIO
I2C
SDIOSPI
UART
USB
SIM
XO
19.2MHz
1.3 Features
Table 1-1 N20 baseband and wireless features
Specifications
Description
Power supply
VBAT: 3.3V to 4.3 V; Typical value: 3.8 V
Current in sleep mode
TBD
Current in PSM mode
TBD
Operating temperature
-40 °C to +85 °C
Processor
ARM Cortex-A7 processor
Main frequency: 1.3 GHz
256 kB L2 cache
Memory
ROM: 128MB
RAM: 64 MB
Or
ROM: 256 MB
RAM: 128 MB
Rate
GPRS: Max 85.6 Kbps(DL) / Max 85.6 Kbps(U)

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EDGE: Max 236.8 Kbps(DL)/Max 236.8 Kbps(UL)
LTE Cat M1: 375 Kbps(DL)/300 Kbps(UL)
LTE Cat NB1: 32 Kbps(DL)/72 Kbps(UL)
Transmit power
EGSM900: +33 dBm (Power Class 4)
DCS1800: +30 dBm (Power Class 1)
EDGE 900 MHz: +27 dBm (Power Class E2)
EDGE 1800 MHz: +26 dBm (Power Class E2)
LTE: +23 dBm (Power Class 3)
Antenna feature
2G/4G antenna, GNSS antenna, 50 Ω impedance
UART
At most 4 Mbps, 2 UART interfaces
UIM
1 UIM interface, 1.8V/3V dual-voltage adaptive
USB
1 high-speed USB2.0 interface
ADC
2 16-bit ADC interfaces, input voltage ranging from 0.1 V to 1.7 V
SPI
1 SPI interface, supporting only host mode
At most 50 Mbps
I2C
1 I2C interface, used to control external sensor
PCM
1 PCM interface, used to transmit digital audio
SDIO
1 SDIO interface, used to control 4-bit WLAN interface
GPIO
4 GPIOs

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2 Application Interfaces
N20 adopts 68-pin LCC encapsulation package.
2.1 Specifications and Pin Definition
Table 2-1 N20 dimensions
Specifications
N20
Dimensions
23.8±0.15 mm x 25.8±0.15 mm x 2.8±0.15 mm (H x W x D)
Weight
TBD
Package
68-pin LCC
Figure 2-1 N20 module pin definition (Top View)

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2.2 Pin Description
Table 2-2 IO types and level feature description
IO Type
B
Digital I/O, COMS logic level
DO
Digital output, COMS logic level
DI
Digital input, COMS logic level
PO
Power output
PI
Power input
AO
Analog output
AI
Analog input
Level feature
P1
Dual-voltage, 1.8V or 2.85V
1.8V level feature:
VIH=1.26V~2.1V, VIL=-0.3V~0.36V
VOH=1.44V~1.8V, VOL=0V~0.4V
2.85V level feature
VIH=2V~3.15V, VIL=-0.3V~0.57V
VOH=2.28V~2.85V, VOL=0V~0.4V
P3
1.8V digital IO voltage
VIH min=1.2V, VIL max= 0.3V
VOH min=1.35V, VOL max=0.45V
P6
Level for USB2.0 data interface
Vmin=2.97V, V max=3.5V, V typ=3.08V

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Table 2-3 N20 pin description
Name
Pin
I/O
Function
Level Feature (V)
Power
Domain
Remarks
Power Supply
VBAT
20, 21, 22
PI
Main power supply
Vmax=4.3 V
Supply a maximum current of 2 A.
VDDIO _1P8
17
PO
1.8 V power supply
Vnorm=1.8 V;
Imax=50 mA;
1.8 V
Used for level shifting and to supply power
for IO.
Leave this pin unconnected if it is not used.
GND
1, 4, 18, 19, 23,
24, 34, 35, 42,
52, 53, 55, 57,
66, 68
GND
Ensure that all GND pins are grounded.
Control Interfaces
RESET_N
13
DI
Reset input
P3
1.8 V
Low level triggers the reset.
PWRKEY
14
DI
Power ON/OFF
P3
1.8 V
Low level triggers the ON state.
The level at the pin is 0.8 V by default.
DTR
15
DI
Sleep mode control
P3
1.8V
Low level triggers sleep mode.
Leave this pin unconnected if it is not used.
RING
50
DO
Incoming call ring
P3
1.8 V
Leave this pin unconnected if it is not used.
NETLIGHT
51
DO
Network status indicator
control
P3
1.8 V
Leave this pin unconnected if it is not used.
UART
UART0_TX
9
DO
UART data transmit
P3
1.8 V
Data transmission
Leave these pins unconnected if they are
not used.
UART0_RX
10
DI
UART data receive
P3
1.8 V

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UART0_RTS
11
DI
Request to send
P3
1.8 V
Leave these pins unconnected if they are
not used.
UART0_CTS
12
DO
Clear to send
P3
1.8 V
UART1_RTS
58
DI
Request to send
P3
1.8 V
Leave these pins unconnected if they are
not used.
UART1_CTS
59
DO
Clear to send
P3
1.8 V
UART1_RX
60
DI
UART data receive
P3
1.8 V
Data transmission
Leave these pins unconnected if they are
not used.
UART1_TX
61
DO
UART data transmit
P3
1.8 V
UIM
VUIM
29
PO
UIM1 power supply output
IO max =50 mA
1.8 V/2.85 V
UIM_DATA
30
IO
UIM1 data I/O
P1
1.8 V/2.85 V
Connected to UIM1_VCC through a 10 kΩ
pull-up resistor
UIM_CLK
31
DO
UIM1 clock output
P1
1.8 V/2.85 V
UIM_RESET
32
DO
UIM1 reset
P1
1.8 V/2.85 V
UIM_PRESENT
33
DI
UIM1 detect
P3
1.8 V
USB
USB_VBUS
25
PI
USB voltage test
3.3 V~5.2 V,
typically 5 V
Used for firmware download and data
transmission
Differential trace for DM and DP with 90 Ω
impedance
USB_HS_DM
26
IO
USB data negative signal
P6
USB_HS_DP
27
IO
USB data positive signal
P6
USB _ID
28
AI
Master and slave device
detect
P3
1.8 V
Leave this pin unconnected if it is not used.
ADC
ADC1
2
AI
Analog-to-digital signal
conversion
Vmax=1.7 V;
Vmin=0.1 V
1.8 V
16-bit, detectable voltage range: 0.1 V to
1.7 V

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ADC2
3
AI
Analog-to-digital signal
conversion
Vmax=1.7 V;
Vmin=0.1 V
1.8 V
I2C
I2C_SCL
44
B
I2C clock
P3
1.8V
Pulled up by a 2.2 kΩresistor internally
I2C_SDA
43
B
I2C data
P3
1.8V
Pulled up by a 2.2 kΩ resistor internally
Sleep mode control
PCM_SYNC
45
B
PCM sync signal
P3
1.8V
Leave this pin unconnected if it is not used.
PCM_CLK
46
DO
PCM clock signal
P3
1.8V
Leave this pin unconnected if it is not used.
PCM_DIN
47
DI
PCM data input
P3
1.8V
Leave this pin unconnected if it is not used.
PCM_DOUT
48
DO
PCM data output
P3
1.8V
Leave this pin unconnected if it is not used.
I2S_MCLK
49
DO
I2S main clock
P3
1.8V
Default frequency: 12.288 MHz
SDIO
SDC_CMD
36
B
Control signal of SDIO
interface
P3
1.8V
Leave this pin unconnected if it is not used.
SDC_CLK
37
DO
Clock signal of SDIO
interface
P3
1.8V
Leave this pin unconnected if it is not used.
SDC_DATA_0
38
B
SDIO data bit 0
P3
1.8V
Leave this pin unconnected if it is not used.
SDC_DATA_1
39
B
SDIO data bit 1
P3
1.8V
Leave this pin unconnected if it is not used.
SDC_DATA_2
40
B
SDIO data bit 2
P3
1.8V
Leave this pin unconnected if it is not used.
SDC_DATA_3
41
B
SDIO data bit 3
P3
1.8V
Leave this pin unconnected if it is not used.
SPI
SPI_CLK
62
DO
Clock signal
P3
1.8V
Leave this pin unconnected if it is not used.
SPI_MISO
63
DI
Master input, slave output
P3
1.8V
Leave this pin unconnected if it is not used.

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SPI_MOSI
64
DO
Master output, slave input
P3
1.8V
Leave this pin unconnected if it is not used.
SPI_CS_N
65
DO
Chip select
P3
1.8V
Leave this pin unconnected if it is not used.
GPIO
GPIO_1
5
B
GPIO with interrupt
P3
1.8V
Leave this pin unconnected if it is not used.
GPIO_2
6
B
GPIO with interrupt
P3
1.8V
Leave this pin unconnected if it is not used.
GPIO_3
7
B
GPIO with interrupt
P3
1.8V
Leave this pin unconnected if it is not used.
GPIO_4
8
B
GPIO
P3
1.8V
Do not connect this pin to the power supply
through a pull-up resistor before the
module is started.
Leave this pin unconnected if it is not used.
Antenna
RF_ANT_GPS
54
GPS antenna
50 Ω impedance
RF_ANT_MAIN
67
Main antenna
50 Ω impedance
Other Pins
EXT_GPS_LNA
_EN
56
DO
GPS LNA enable
P3
1.8V
Leave this pin unconnected if it is not used.
FORCE_USB_B
OOT
48
DI
Forcible upgrade control
P3
1.8 V
Connect a 10 kΩ pull-up resistor to 1.8V,
and the module enters USB download
mode
Leave this pin unconnected if it is not used.

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2.3 Power and Control Interfaces
Name
Pin
I/O
Function
Remarks
VBAT
20, 21, 22
PI
Power supply input
3.3 V to 4.3 V (typical value: 3.8 V)
VDDIO_1P8
17
PO
1.8 V power supply
output
Power supply for IO level shifting circuit.
Load capability: <50 mA
Added ESD protection when using this pin.
RESET_N
13
DI
Reset input
Low level triggers reset
PWRKEY
14
DI
Power ON/OFF
Low level triggers the ON status
DTR
15
DI
Sleep mode control
Low level triggers sleep mode.
Leave this pin unconnected if it is not used.
RING
50
DO
Incoming call ring
Leave this pin unconnected if it is not used.
NETLIGHT
51
DO
Network status
indicator control
Leave this pin unconnected if it is not used.
2.3.1 VBAT
VBAT is the power supply input pin of the module. Its input voltage ranges from 3.3 V to 4.3 V and the
typical value is 3.8 V. In addition to baseband, it supplies power to RF power amplifier. The performance
of the VBAT power supply is a critical path to module's performance and stability. The peak input current
at the VBAT pin can be up to 2A when the signal is weak and the module works at the maximum
transmitting power. The voltage will encounter a drop in such a situation. The module might restart if the
voltage drops lower than 3.3 V.
Figure 2-2 Current peaks and voltage drops
Keep the voltage above 3.3 V
3.3 V
0 ms 3.7 ms 7.4 ms 10.7 ms T
2 A
Voltage
Input
current
3.8 V

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The reference design of the VBAT power supply is shown as below:
Figure 2-3 Capacitors used for the power supply
N20
D1
C1 C2 C3 C4 C5
VBAT
Test point
I_max
Power supply
R1
In Figure 2-3, use TVS at D1 to enhance the performance of the module during a burst. SMF5.0AG
(Vrwm=5 V&Pppm=200 W) is recommended. Place it close to the module. A large bypass tantalum
capacitor (220 μF or 100 μF) or aluminum capacitor (470 μF or 1000 μF) is expected at C1 to reduce
voltage drops during bursts together with C2 (10 μF ceramics capacitor).In addition, add 0.1 μF, 100 pF,
and 33 pF filter capacitors to enhance the stability of the power supply. R1 is a bleeder resistor that is used
in scenarios with high requirements for the switch of power supply.
The module might fail to reset or power on/off in remote or unattended applications, or in an environment
with great electromagnetic interference (EMI). A controllable power supply is preferable if used in harsh
conditions. Use the EN pin on the LDO or DC/DC chipset to control the switch of the power supply as
shown in Figure 2-4 if a 5 V power supply is used.
MIC29302WU in Figure 2-4 is an LDO and outputs a maximum current of 3 A to ensure the performance
of the module.
Figure 2-4 Reference design of power supply control
VDC_5V
VBAT
100 uF
TAN
0.1 uF
TVS
5V
10 uF
470uF
TAN
100K
47.5K
VOUT
MIC29302WU
EN
VIN ADJ 0.1 uF 100pF 33pF
PWR_EN
R1

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The alternative way is to use an enhancement-mode p-MOSFET and NPN triode to control the module's
power, as shown in Figure 2-5.
In Figure 2-5, the module is turned on when PWR_EN is set to high level.
Figure 2-5 Reference design of power supply controlled by p-MOSFET
VBAT
R2
D1
10uF 100pF 33pF
0.1uF
R1
0.1uF
10uF
Q1
Q2
R4
2KΩ
10KΩ
100KΩ
VCCIN_3V9
PWR_EN
G
S D
B
C
E
VGS across Q1 is equal to the voltage across R4. When high level is input at PWR_EN, the circuit is open
at Q2 and there is current at R4. VCE across Q2 is very small while VGS is almost equal to that of
VCCIN_3V9. VS is greater than VGand VGS is smaller than VGS(th) (where VGS (th) is the Gate Threshold
Voltage), so the circuit is open at Q1 and the current travels from source to drain.
In case that the MCU can supply a high voltage greater than VCCIN_3V9|, Q2 is not needed.
Reference components:
Q1 can be IRML6401 or low Rds (on) p-MOSFET, which has higher, withstand voltage and drain
current.
Q2: a common NPN tripolar transistor, e.g. MMBT3904; or a digital NPN tripolar transistor, e.g.
DTC123. If digital tripolar transistor is used, delete R1 and R2.
The module works in burst mode that generates voltage drops on power supply. Furthermore, this results
in a 217 Hz TDD noise through power (One of the way generating noise. Another way is through RF
radiation). Analog parts, especially the audio circuits, are subjected to this noise, known as a "buzz noise"
in GSM systems. To prevent other parts from being affected, use separated power supplies. The module
shall be supplied by an independent power, like a DC/DC or LDO. See Figure 2-6.
DC/DC or LDO should output rated peak current larger than 3A.
The inductor used in Reference Design (b), should be a power inductor and have very low resistance. The
value of 10 μH, with average current ability greater than 2 A and low DC resistance, is recommended.