Neoway N75 Installation manual

N75
Hardware User Guide
Issue 1.0
Date 2019-05-23
Neoway Product Document

N75
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
i
Copyright © Neoway Technology Co., Ltd 2019. All rights reserved.
No part of this document may be reproduced or transmitted in any form or by any means without prior written
consent of Neoway Technology Co., Ltd.
is the trademark of Neoway Technology Co., Ltd.
All other trademarks and trade names mentioned in this document are the property of their respective
holders.
Notice
This document provides guide for users to use N75.
This document is intended for system engineers (SEs), development engineers, and test engineers.
THIS GUIDE PROVIDES INSTRUCTIONS FOR CUSTOMERS TO DESIGN THEIR APPLICATIONS.
PLEASE FOLLOW THE RULES AND PARAMETERS IN THIS GUIDE TO DESIGN AND COMMISSION.
NEOWAY WILL NOT TAKE ANY RESPONSIBILITY OF BODILY HURT OR ASSET LOSS CAUSED BY
IMPROPER OPERATIONS.
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE DUE TO
PRODUCT VERSION UPDATE OR OTHER REASONS.
EVERY EFFORT HAS BEEN MADE IN PREPARATION OF THIS DOCUMENT TO ENSURE ACCURACY
OF THE CONTENTS, BUT ALL STATEMENTS, INFORMATION, AND RECOMMENDATIONS IN THIS
DOCUMENT DO NOT CONSTITUTE A WARRANTY OF ANY KIND, EXPRESS OR IMPLIED.
Neoway provides customers complete technical support. If you have any question, please contact your
account manager or email to the following email addresses:
[email protected]
[email protected]
Website: http://www.neoway.com

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Hardware User Guide
Copyright © Neoway Technology Co., Ltd
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Contents
1 About N75..................................................................................................1
1.1 Product Overview......................................................................................................................... 1
1.2 Block Diagram.............................................................................................................................. 2
1.3 Basic Features ............................................................................................................................. 3
2 Module Pins...............................................................................................5
2.1 Pad Layout ................................................................................................................................... 5
2.2 Pin Description ............................................................................................................................. 6
3 Application Interfaces ..............................................................................14
3.1 Power Interface .......................................................................................................................... 14
3.1.1 VBAT.................................................................................................................................. 14
3.1.2 VDD_1P8........................................................................................................................... 18
3.2 Control Interfaces....................................................................................................................... 19
3.2.1 PWRKEY_N ...................................................................................................................... 19
3.2.2 RESET_N .......................................................................................................................... 21
3.3 Peripheral Interfaces .................................................................................................................. 23
3.3.2 USB ................................................................................................................................... 23
3.3.3 USIM.................................................................................................................................. 25
3.3.4 UART................................................................................................................................. 27
3.3.5 SDC ................................................................................................................................... 30
3.3.6 I2S/PCM ............................................................................................................................ 33
3.3.7 SPI..................................................................................................................................... 39
3.3.8 I2C ..................................................................................................................................... 40
3.4 Network and Connection............................................................................................................ 44
3.4.1 Ethernet ............................................................................................................................. 44
3.4.2 WLAN ................................................................................................................................ 47
3.4.3 Bluetooth ........................................................................................................................... 50
3.5 RF Interface................................................................................................................................ 51
3.5.1 ANT_MAIN/ANT_DIV antenna interface ........................................................................... 52
3.5.2 ANT_GNSS Interface ........................................................................................................ 54
3.5.3 Antenna Assembling.......................................................................................................... 57
3.6 GPIO .......................................................................................................................................... 58
3.7 MUX Interfaces .......................................................................................................................... 59
3.8 Other Interfaces ......................................................................................................................... 62
3.8.1 GNSS_LNA_EN ................................................................................................................ 62
3.8.2 ADC ................................................................................................................................... 62
3.8.3 RING.................................................................................................................................. 62
3.8.4 DTR ................................................................................................................................... 63
3.8.5 USB_BOOT ....................................................................................................................... 65
4 Electric Feature and Reliability ................................................................66
4.1 Electric Features ........................................................................................................................ 66

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4.2 Temperature Features................................................................................................................ 68
4.3 ESD Protection........................................................................................................................... 69
5 RF Features.............................................................................................70
5.1 Operating Bands ........................................................................................................................ 70
5.2 TX Power and RX Sensitivity ..................................................................................................... 71
5.3 GNSS Feature............................................................................................................................ 72
6 Mechanical Features ...............................................................................74
6.1 Dimensions................................................................................................................................. 74
6.2 Label........................................................................................................................................... 75
6.3 Pack ........................................................................................................................................... 75
6.3.1 Reel&Tape ......................................................................................................................... 75
6.3.2 Moisture............................................................................................................................. 77
7 Mounting the Module onto the Application Board ....................................78
7.1 Bottom Dimensions .................................................................................................................... 78
7.2 Application Foot Print ................................................................................................................. 79
7.3 Stencil......................................................................................................................................... 79
7.4 Solder Paste............................................................................................................................... 79
7.5 SMT Furnace Temperature Curve.............................................................................................. 80
8 Safety Recommendations .......................................................................81
Conformity and Compliance ....................................................................82
A.1 Approvals ................................................................................................................................... 82
A.2 American Notice......................................................................................................................... 82
A.2.1 Modify................................................................................................................................ 82
A.2.2 FCC Class A Digital Device Notice ................................................................................... 82
A.2.3 FCC Class B Digital Device Notice ................................................................................... 82
Abbreviation ............................................................................................84

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Hardware User Guide
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Table of Figures
Figure 1-1 Block Diagram .................................................................................................................. 2
Figure 2-1 N75 pin definition (Top View)............................................................................................ 5
Figure 3-1 Current peaks and voltage drops (GSM/GPRS) ............................................................ 15
Figure 3-2 Recommended design 1................................................................................................. 15
Figure 3-3 Recommended design 2................................................................................................. 16
Figure 3-4 Recommended design 3................................................................................................. 17
Figure 3-5 Recommended design 4................................................................................................. 17
Figure 3-6 Reference design of startup controlled by button........................................................... 19
Figure 3-7 Reference design of startup controlled by MCU............................................................. 20
Figure 3-8 Reference design of automatic start once powered up .................................................. 20
Figure 3-9 N75 on/off timing............................................................................................................. 21
Figure 3-10 Reset controlled by button............................................................................................ 22
Figure 3-11 Reset circuit with triode separating............................................................................... 22
Figure 3-12 Reset timing of N75 ...................................................................................................... 22
Figure 3-13 USB connection ............................................................................................................ 24
Figure 3-14 Reference design of USB OTG function....................................................................... 24
Figure 3-15 Reference design of USIM card interface..................................................................... 26
Figure 3-16 Reference design of UART connection (with flow control) ........................................... 27
Figure 3-17 Reference design of UART connection (without flow control) ...................................... 27
Figure 3-18 Recommended level shifting circuit 1........................................................................... 28
Figure 3-19 Recommended level shifting circuit 2........................................................................... 29
Figure 3-20 Recommended level shifting circuit 3........................................................................... 30
Figure 3-21 SD connection .............................................................................................................. 31
Figure 3-22 SDC SDR timing ........................................................................................................... 32
Figure 3-23 SDC DDR timing........................................................................................................... 33
Figure 3-24 I2S connection .............................................................................................................. 34
Figure 3-25 I2S timing...................................................................................................................... 35

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Figure 3-26 PCM connection ........................................................................................................... 36
Figure 3-27 PCM sync signal timing in primary mode ..................................................................... 36
Figure 3-28 PCM data input timing in primary mode ....................................................................... 36
Figure 3-29 PCM data output timing in primary mode ..................................................................... 37
Figure 3-30 PCM sync signal timing in auxiliary mode .................................................................... 37
Figure 3-31 PCM data input timing in auxiliary mode ...................................................................... 38
Figure 3-32 PCM data output timing in auxiliary mode.................................................................... 38
Figure 3-33 SPI connection.............................................................................................................. 39
Figure 3-34 SPI timing ..................................................................................................................... 40
Figure 3-35 I2Cconnection............................................................................................................... 41
Figure 3-36 I2C data transmission................................................................................................... 42
Figure 3-37 I2C timing...................................................................................................................... 42
Figure 3-38 SGMII connection ......................................................................................................... 45
Figure 3-39 Connection between MDIO and PHY........................................................................... 46
Figure 3-40 MDIO input timing......................................................................................................... 46
Figure 3-41 MDIO output timing....................................................................................................... 46
Figure 3-42 WLAN connection......................................................................................................... 48
Figure 3-43 SDIO SDR timing.......................................................................................................... 49
Figure 3-44 SDIO DDR timing.......................................................................................................... 49
Figure 3-45 Bluetooth connection .................................................................................................... 51
Figure 3-46 L network ...................................................................................................................... 52
Figure 3-47 Split capacitor network.................................................................................................. 52
Figure 3-48 Pi network ..................................................................................................................... 53
Figure 3-49 Recommended RF PCB design 1 ................................................................................ 54
Figure 3-50 GNSS RF structure....................................................................................................... 54
Figure 3-51 Reference Design of Passive GNSS Antenna.............................................................. 55
Figure 3-52 Reference design of active GNSS antenna.................................................................. 56
Figure 3-53 Reference layout of GNSS antenna traces .................................................................. 57
Figure 3-54 Specifications of MM9329-2700RA1 ............................................................................ 58
Figure 3-55 RF connections............................................................................................................. 58
Figure 3-56 Pulse wave for an incoming call ................................................................................... 62

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Figure 3-57 RING indicator for SMS ................................................................................................ 63
Figure 3-58 Process of entering sleep mode ................................................................................... 63
Figure 3-59 Incoming call service process....................................................................................... 64
Figure 3-60 Outgoing call service process....................................................................................... 64
Figure 3-61 Process of exiting from sleep mode ............................................................................. 64
Figure 3-62 Reference design of USB_BOOT................................................................................. 65
Figure 6-1 N75 dimensions .............................................................................................................. 74
Figure 6-2 N75 label......................................................................................................................... 75
Figure 7-1 Bottom view .................................................................................................................... 78
Figure 7-2 Recommended Application Foot Print (Top View) .......................................................... 79
Figure 7-3 SMT furnace temperature curve..................................................................................... 80

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Hardware User Guide
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Table of Tables
Table 1-1 Variant and frequency bands.............................................................................................. 1
Table 2-1 IO types and level features................................................................................................. 6
Table 2-2 Pin Description ................................................................................................................... 7
Table 3-1 VDD_1P8 electrical features ............................................................................................ 19
Table 3-2 Compliant standards of peripheral interfaces................................................................... 23
Table 3-3 SD card feature parameters............................................................................................. 31
Table 3-4 Timing parameters of SDC interface................................................................................ 33
Table 3-5 Timing parameters of I2S interface .................................................................................. 35
Table 3-6 PCM work modes ............................................................................................................. 35
Table 3-7 Parameters of PCM timing in primary mode .................................................................... 37
Table 3-8 Parameters of PCM timing in auxiliary mode................................................................... 38
Table 3-9 Timing parameters of SPI interface.................................................................................. 40
Table 3-10 I2C feature parameters .................................................................................................. 41
Table 3-11 I2C timing parameters (standard mode)......................................................................... 42
Table 3-12 I2C timing parameters (fast mode)................................................................................. 43
Table 3-13 I2C timing parameters (fast mode plus) ......................................................................... 43
Table 3-14 SDIO/WLAN feature parameters.................................................................................... 47
Table 3-15 Timing parameters of SDIO/WLAN interface ................................................................. 49
Table 3-16 MUX pins........................................................................................................................ 59
Table 4-1 Electric features................................................................................................................ 66
Table 4-2 Current consumption of N75 ............................................................................................ 66
Table 4-3 Temperature features ....................................................................................................... 68
Table 4-4 ESD protection features ................................................................................................... 69
Table 5-1 Operating Bands .............................................................................................................. 70
Table 5-2 RF TX power .................................................................................................................... 71

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Hardware User Guide
Copyright © Neoway Technology Co., Ltd
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About This Document
Scope
This document is applicable to N75 series.
It defines the features, indicators, and test standards of the N75 module and provides reference for the
hardware design of each interface.
Reference designs in this document are only for reference. Customers should design applications
based on the actual scenarios and conditions.Please contact Neoway FAE if you have any question or
doubt.
Audience
This document is intended for system engineers (SEs), development engineers, and test engineers.
Change History
Issue
Date
Change
Changed By
1.0
2019-03
Initial draft
Wang Qiang
Conventions
Symbol
Indication
This warning symbol means danger. You are in a situation that could cause fatal
device damage or even bodily damage.
Means reader be careful. In this situation, you might perform an action that could
result in module or product damages.
Means note or tips for readers to use the module

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Hardware User Guide
Copyright © Neoway Technology Co., Ltd
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Related Documents
Neoway_N75_Datasheet
Neoway_N75_Product_Specifications
Neoway_N75_AT_Command_Manual
Neoway_N75_EVK_User_Guide
Neoway Module Reflow Manufacturing Recommendations

N75
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
1
1 About N75
N75 is an industrial-grade 4G module developed on Qualcomm platform. It supports
GSM/GPRS/EDGE, WCDMA R99 to DC-HSPA+, and LTE Cat4. With various hardware interfaces and
optional GNSS functions, N75 is well applicable to wireless metering terminals, in-vehicle terminals,
POS, industrial routers, and other IoT terminals.
1.1 Product Overview
N75 series include multiple variants. Table 1-1 lists the variants and frequency bands supported.
Table 1-1 Variant and frequency bands
Variant
Region
Category
Band
GNSS1
NA
North
America
Cat4
FDD-LTE: B2, B4, B5, B7, B12, B13, B142,
B25, B26, B66, B71
UMTS: B2, B4, B5
GSM/GPRS/EDGE: 850/1900 MHz
support
A
North
America
Cat4
FDD-LTE: B2, B4, B5, B12, B142, B66
UMTS: B2, B4, B5
support
E
European
Union
Cat4
FDD-LTE: B1, B3, B5, B7, B8, B20, B28
TDD-LTE: B38, B40
UMTS: B1, B5, B8
GSM/GPRS/EDGE: 850/1900 MHz
support
JP
Japan
Cat4
FDD-LTE: B1, B3, B8, B18, B19, B26
TDD-LTE: B41
UMTS: B1, B6, B8, B19
support
1
GNSS optional for all above variants
2
B14 and GNSS are exclusive to each other

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1.2 Block Diagram
N75 consists of the following functionality units:
⚫Baseband
⚫MCP
⚫Power management unit
⚫19.2MHz crystal oscillator
⚫RF section
⚫Digital interfaces (USIM, SPI, I2C, SGMII, SDIO, ADC, GPIO, UART, USB)
Figure 1-1 Block Diagram
VBAT
RF transceiver
19.2M
crystal
RF Front-end
(PA/ASW/DUP/SAW)
ANT_MAIN ANT_DIV ANT_GNSS
PWRKEY
RESET
MCP
NAND
LPDDR2
SDRAM
Base Band
MEMORY SUPPORT
RFFE I/F S
CONNECTIVITY
SPMI
VDDs
TRX
TRX&MIPI
Input PM
Output PM
Interfaces
ADC
PM_GPIOs
VBAT
UART
SPI
I2C
ADC
USB
SGMII
SDIO
UIM
GPIO
I2S/PCM
Power
Manager
VDDs for
MCP
VDDs
for PA/ASW

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1.3 Basic Features
Parameter
Description
Physical features
Dimensions: (30.0±0.1) mm ×(28.0±0.1) mm ×(2.8±0.2) mm
Package: 100-pin LGA
Weight: around 5.3g
Temperature
ranges
Operating: -35°C to +75°C
Extended: -40°C to +85°C
Storage: -45°C to +90°C
Operating voltage
VBAT: 3.3V to 4.3V, TYP: 3.8V
Current
Flight mode
1.24mA
Sleep Mode
GSM DRX=6: 2.2mA
GSM DRX=9: 1.45mA
WCDMA DRX=2: 2.64mA
WCDMA DRX=9: 1.54mA
LTE (Paging Cycle 320ms): 6.5mA
LTE (Paging Cycle 2.56s): 1.67mA
Active
VBAT: 2A Max
Processor
ARM Cortex-A7 processor, 1.3 GHz main frequency
Memory
ROM+RAM:
⚫2Gb+1Gb
⚫4Gb+2Gb
Operating Bands
See Table 1-1.
Wireless rate
GPRS: Max 85.6 Kbps(DL) / Max 85.6 Kbps(UL)
EDGE: Max 236.8Kbps(DL) / Max 236.8Kbps(UL)
WCDMA: DC-HSPA+, Max 42Mbps (DL)/Max 5.76Mbps (UL)
FDD-LTE: non-CA cat4, Max 150 Mbps(DL)/Max 50 Mbps (UL)
Transmit power
GSM850: (33dBm±2dB) (Power Class 4)
PCS1900: (30dBm±2dB) (Power Class 1)
EDGE 850MHz: (27dBm±3dB) (Power Class E2)
EDGE1900MHz: (26dBm±3dB) (Power Class E2)
UMTS: (24dBm+1/-3dB) (Power Class 3)
LTE: (23dBm±2dB) (Power Class 3)

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Application
Interfaces
2G/3G/4G antenna interface, diversity antenna interface, GNSS antenna
interface
50Ω impedance
Two UART interfaces: one is an ordinary serial port, and one is used for
Bluetooth by default
One I2C interface, supporting only host mode
One SPI interface, supporting only host mode and max. 50 MHz
One USIM interface, 1.8V/3V
One USB2.0 interface, OTG function requires external 5V DC-DC
Two 15-bit ADC interfaces, detectable voltage ranging from 0.1 to 1.7V
One I2S/PCM interface, used to connect to CODEC chipset
One SDIO interface, used for WLAN
One SGMII/MDIO interface, used for Ethernet
Four GPIO interfaces
AT Command
Neoway extended commands
Data
PPP, RNDIS, ECM, RMNET
Protocol
TCP, UDP, MQTT, FTP/FTPS, HTTP/HTTP(S), SSL, TLS
Certification
approval
FCC, PTCRB, AT&T, CE-R, GCF, RoHS, NCC*, RCM*

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2 Module Pins
There are 100 pins on N75 and their pads are introduced in LGA package.
2.1 Pad Layout
Figure 2-1 shows the pad layout of N75.
Figure 2-1 N75 pin definition (Top View)

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2.2 Pin Description
Table 3-1 lists the definition of IO types
Table 2-1 IO types and level features
IO Type
B
Digital input/output, COMS logic level
DO
Digital output, COMS logic level
DI
Digital input, COMS logic level
PO
Power output
PI
Power supply input
AI
Analog input
AIO
Analog input/output
OD
Open drain
Level Feature
I/O
Pin type
Voltage Feature
Current Feature
P1
USIM1 interface voltage,
compatible with 1.8V/3V
1.8V
VIH=1.26V~2.1V
VIL=-0.3V~0.36V
VOH=1.44V~1.8V
VOL=0V~0.4V
3V
VIH=2V~3.15V,
VIL=-0.3V~0.57V
VOH=2.28V~2.85V
VOL=0V~0.4V
2 mA to 16 mA,
adjustable at a
spacing of 2 mA
P2
USIM2 and MDIO interface
voltage, compatible with
1.8V/3V
1.8V
VIH=1.26V~2.1V
VIL=-0.3V~0.36V
VOH=1.44V~1.8V
VOL=0V~0.4V
3V
VIH=2V~3.15V,
VIL=-0.3V~0.57V
VOH=2.28V~2.85V
VOL=0V~0.4V
P3
1.8V digital IO voltage
VIH min=1.2V, VIL max= 0.3V
VOH min=1.35V, VOL max= 0.45V
P4
SDC interface voltage,
compatible with 1.8V/2.85V
1.8V:
VIH=1.27V~2V,
VIL= -0.3V~0.58V
VOH=1.4V~1.8V,
VOL=0V~0.45V
3V:
VIH=1.8V~3.15V,
VIL= -0.3V~0.7V
VOH=2.1V~2.85V,
VOL=0V~0.36V

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P7
GPIO of PM chipset can be
divided into three types: 1.2V,
1.8V, and VBAT. They are
used for output because their
IO cannot adapt automatically.
VIH=0.65*VIO~(VIO+0.3V),
VIL=-0.3V~0.35*VIO
VOH=(VIO-0.45)V~VIO
VOL=0V~0.45V
(VIO is GPIO voltage, 1.2V/1.8V/VBAT)
When VIO is 1.8V
High: 0.9mA
Medium: 0.6mA
Low: 0.15 mA
P8
Level of GPIO for power
management chipset, fixed to
1.8V
VIH=1.26V~2.1V
VIL=-0.3V~0.63V
VOH=1.35V~1.8V
VOL=0V~0.45V
High: 0.9mA
Medium: 0.6mA
Low: 0.15 mA
Table 2-2 Pin Description
Signal
Pin
I/O
Function
Level
Feature
Remarks
Power Interface
VBAT
27, 28,
29
PI
Main power supply input
Vmax=4.3V
Supply at most 2A
DVDD_1P8
45
PO
1.8V power output
Vnorm=1.8V
Imax=50mA
Used only for level
shifting.
Leave this pin
floating if it is not
used.
DVDD_XO_1P8
53
PO
1.8V power output
Vnorm=1.8V
Imax=20mA
Used to pull up the
crystal oscillator of
external WLAN
module
Leave this pin
floating if it is not
used.
GND
1, 14, 17, 20, 26,
30, 31, 44, 49,
74, 75, 77, 91,
93, 95, 97, 98,
99, 100
Ground
Connect all GND
pins to the ground
plane.
Control Interfaces
RESET_N
32
DI
Module reset input
P3
Triggered by low
level to reset the
module.

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PWRKEY_N
33
DI
ON/OFF button
(recommended)
P3
Triggered by low
level
Embedded with
diode switch and a
200 kΩ pull-up
resistor
Around 0.8V when
the pin is floating
UART Interface
UART5_TXD
46
DO
UART5 data transmitting
P3
Used for data
transmission.
Leave them
floating if they are
not used.
UART5_RXD
47
DI
UART5 data receiving
P3
USIM interface
USIM1_VCC
35
PO
USIM1 power output
P1 Imax=50mA
The module is
compatible with
1.8V and 2.85V
USIM cards.
Connect DATA pin
to USIM_VCC
through a 10 kΩ
pull-up resistor.
Leave them
floating if they are
not used.
USIM1_DATA
36
IO
USIM data IO
P1
USIM1_CLK
37
DO
USIM1 clock output
P1
USIM1_RESET
38
DO
USIM1 reset
P1
USIM1_DET
39
DI
USIM1 detect
P3
USB interface
VBUS
40
PI
Charging voltage check
3.3V to 5.2V,
TYP: 5V
In compliance with
USB2.0 protocol
Used for firmware
download and data
transmission.
USB_DM
41
AIO
USB data minus
USB_DP
42
AIO
USB data plus
USB_ID
43
AI
OTG detect
Leave this pin
floating if it is not
used.
ADC interface
ADC2
88
AI
Analog-to-digital signal
conversion
Vmax=1.7V;
Vmin=0.1V
15-bit, detectable
voltage ranging
from 0.1V to 1.7V
Leave this pin

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floating if it is not
used.
ADC1
89
AI
Analog-to-digital signal
conversion
Vmax=1.7V;
Vmin=0.1V
15-bit, detectable
voltage ranging
from 0.1V to 1.7V
Leave this pin
floating if it is not
used.
SGMII interface
SGMII_TX_N
15
AO
SGMII transmit minus
Leave this pin
floating if it is not
used.
SGMII_TX_P
16
AO
SGMII transmit plus
SGMII_RX_N
18
AI
SGMII receive minus
SGMII_RX_P
19
AI
SGMII receive plus
MDIO Control Interfaces
SGMII_VCC
21
PO
USIM2 power output
P2
For MDIO data line
to be connected
through a pull-up
resistor
SGMII_MDIO_CLK
22
DO
SGMII clock output
P2
Multiplexed as
USIM2
Leave them
floating if they are
not used.
SGMII_MDIO_DATA
23
B
SGMII data IO
P2
ETH_REST_N
24
DO
Ethernet PHY reset
P2
ETH_INT_N
25
DI
Ethernet PHY interrupt
P2
I2C interface
I2C_4_SDA
81
OD
I2C data signal
P3
It is connected
through a 2.2 kΩ
internal pull-up
resistor.
Leave this pin
floating if it is not
used.
I2C_4_SCL
82
OD
I2C clock
P3
I2S/PCM interface
I2S_1_SCLK
9
DO
I2S serial clock
P3
Multiplexed as
PCM
Leave this pin
floating if it is not
used.
I2S_1_DOUT
10
DO
I2S data transmit
P3
I2S_1_DIN
11
DI
I2S data receive
P3
I2S_1_WS
12
B
I2S word select
P3

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I2S_MCLK
64
DO
I2S main clock
P3
12.288 MHz by
default
WLAN interface
WLAN_SDIO_CMD
54
B
SDIO data IO
P3
Leave this pin
floating if it is not
used.
WLAN_SDIO_CLK
55
DO
SDIO clock
P3
Leave this pin
floating if it is not
used.
WLAN_SDIO_DATA_0
56
B
SDIO data0 IO
P3
Leave this pin
floating if it is not
used.
WLAN_SDIO_DATA_1
57
B
SDIO data1 IO
P3
Leave this pin
floating if it is not
used.
WLAN_SDIO_DATA_2
58
B
SDIO data2 IO
P3
Leave this pin
floating if it is not
used.
WLAN_SDIO_DATA_3
59
B
SDIO data3 IO
P3
Leave this pin
floating if it is not
used.
WAKE_ON_WIRELESS
60
DO
WLAN wakeup
P3
Leave this pin
floating if it is not
used.
WLAN_SLEEP_CLK
61
DO
Wi-Fi sleep clock
P8
Leave this pin
floating if it is not
used.
WLAN_EN
62
DO
WLAN enable signal
P3
Leave this pin
floating if it is not
used.
WLAN_PWR_EN
63
DO
Control of WLAN
external power
P8
Leave this pin
floating if it is not
used.
WCI_LTE_RXD/USB_B
OOT
48
DI
LTE/WLAN co-exist
UART data
receive/forcible
download mode control
P3
Do not pull this pin
high during the
startup of the
module.
Otherwise, the
module enters