Neoway N720 Installation manual

N720 OpenLinux
Hardware User Guide
Issue 1.4
Date 2019-03-25
Neoway Product Document

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
i
Copyright © Neoway Technology Co., Ltd 2019. All rights reserved.
No part of this document may be reproduced or transmitted in any form or by any means without prior written
consent of Neoway Technology Co., Ltd.
is the trademark of Neoway Technology Co., Ltd.
All other trademarks and trade names mentioned in this document are the property of their respective
holders.
Notice
This document provides guide for users to use N720 OpenLinux.
This document is intended for system engineers (SEs), development engineers, and test engineers.
THIS GUIDE PROVIDES INSTRUCTIONS FOR CUSTOMERS TO DESIGN THEIR APPLICATIONS.
PLEASE FOLLOW THE RULES AND PARAMETERS IN THIS GUIDE TO DESIGN AND COMMISSION.
NEOWAY WILL NOT TAKE ANY RESPONSIBILITY OF BODILY HURT OR ASSET LOSS CAUSED BY
IMPROPER OPERATIONS.
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE DUE TO
PRODUCT VERSION UPDATE OR OTHER REASONS.
EVERY EFFORT HAS BEEN MADE IN PREPARATION OF THIS DOCUMENT TO ENSURE ACCURACY
OF THE CONTENTS, BUT ALL STATEMENTS, INFORMATION, AND RECOMMENDATIONS IN THIS
DOCUMENT DO NOT CONSTITUTE A WARRANTY OF ANY KIND, EXPRESS OR IMPLIED.
Neoway provides customers complete technical support. If you have any question, please contact your
account manager or email to the following email addresses:
[email protected]
[email protected]
Website: http://www.neoway.com

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
ii
Contents
1 About N720 OpenLinux ............................................................................. 1
1.1 Product Overview......................................................................................................................... 1
1.2 Block Diagram.............................................................................................................................. 2
1.3 Basic Features ............................................................................................................................. 3
2 Module Pins............................................................................................... 6
2.1 Pad Layout ................................................................................................................................... 6
3 Application Interfaces .............................................................................. 15
3.1 Power Interface .......................................................................................................................... 15
3.1.1 VBAT.................................................................................................................................. 15
3.1.2 VDD_1P8........................................................................................................................... 19
3.2 Control Interfaces....................................................................................................................... 20
3.2.1 PWRKEY_N ...................................................................................................................... 20
3.2.2 RESET_N .......................................................................................................................... 23
3.3 Peripheral Interfaces .................................................................................................................. 24
3.3.2 USB ................................................................................................................................... 24
3.3.3 USIM.................................................................................................................................. 26
3.3.4 UART................................................................................................................................. 27
3.3.5 SDC ................................................................................................................................... 31
3.3.6 I2S/PCM ............................................................................................................................ 35
3.3.7 SPI..................................................................................................................................... 39
3.3.8 I2C ..................................................................................................................................... 41
3.4 Network and Connection............................................................................................................ 45
3.4.1 Ethernet ............................................................................................................................. 45
3.4.2 WLAN ................................................................................................................................ 48
3.4.3 Bluetooth ........................................................................................................................... 51
3.5 RF Interface................................................................................................................................ 52
3.5.1 ANT_MAIN/ANT_DIV antenna interface ........................................................................... 53
3.5.2 ANT_GNSS Interface ........................................................................................................ 55
3.5.3 Antenna Assembling.......................................................................................................... 58
3.6 GPIO .......................................................................................................................................... 59
3.7 MUX Interfaces .......................................................................................................................... 60
3.8 Other Interfaces ......................................................................................................................... 63
3.8.1 GNSS_LNA_EN ................................................................................................................ 63
3.8.2 ADC ................................................................................................................................... 63
3.8.3 RING.................................................................................................................................. 63
3.8.4 DTR ................................................................................................................................... 64
3.8.5 USB_BOOT ....................................................................................................................... 66
4 Electric Feature and Reliability ................................................................ 67
4.1 Electric Features ........................................................................................................................ 67
4.2 Temperature Features................................................................................................................ 67

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Hardware User Guide
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4.3 ESD Protection........................................................................................................................... 68
5 RF Features............................................................................................. 69
5.1 Operating Bands ........................................................................................................................ 69
5.2 TX Power and RX Sensitivity ..................................................................................................... 70
5.3 GNSS Feature............................................................................................................................ 72
6 Mechanical Features ............................................................................... 74
6.1 Dimensions................................................................................................................................. 74
6.2 Label........................................................................................................................................... 75
6.3 Pack ........................................................................................................................................... 75
6.3.1 Tray.................................................................................................................................... 76
6.3.2 Moisture............................................................................................................................. 77
7 Mounting N720 onto the Application Board ............................................. 78
7.1 Bottom Dimensions .................................................................................................................... 78
7.2 Application Foot Print ................................................................................................................. 79
7.3 Stencil......................................................................................................................................... 79
7.4 Solder Paste............................................................................................................................... 79
7.5 SMT Furnace Temperature Curve.............................................................................................. 80
8 Safety Recommendations ....................................................................... 81
A Conformity and Compliance .................................................................... 82
A.1 Approvals ................................................................................................................................... 82
A.2 Chinese Notice........................................................................................................................... 82
A.2.1 CCC Class A Digital Device Notice................................................................................... 82
A.2.2 Environmental Protection Notice....................................................................................... 82
B Abbreviation ............................................................................................ 83

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
iv
Table of Figures
Figure 1-1 Block Diagram .................................................................................................................. 3
Figure 2-1 N720 OpenLinux pin definition (Top View) ....................................................................... 6
Figure 3-1 Current peaks and voltage drops ................................................................................... 16
Figure 3-2 Recommended design 1................................................................................................. 16
Figure 3-3 Recommended design 2................................................................................................. 17
Figure 3-4 Recommended design 3................................................................................................. 18
Figure 3-5 Recommended design 4................................................................................................. 18
Figure 3-6 Reference design of startup controlled by button........................................................... 21
Figure 3-7 Reference design of startup controlled by MCU............................................................. 21
Figure 3-8 Reference design of automatic start once powered up .................................................. 21
Figure 3-9 N720 on/off timing........................................................................................................... 22
Figure 3-10 Reset controlled by button............................................................................................ 23
Figure 3-11 Reset circuit with triode separating............................................................................... 23
Figure 3-12 Reset timing of N720 OpenLinux.................................................................................. 23
Figure 3-13 USB connection ............................................................................................................ 25
Figure 3-14 Reference design of USB OTG function....................................................................... 25
Figure 3-15 Reference design of USIM card interface..................................................................... 26
Figure 3-16 Reference design of UART connection (with flow control) ........................................... 28
Figure 3-17 Reference design of UART connection (without flow control) ...................................... 28
Figure 3-18 Recommended level shifting circuit 1........................................................................... 29
Figure 3-19 Recommended level shifting circuit 2........................................................................... 30
Figure 3-20 Recommended level shifting circuit 3........................................................................... 31
Figure 3-21 SD connection .............................................................................................................. 32
Figure 3-22 SDC SDR timing ........................................................................................................... 33
Figure 3-23 SDC DDR timing........................................................................................................... 34
Figure 3-24 I2S connection .............................................................................................................. 35
Figure 3-25 I2S timing...................................................................................................................... 36

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
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Figure 3-26 PCM connection ........................................................................................................... 37
Figure 3-27 PCM sync signal timing in primary mode ..................................................................... 37
Figure 3-28 PCM data input timing in primary mode ....................................................................... 37
Figure 3-29 PCM data output timing in primary mode ..................................................................... 37
Figure 3-30 PCM sync signal timing in auxiliary mode .................................................................... 38
Figure 3-31 PCM data input timing in auxiliary mode ...................................................................... 38
Figure 3-32 PCM data output timing in auxiliary mode.................................................................... 39
Figure 3-33 SPI connection.............................................................................................................. 40
Figure 3-34 SPI timing ..................................................................................................................... 41
Figure 3-35 I2Cconnection............................................................................................................... 42
Figure 3-36 I2C data transmission................................................................................................... 42
Figure 3-37 I2C timing...................................................................................................................... 43
Figure 3-38 SGMII connection ......................................................................................................... 45
Figure 3-39 Connection between MDIO and PHY........................................................................... 47
Figure 3-40 MDIO input timing......................................................................................................... 47
Figure 3-41 MDIO output timing....................................................................................................... 47
Figure 3-42 WLAN connection ......................................................................................................... 49
Figure 3-43 SDIO SDR timing.......................................................................................................... 50
Figure 3-44 SDIO DDR timing.......................................................................................................... 50
Figure 3-45 Bluetooth connection .................................................................................................... 52
Figure 3-46 L network ...................................................................................................................... 53
Figure 3-47 Split capacitor network.................................................................................................. 53
Figure 3-48 Pi network ..................................................................................................................... 54
Figure 3-49 Recommended RF PCB design 1 ................................................................................ 55
Figure 3-50 Recommended RF PCB design 2 ................................................................................ 55
Figure 3-51 GNSS RF structure....................................................................................................... 55
Figure 3-52 Reference Design of Passive GNSS Antenna.............................................................. 56
Figure 3-53 Reference design of active GNSS antenna.................................................................. 57
Figure 3-54 Reference layout of GNSS antenna traces .................................................................. 58
Figure 3-55 Specifications of MM9329-2700RA1 ............................................................................ 59
Figure 3-56 RF connections............................................................................................................. 59

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
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Figure 3-57 Pulse wave for an incoming call ................................................................................... 63
Figure 3-58 RING indicator for SMS ................................................................................................ 64
Figure 3-59 Process of entering sleep mode ................................................................................... 64
Figure 3-60 Incoming call service process....................................................................................... 65
Figure 3-61 Outgoing call service process....................................................................................... 65
Figure 3-62 Process of exiting from sleep mode ............................................................................. 65
Figure 3-63 Reference design of USB_BOOT................................................................................. 66
Figure 6-1 N720 dimensions ............................................................................................................ 74
Figure 6-2 N720 Openlinux label ..................................................................................................... 75
Figure 6-3 N720 OpenLinux packing with vacuum bag and tray ..................................................... 76
Figure 6-4 Packaging process ......................................................................................................... 76
Figure 7-1 Bottom view .................................................................................................................... 78
Figure 7-2 Recommended Application Foot Print (Top View) .......................................................... 79
Figure 7-3 SMT furnace temperature curve ..................................................................................... 80

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
vii
Table of Tables
Table 1-1 Variant and frequency bands.............................................................................................. 1
Table 2-1 IO types and level features................................................................................................. 7
Table 2-2 Pin Description ................................................................................................................... 8
Table 3-1 VDD_1P8 electrical features ............................................................................................ 20
Table 3-2 Compliant standards of peripheral interfaces................................................................... 24
Table 3-3 SD card feature parameters............................................................................................. 32
Table 3-4 Timing parameters of SDC interface ................................................................................ 34
Table 3-5 Timing parameters of I2S interface .................................................................................. 36
Table 3-6 PCM work modes ............................................................................................................. 36
Table 3-7 Parameters of PCM timing in primary mode .................................................................... 38
Table 3-8 Parameters of PCM timing in auxiliary mode................................................................... 39
Table 3-9 Timing parameters of SPI interface.................................................................................. 41
Table 3-10 I2C feature parameters .................................................................................................. 41
Table 3-11 I2C timing parameters (standard mode)......................................................................... 43
Table 3-12 I2C timing parameters (fast mode)................................................................................. 44
Table 3-13 I2C timing parameters (fast mode plus)......................................................................... 44
Table 3-14 SDIO/WLAN feature parameters.................................................................................... 48
Table 3-15 Timing parameters of SDIO/WLAN interface ................................................................. 50
Table 3-16 MUX pins........................................................................................................................ 60
Table 4-1 Electric features................................................................................................................ 67
Table 4-2 Temperature features ....................................................................................................... 67
Table 4-3 ESD protection features ................................................................................................... 68
Table 5-1 Operating Bands .............................................................................................................. 69
Table 5-2 RF TX power .................................................................................................................... 70
Table 5-3 RF RX sensitivity .............................................................................................................. 71

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
viii
About This Document
Scope
This document is applicable to N720 OpenLinux series.
It defines the features, indicators, and test standards of the N720 OpenLinux module and provides
reference for the hardware design of each interface.
Reference designs in this document are only for reference. Customers should design applications
based on the actual scenarios and conditions.Please contact Neoway FAE if you have any question or
doubt.
Audience
This document is intended for system engineers (SEs), development engineers, and test engineers.
Change History
Issue
Date
Change
Changed By
1.0
2017-02
Initial draft
Dong Liuting
1.1
2017-04
Updated pin definition and description
Modified the description of reset pin
Updated internal connection of GPS
Dong Liuting
1.2
2017-07
Added LTE B12 for NA variant
Added memory and size tolerance
Modified the description of PWRKEY, RESET, UART,
and VDDIO_1P8
Added MUX description of some pins
Modified description
Dong Liuting
1.3
2018-01
Updated variants and bands
Added GNSS features
Added description of SGMII, WLAN, and SD
interfaces
Dong Liuting

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
ix
Modified the resistance of a resistor in level shifting
circuit 2.
Modified description
1.4
2019-01
Modified the pin definition according to Neoway
Module Pin Definition
Updated Chapter 3.
Updated the block diagram of N720
Added description of USB OTG
Updated packaging process
Modified description
Dong Liuting
Conventions
Symbol
Indication
This warning symbol means danger. You are in a situation that could cause fatal
device damage or even bodily damage.
Means reader be careful. In this situation, you might perform an action that could
result in module or product damages.
Means note or tips for readers to use the module
Related Documents
Neoway_N720 OpenLinux_Datasheet
Neoway_N720 OpenLinux_Product_Specifications
Neoway_N720 OpenLinux_User_Manual
Neoway_N720 OpenLinux_SDK_Developer_Guide
Neoway_N720 OpenLinux_Upgrade_Guide
Neoway_N720 OpenLinux_EVK_User_Guide
Neoway Module Reflow Manufacturing Recommendations

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
1
1 About N720 OpenLinux
N720 OpenLinux is an industrial-grade 4G module developed on Qualcomm platform. It supports
GSM/GPRS/EDGE, CDMA2000®1x/1xAdvanced/1xEV-DOrA, WCDMAR99 to DC-HSPA+, TD-
SCDMA, and LTE Cat4. With various hardware interfaces and optinal GNSS functions, N720
OpenLinux is well applicable to Mi-Fi, in-vehicle terminals, POS, industrial routers, and other IoT
terminals.
1.1 Product Overview
N720 OpenLinux series include multiple variants. Table 1-1 lists the variants and frequency bands
supported.
Table 1-1 Variant and frequency bands
Version
Region
Category
Band
GNSS1
CA
China
Cat4
FDD-LTE: B1, B3, B5, B82
FDD-LTE: B38, B39, B40, B41
TD-SCDMA: B34, B39
UMTS: B1, B8
EV-DO: BC0
CDMA 1x BC0
GSM/GPRS/EDGE: 900/1800 MHz
support
CB
China/India
Cat4
FDD-LTE: B1, B3, B5, B82
FDD-LTE: B38, B39, B40, B41
TD-SCDMA: B34, B39
UMTS: B1, B8
GSM/GPRS/EDGE: 900/1800 MHz
support
EA
Europe
Cat4
FDD-LTE: B1, B3, B53, B7, B8, B20
FDD-LTE: B403
support
1
GNSS optional for all above variants
2
LTE B8 of CA and CB variants does not support diversity receive.
3
LTE B5 and B40 of EA variant does not support diversity receive.

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
2
UMTS: B1, B8
GSM/GPRS/EDGE: 900/1800 MHz
NA
North
America
Cat4
FDD-LTE: B2, B4, B5, B7, B12, B17
UMTS: B2, B4, B5
GSM/GPRS/EDGE: 850/900/1800/1900 MHz
support
TWN
Taiwan
Cat4
FDD-LTE: B1, B3, B7, B8, B28
UMTS: B1, B8
GSM/GPRS/EDGE: 900/1800 MHz
support
1.2 Block Diagram
N720 OpenLinux consists of the following functionality units:
Baseband
MCP
Power management unit
19.2MHz crystal oscillator
RF section
Digital interfaces (UIM, SPI, I2C, SGMII, SDIO, ADC, GPIO, UART, USB)

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
3
Figure 1-1 Block Diagram
VBAT
RF transceiver
19.2M
crystal
RF Front-end
(PA/ASW/DUP/SAW)
ANT_MAIN ANT_DIV ANT_GNSS
PWRKEY
RESET
MCP
NAND
LPDDR2
SDRAM
Base Band
MEMORY SUPPORT
RFFE I/F S
CONNECTIVITY
SPMI
VDDs
TRX
TRX&MIPI
Input PM
Output PM
Interfaces
ADC
PM_GPIOs
VBAT
UART
SPI
I2C
ADC
USB
SGMII
SDIO
UIM
GPIO
I2S/PCM
Power
Manager
VDDs for
MCP
VDDs
for PA/ASW
1.3 Basic Features
Parameter
Description
Physical features
Dimensions: 30 mm * 28 mm * 2.8 mm
Weight: around 5.1g
Temperature
ranges
Operating: -35°C to +75°C
Extended: -40℃ to +85℃
Storage: -45°C to +90°C
Operating voltage
VBAT: 3.3V to 4.3V, TYP: 3.8V

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Hardware User Guide
Copyright © Neoway Technology Co., Ltd
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Operating Current
Sleep4: < 4 mA
Idle5: < 20 mA
Operating mode6(LTE networks)
Current in data service: about 250 mA
Current in max. RX power: about 580 mA (FDD-LTE), 380 mA (TDD-LTE)
MIPS processor
ARM Cortex-A7 processor, 1.3 GHz main frequency
Memory
ROM+RAM: 4Gb+2Gb
Operating Bands
See Table 1-1.
Wireless rate
GPRS: Max 85.6 Kbps(DL) / Max 85.6 Kbps(UL)
EDGE: Max 236.8Kbps(DL) / Max 236.8Kbps(UL)
CDMA: Max 3.1Mbps (DL) / Max 1.8Mbps (UL)
WCDMA: DC-HSPA+，Max 42Mbps (DL)/Max 5.76Mbps (UL)
TD-SCDMA: Max 4.2 Mbps (DL)/Max 2.2 Mbps (UL)
FDD-LTE: non-CA cat4, Max 150 Mbps(DL)/Max 50 Mbps (UL)
TDD-LTE: non-CA cat4, Max 130 Mbps(DL)/Max 35 Mbps(UL)
Transmit power
GSM850: +33dBm (Power Class 4)
EGSM900: +33dBm (Power Class 4)
DCS1800: +30dBm (Power Class 1)
PCS1900: +30dBm (Power Class 1)
EDGE 850MHz: +27dBm (Power Class E2)
EDGE 900MHz: +27dBm (Power Class E2)
EDGE1800MHz: +26dBm (Power Class E2)
EDGE1900MHz: +26dBm (Power Class E2)
TD-SCDMA: +23 dBm (Power Class 3)
CDMA 1X/EVDO: +23dBm (Power Class 3)
UMTS: +23dBm (Power Class 3)
LTE: +23dBm (Power Class 3)
Application
2G/3G/4G antenna, diversity antenna, GNSS antenna
4
Sleep mode is the low power consumption state the module enters. In this mode, peripheral interfaces of the
module are disabled but the RF function works. If a call or SMS message incomes, the module exits from sleep mode.
After the call or voice is end, the module enters sleep mode again.
5
Idle mode indicates the status of no service when the module is running.
6
Current in operating mode indicates the current during data communication. For currents of other network modes
and bands, see N720 Current Test Report.

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
5
Interfaces
50Ω impedance
Two UART interfaces: one is an ordinary serial port, and one is used for
Bluetooth by default
One I2C interface, supporting only host mode
One SPI interface, supporting only host mode and max. 50 Mbps
One USIM interface, 1.8V/2.85V
One USB2.0 interface, OTG function requires external 5V DC-DC
Two 15-bit ADC interfaces, detectable voltage ranging from 0.1 to 1.7V
One I2S/PCM interface, used to connect to CODEC chipset
One SDIO interface, used to control WLAN
One SGMII/MDIO interface, used for Ethernet
Four GPIO interfaces
AT Command
Neoway extended commands
Data
PPP, RNDIS, ECM, RMNET
Protocol
TCP, UDP, MQTT, FTP/FTPS, HTTP/HTTP(S), SSL, TLS
Certification
approval
CCC, SRRC, RoSH, CE

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
6
2 Module Pins
There are 100 pins on N720 OpenLinux and their pads are introduced in LGA package.
2.1 Pad Layout
Figure 2-1 shows the pad layout of N720 OpenLinux.
Figure 2-1 N720 OpenLinux pin definition (Top View)

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Hardware User Guide
Copyright © Neoway Technology Co., Ltd
7
Pin Description
Table 3-1 lists the definition of IO types
Table 2-1 IO types and level features
IO Type
B
Digital input/output, COMS logic level
DO
Digital output, COMS logic level
DI
Digital input, COMS logic level
PO
Power output
PI
Power supply input
AI
Analog input
AIO
Analog input/output
OD
Open drain
Level Feature
I/O
Pin type
Voltage Feature
Current Feature
P1
USIM1 interface voltage,
compatible with 1.8V/2.85V
1.8V Voltage
Feature
VIH=1.26V~2.1V
VIL=-0.3V~0.36V
VOH=1.44V~1.8V
VOL=0V~0.4V
2.85V Voltage
Feature
VIH=2V~3.15V,
VIL=-0.3V~0.57V
VOH=2.28V~2.85V
VOL=0V~0.4V
2 mA to 16 mA,
adjustable at a
spacing of 2 mA
P2
USIM2 and MDIO interface
voltage, compatible with
1.8V/2.85V
1.8V Voltage
Feature
VIH=1.26V~2.1V
VIL=-0.3V~0.36V
VOH=1.44V~1.8V
VOL=0V~0.4V
2.85V Voltage
Feature
VIH=2V~3.15V,
VIL=-0.3V~0.57V
VOH=2.28V~2.85V
VOL=0V~0.4V
P3
1.8V digital IO voltage
VIH min=1.2V, VIL max= 0.3V
VOH min=1.35V, VOL max= 0.45V

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Hardware User Guide
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P4
SDC interface voltage,
compatible with 1.8V/2.85V
1.8V Voltage
Feature:
VIH=1.27V~2V,
VIL= -0.3V~0.58V
VOH=1.4V~1.8V,
VOL=0V~0.45V
2.85V Voltage
Feature:
VIH=1.8V~3.15V,
VIL= -0.3V~0.7V
VOH=2.1V~2.85V,
VOL=0V~0.36V
P7
GPIO of PM chipset can be
divided into three types: 1.2V,
1.8V, and VBAT. They are
used for output because their
IO cannot adapt automatically.
VIH=0.65*VIO~(VIO+0.3V),
VIL=-0.3V~0.35*VIO
VOH=(VIO-0.45)V~VIO
VOL=0V~0.45V
(VIO is GPIO voltage, 1.2V/1.8V/VBAT)
When VIO is 1.8V
High: 0.9mA
Medium: 0.6mA
Low: 0.15 mA
P8
Level of GPIO for power
management chipset, fixed to
1.8V
VIH=1.26V~2.1V
VIL=-0.3V~0.63V
VOH=1.35V~1.8V
VOL=0V~0.45V
High: 0.9mA
Medium: 0.6mA
Low: 0.15 mA
Table 2-2 Pin Description
Signal
Pin
I/O
Function
Level
Feature
Remarks
Power Interface
VBAT
27, 28,
29
PI
Main power supply input
Vmax=4.3V
Supply at most 2A
DVDD_1P8
45
PO
1.8V power output
Vnorm=1.8V
Imax=50mA
Used only for level
shifting.
Leave this pin
floating if it is not
used.
DVDD_XO_1P8
53
PO
1.8V power output
Vnorm=1.8V
Imax=20mA
Used to pull up the
crystal oscillator of
external WLAN
module
Leave this pin
floating if it is not
used.

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
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GND
1, 14, 17, 20, 26,
30, 31, 44, 49,
74, 75, 77, 91,
93, 95, 97, 98,
99, 100
Ground
Connect all GND
pins to the ground
plane.
Control Interfaces
RESET_N
32
DI
Module reset input
P3
Triggered by low
level to reset the
module.
PWRKEY_N
33
DI
ON/OFF button
(recommended)
P3
Triggered by low
level
Embedded with
diode switch and a
200 kΩ pull-up
resistor
Around 0.8V when
the pin is floating
PWRKEY_P
34
DI
Module ON/OFF control
P3
Triggered by high
level
Embedded a 200
kΩ pull-down
resistor
Connect it to the
ground plane if it is
not used
UART Interface
UART5_TXD
46
DO
UART5 data transmitting
P3
Used for data
transmission.
Leave them
floating if they are
not used.
UART5_RXD
47
DI
UART5 data receiving
P3
USIM interface
USIM1_VCC
35
PO
USIM1 power output
P1 Imax=50mA
The module is
compatible with
1.8V and 2.85V
USIM cards.
Connect DATA pin
to USIM_VCC
through a 10 kΩ
pull-up resistor.
Leave them
USIM1_DATA
36
IO
USIM data IO
P1
USIM1_CLK
37
DO
USIM1 clock output
P1
USIM1_RESET
38
DO
USIM1 reset
P1
USIM1_DET
39
DI
USIM1 detect
P3

N720 OpenLinux
Hardware User Guide
Copyright © Neoway Technology Co., Ltd
10
floating if they are
not used.
USB interface
VBUS
40
PI
Charging voltage check
3.3V to 5.2V,
TYP: 5V
In compliance with
USB2.0 protocol
Used for firmware
download and data
transmission.
USB_DM
41
AIO
USB data minus
USB_DP
42
AIO
USB data plus
USB_ID
43
AI
OTG detect
Leave this pin
floating if it is not
used.
ADC interface
ADC2
88
AI
Analog-to-digital signal
conversion
Vmax=1.7V;
Vmin=0.1V
15-bit, detectable
voltage ranging
from 0.1V to 1.7V
Leave this pin
floating if it is not
used.
ADC1
89
AI
Analog-to-digital signal
conversion
Vmax=1.7V;
Vmin=0.1V
15-bit, detectable
voltage ranging
from 0.1V to 1.7V
Leave this pin
floating if it is not
used.
SGMII interface
SGMII_TX_N
15
AO
SGMII transmit minus
Leave this pin
floating if it is not
used.
SGMII_TX_P
16
AO
SGMII transmit plus
SGMII_RX_N
18
AI
SGMII receive minus
SGMII_RX_P
19
AI
SGMII receive plus
MDIO Control Interfaces
USIM2_VCC
21
PO
USIM2 power output
P2
For MDIO data line
to be connected
through a pull-up
resistor
Compatible with
1.8 V/3 V UIM card
SGMII_MDIO_CLK
22
DO
SGMII clock output
P2
Multiplexed as